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From: Andrew Jeffery <andrew@codeconstruct.com.au>
To: Willie Thai <wthai@nvidia.com>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org,
	dkodihalli@nvidia.com,  gpiccoli@igalia.com, joel@jms.id.au,
	kees@kernel.org, krzk+dt@kernel.org,  leohu@nvidia.com,
	linux-arm-kernel@lists.infradead.org,
	 linux-aspeed@lists.ozlabs.org, linux-hardening@vger.kernel.org,
	 linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org,
	robh@kernel.org,  tingkaic@nvidia.com, tony.luck@intel.com,
	harrys@nvidia.com
Subject: Re: Re: [PATCH v4 2/3] dt-bindings: pinctrl: aspeed,ast2600-pinctrl
Date: Tue, 01 Apr 2025 11:22:16 +1030	[thread overview]
Message-ID: <71bced05e26ae1a5f15a7335928f3f71bde143f1.camel@codeconstruct.com.au> (raw)
In-Reply-To: <20250331171857.262649-1-wthai@nvidia.com>

Hi Willie,

On Mon, 2025-03-31 at 17:18 +0000, Willie Thai wrote:
> > > Add EMMCG5 enum to compatible list of pinctrl binding for emmc
> > > enabling.
> > > 
> > > Cc: Andrew Jeffery <andrew@codeconstruct.com.au>
> > > Signed-off-by: Willie Thai <wthai@nvidia.com>
> > > ---
> > >  .../devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml     
> > > | 1
> > > +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git
> > > a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-
> > > pinctrl.yaml
> > > b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-
> > > pinctrl.yaml
> > > index 80974c46f3ef..cb75e979f5e0 100644
> > > --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-
> > > pinctrl.yaml
> > > +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-
> > > pinctrl.yaml
> > > @@ -276,6 +276,7 @@ additionalProperties:
> > >          - BMCINT
> > >          - EMMCG1
> > >          - EMMCG4
> > > +        - EMMCG5
> > 
> > What pin configuration does this correspond to for the eMMC
> > controller?
> > These groups aren't arbitrary, they correspond to the 1, 4 and 8-
> > bit
> > bus modes.
> > 
> > You may have added this squash a warning, but I suspect the pinctrl
> > configuration in your devicetree is incorrect.
> > 
> > Andrew
> > 
> 
> Thanks for your feedback !
> We want to exclude AC5 pin in the default EMMCG4 pin group, because
> that pin is used for other purpose.

Okay, sure.

> We define a new group called EMMCG5 as:
> GROUP_DECL(EMMCG5, AB4, AA4, AC4, AA5, Y5, AB5, AB6)
> The bus mode is still 4-bit mode.
> Could you please advise if we can use the name "EMMCG5" ?

Why is EMMCG5 an intuitive name? It doesn't make sense to me for what
you're trying to achieve. It's probably better if we rethink the
functions and groups to make them a little more fine-grained, perhaps

- EMMCDAT1
- EMMCDAT4
- EMMCDAT8
- EMMCWP
- EMMCCD

and then you request what's appropriate, rather than create groups that
exclude a specific function/pin (such as card detect).

Maybe you should drop the eMMC node from your devicetree for now, and
add it back once we've sorted out the pinctrl side of things in a
separate series.

Andrew


  reply	other threads:[~2025-04-01  0:52 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-24 17:59 [PATCH v4 0/3] Add device tree for Nvidia's GB200NVL BMC Willie Thai
2025-03-24 17:59 ` [PATCH v4 1/3] dt-bindings: arm: aspeed: add " Willie Thai
2025-03-25  7:17   ` Krzysztof Kozlowski
2025-03-24 17:59 ` [PATCH v4 2/3] dt-bindings: pinctrl: aspeed,ast2600-pinctrl Willie Thai
2025-03-25  7:17   ` Krzysztof Kozlowski
2025-03-28  0:46   ` Andrew Jeffery
2025-03-31 17:18     ` Willie Thai
2025-04-01  0:52       ` Andrew Jeffery [this message]
2025-03-24 17:59 ` [PATCH v4 3/3] ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMC Willie Thai
2025-03-25  3:13 ` [PATCH v4 0/3] " Rob Herring (Arm)

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