[PATCH v0 0/5] Add initial AST2700 SoC support

[PATCH v0 0/5] Add initial AST2700 SoC support

[Ryan Chen]

This patch series introduces initial support for the Aspeed AST2700 SoC
and the AST2700 Evaluation Board (EVB) to the Linux kernel. The AST2700
is the 7th generation Baseboard Management Controller (BMC) SoC from Aspeed,
featuring improved performance, enhanced security, and expanded I/O
capabilities compared to previous generations.

The patchset includes the following changes:
- Device tree bindings for AST2700 boards.
- Addition of the AST2700 platform to the Kconfig menu.
- Basic device tree for the AST2700 SoC.
- Device tree for the AST2700-EVB.
- Updated defconfig to enable essential options for AST2700.

Ryan Chen (5):
  dt-bindings: arm: aspeed: Add AST2700 board compatible
  arm64: Kconfig: Add Aspeed SoC family (ast2700) platform option
  arm64: dts: aspeed: Add initial AST2700 SoC device tree
  arm64: dts: aspeed: Add AST2700 EVB device tree
  arm64: configs: Update defconfig for AST2700 platform support

 .../bindings/arm/aspeed/aspeed.yaml           |   5 +
 arch/arm64/Kconfig.platforms                  |   6 +
 arch/arm64/boot/dts/Makefile                  |   1 +
 arch/arm64/boot/dts/aspeed/Makefile           |   4 +
 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi     | 380 ++++++++++++++++++
 arch/arm64/boot/dts/aspeed/ast2700-evb.dts    |  54 +++
 arch/arm64/configs/defconfig                  |   1 +
 7 files changed, 451 insertions(+)
 create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
 create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
 create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts

-- 
2.34.1

[PATCH v0 1/5] dt-bindings: arm: aspeed: Add AST2700 board compatible

[Ryan Chen]

Add device tree compatible string for AST2700 based boards
("aspeed,ast2700-evb" and "aspeed,ast2700") to the Aspeed SoC
board bindings. This allows proper schema validation and
enables support for AST2700 platforms.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
index 01333ac111fb..660529c81af9 100644
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -102,5 +102,10 @@ properties:
               - quanta,s6q-bmc
               - ufispace,ncplite-bmc
           - const: aspeed,ast2600
+      - description: AST2700 based boards
+        items:
+          - enum:
+              - aspeed,ast2700-evb
+          - const: aspeed,ast2700
 
 additionalProperties: true
-- 
2.34.1

Re: [PATCH v0 1/5] dt-bindings: arm: aspeed: Add AST2700 board compatible

[Krzysztof Kozlowski]

On 12/06/2025 12:09, Ryan Chen wrote:
> Add device tree compatible string for AST2700 based boards
> ("aspeed,ast2700-evb" and "aspeed,ast2700") to the Aspeed SoC
> board bindings. This allows proper schema validation and
> enables support for AST2700 platforms.
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
Align with your colleagues. This is not v0, but vX+1. And X was already
3 since you sent it!

https://lore.kernel.org/all/20241212155237.848336-4-kevin_chen@aspeedtech.com/

Best regards,
Krzysztof

RE: [PATCH v0 1/5] dt-bindings: arm: aspeed: Add AST2700 board compatible

[Ryan Chen]

> Subject: Re: [PATCH v0 1/5] dt-bindings: arm: aspeed: Add AST2700 board
> compatible
> 
> On 12/06/2025 12:09, Ryan Chen wrote:
> > Add device tree compatible string for AST2700 based boards
> > ("aspeed,ast2700-evb" and "aspeed,ast2700") to the Aspeed SoC board
> > bindings. This allows proper schema validation and enables support for
> > AST2700 platforms.
> >
> > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> > ---
> Align with your colleagues. This is not v0, but vX+1. And X was already
> 3 since you sent it!
> 
Got it, will go for v4, thanks the instruction.

> https://lore.kernel.org/all/20241212155237.848336-4-kevin_chen@aspeedtec
> h.com/
> 
> Best regards,
> Krzysztof

[PATCH v0 2/5] arm64: Kconfig: Add Aspeed SoC family (ast2700) platform option

[Ryan Chen]

Add ARCH_ASPEED platform option to arm64 Kconfig, enabling support
for Aspeed ast2700 and similar 7th generation Aspeed BMCs.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 arch/arm64/Kconfig.platforms | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index a541bb029aa4..03e6c168c87e 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -40,6 +40,12 @@ config ARCH_APPLE
 	  This enables support for Apple's in-house ARM SoC family, such
 	  as the Apple M1.
 
+config ARCH_ASPEED
+	bool "Aspeed SoC family"
+	help
+	  Say yes if you intend to run on an Aspeed ast2700 or similar
+	  seventh generation Aspeed BMCs.
+
 menuconfig ARCH_BCM
 	bool "Broadcom SoC Support"
 
-- 
2.34.1

[PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Ryan Chen]

This add the initial device tree support for the ASPEED AST2700 SoC.

- Add top-level compatible string "aspeed,ast2700" and set up
address-cells/size-cells for 64-bit address space.
- Describe a quad-core ARM Cortex-A35 CPU cluster with L2 cache,
including cache properties and PSCI enable-method.
- Add PMU and ARMv8 timer nodes with correct PPI interrupt wiring.
- Model the dual-SoC architecture with two simple-bus nodes:
soc0 (@0x10000000) and soc1 (@0x14000000).
- Add syscon nodes for both SoCs (syscon0, syscon1) with clock/reset
cell definitions and address mapping.
- Add GICv3 interrupt controller node under soc0, with full register
mapping and interrupt properties.
- Hierarchical interrupt controller structure:
  - intc0 under soc0, with child intc0_11 node.
  - intc1 under soc1, with child intc1_0~intc1_5 nodes.
- Add serial4 node under soc0, others serial node under soc1.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 380 ++++++++++++++++++++++
 1 file changed, 380 insertions(+)
 create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi

diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
new file mode 100644
index 000000000000..d197187bcf9f
--- /dev/null
+++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+#include <dt-bindings/clock/aspeed,ast2700-scu.h>
+#include <dt-bindings/reset/aspeed,ast2700-scu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			enable-method = "psci";
+			reg = <0x0 0x1>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			enable-method = "psci";
+			reg = <0x0 0x2>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			enable-method = "psci";
+			reg = <0x0 0x3>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0x80000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+		};
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a35-pmu";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		arm,cpu-registers-not-fw-configured;
+		always-on;
+	};
+
+	soc0: soc@10000000 {
+		compatible = "simple-bus";
+		reg = <0x0 0x10000000 0x10000000>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		syscon0: syscon@12c02000 {
+			compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
+			reg = <0x0 0x12c02000 0x1000>;
+			ranges = <0x0 0x0 0 0x12c02000 0x1000>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		gic: interrupt-controller@12200000 {
+			compatible = "arm,gic-v3";
+			reg = <0 0x12200000 0x10000>, /* GICD */
+			      <0 0x12280000 0x80000>, /* GICR */
+			      <0 0x40440000 0x1000>;  /* GICC */
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			interrupt-parent = <&gic>;
+		};
+
+		serial4: serial@12c1a000 {
+			compatible = "ns16550a";
+			reg = <0x0 0x12c1a000 0x1000>;
+			clocks = <&syscon0 SCU0_CLK_GATE_UART4CLK>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+	};
+
+	soc1: soc@14000000 {
+		compatible = "simple-bus";
+		reg = <0x0 0x14000000 0x10000000>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		syscon1: syscon@14c02000 {
+			compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
+			reg = <0x0 0x14c02000 0x1000>;
+			ranges = <0x0 0x0 0x0 0x14c02000 0x1000>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		serial12: serial@14c33b00 {
+			compatible = "ns16550a";
+			reg = <0x0 0x14c33b00 0x100>;
+			clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
+			interrupts-extended =
+				<&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+	};
+};
+
+&soc0 {
+	intc0: interrupt-controller@12100000 {
+		compatible = "simple-mfd";
+		reg = <0 0x12100000 0x4000>;
+		ranges = <0x0 0x0 0x0 0x12100000 0x4000>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+
+		intc0_11: interrupt-controller@1b00 {
+			compatible = "aspeed,ast2700-intc-ic";
+			reg = <0x0 0x1b00 0x10>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			interrupts = <GIC_SPI 192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+				     <GIC_SPI 193 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+				     <GIC_SPI 194 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+				     <GIC_SPI 195 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+				     <GIC_SPI 196 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+				     <GIC_SPI 197 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+};
+
+&soc1 {
+	intc1: interrupt-controller@14c18000 {
+		compatible = "simple-mfd";
+		reg = <0 0x14c18000 0x400>;
+		ranges = <0x0 0x0 0x0 0x14c18000 0x400>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+
+		intc1_0: interrupt-controller@100 {
+			compatible = "aspeed,ast2700-intc-ic";
+			reg = <0x0 0x100 0x10>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			interrupts-extended =
+				<&intc0_11 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		intc1_1: interrupt-controller@110 {
+			compatible = "aspeed,ast2700-intc-ic";
+			reg = <0x0 0x110 0x10>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			interrupts-extended =
+				<&intc0_11 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		intc1_2: interrupt-controller@120 {
+			compatible = "aspeed,ast2700-intc-ic";
+			reg = <0x0 0x120 0x10>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			interrupts-extended =
+				<&intc0_11 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		intc1_3: interrupt-controller@130 {
+			compatible = "aspeed,ast2700-intc-ic";
+			reg = <0x0 0x130 0x10>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			interrupts-extended =
+				<&intc0_11 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		intc1_4: interrupt-controller@140 {
+			compatible = "aspeed,ast2700-intc-ic";
+			reg = <0x0 0x140 0x10>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			interrupts-extended =
+				<&intc0_11 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		intc1_5: interrupt-controller@150 {
+			compatible = "aspeed,ast2700-intc-ic";
+			reg = <0x0 0x150 0x10>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			interrupts-extended =
+				<&intc0_11 5 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+
+	serial0: serial@14c33000 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33000 0x100>;
+		clocks = <&syscon1 SCU1_CLK_GATE_UART0CLK>;
+		interrupts-extended = <&intc1_4 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	serial1: serial@14c33100 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33100 0x100>;
+		clocks = <&syscon1 SCU1_CLK_GATE_UART1CLK>;
+		interrupts-extended = <&intc1_4 8 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	serial2: serial@14c33200 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33200 0x100>;
+		clocks = <&syscon1 SCU1_CLK_GATE_UART2CLK>;
+		interrupts-extended = <&intc1_4 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	serial3: serial@14c33300 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33300 0x100>;
+		clocks = <&syscon1 SCU1_CLK_GATE_UART3CLK>;
+		interrupts-extended = <&intc1_4 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	serial5: serial@14c33400 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33400 0x100>;
+		clocks = <&syscon1 SCU1_CLK_GATE_UART5CLK>;
+		interrupts-extended = <&intc1_4 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	serial6: serial@14c33500 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33500 0x100>;
+		clocks = <&syscon1 SCU1_CLK_GATE_UART6CLK>;
+		interrupts-extended = <&intc1_4 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	serial7: serial@14c33600 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33600 0x100>;
+		clocks = <&syscon1 SCU1_CLK_GATE_UART7CLK>;
+		interrupts-extended = <&intc1_4 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	serial8: serial@14c33700 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33700 0x100>;
+		clocks = <&syscon1 SCU1_CLK_GATE_UART8CLK>;
+		interrupts-extended = <&intc1_4 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	serial9: serial@14c33800 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33800 0x100>;
+		clocks = <&syscon1 SCU1_CLK_GATE_UART9CLK>;
+		interrupts-extended = <&intc1_4 15 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	serial10: serial@14c33900 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33900 0x100>;
+		clocks = <&syscon1 SCU1_CLK_GATE_UART10CLK>;
+		interrupts-extended = <&intc1_4 16 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	serial11: serial@14c33a00 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33a00 0x100>;
+		clocks = <&syscon1 SCU1_CLK_GATE_UART11CLK>;
+		interrupts-extended = <&intc1_4 17 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	serial12: serial@14c33b00 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33b00 0x100>;
+		clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
+		interrupts-extended = <&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		pinctrl-names = "default";
+	};
+
+	serial13: serial@14c33c00 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33c00 0x100>;
+		clocks = <&syscon1 SCU1_CLK_UART13>;
+		interrupts-extended = <&intc1_0 23 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	serial14: serial@14c33d00 {
+		compatible = "ns16550a";
+		reg = <0x0 0x14c33d00 0x100>;
+		clocks = <&syscon1 SCU1_CLK_UART14>;
+		interrupts-extended = <&intc1_1 23 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+};
+
-- 
2.34.1

Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Krzysztof Kozlowski]

On 12/06/2025 12:09, Ryan Chen wrote:
> This add the initial device tree support for the ASPEED AST2700 SoC.
> 
> - Add top-level compatible string "aspeed,ast2700" and set up
> address-cells/size-cells for 64-bit address space.
> - Describe a quad-core ARM Cortex-A35 CPU cluster with L2 cache,
> including cache properties and PSCI enable-method.
> - Add PMU and ARMv8 timer nodes with correct PPI interrupt wiring.
> - Model the dual-SoC architecture with two simple-bus nodes:
> soc0 (@0x10000000) and soc1 (@0x14000000).
> - Add syscon nodes for both SoCs (syscon0, syscon1) with clock/reset
> cell definitions and address mapping.
> - Add GICv3 interrupt controller node under soc0, with full register
> mapping and interrupt properties.
> - Hierarchical interrupt controller structure:
>   - intc0 under soc0, with child intc0_11 node.
>   - intc1 under soc1, with child intc1_0~intc1_5 nodes.
> - Add serial4 node under soc0, others serial node under soc1.
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
>  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 380 ++++++++++++++++++++++
>  1 file changed, 380 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> 
> diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> new file mode 100644
> index 000000000000..d197187bcf9f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> @@ -0,0 +1,380 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +#include <dt-bindings/clock/aspeed,ast2700-scu.h>
> +#include <dt-bindings/reset/aspeed,ast2700-scu.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <1>;
> +	interrupt-parent = <&gic>;
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			enable-method = "psci";
> +			reg = <0x0 0x1>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		cpu2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			enable-method = "psci";
> +			reg = <0x0 0x2>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		cpu3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			enable-method = "psci";
> +			reg = <0x0 0x3>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		l2: l2-cache0 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-unified;
> +			cache-size = <0x80000>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +		};
> +	};
> +
> +	arm-pmu {
> +		compatible = "arm,cortex-a35-pmu";
> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +		arm,cpu-registers-not-fw-configured;
> +		always-on;
> +	};
> +
> +	soc0: soc@10000000 {
> +		compatible = "simple-bus";
> +		reg = <0x0 0x10000000 0x10000000>;
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		syscon0: syscon@12c02000 {
> +			compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
> +			reg = <0x0 0x12c02000 0x1000>;
> +			ranges = <0x0 0x0 0 0x12c02000 0x1000>;
> +			#address-cells = <2>;
> +			#size-cells = <1>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		gic: interrupt-controller@12200000 {
> +			compatible = "arm,gic-v3";
> +			reg = <0 0x12200000 0x10000>, /* GICD */
> +			      <0 0x12280000 0x80000>, /* GICR */
> +			      <0 0x40440000 0x1000>;  /* GICC */
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +			interrupt-parent = <&gic>;
> +		};
> +
> +		serial4: serial@12c1a000 {
> +			compatible = "ns16550a";
> +			reg = <0x0 0x12c1a000 0x1000>;
> +			clocks = <&syscon0 SCU0_CLK_GATE_UART4CLK>;
> +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			status = "disabled";
> +		};
> +	};
> +
> +	soc1: soc@14000000 {
> +		compatible = "simple-bus";
> +		reg = <0x0 0x14000000 0x10000000>;
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		syscon1: syscon@14c02000 {
> +			compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
> +			reg = <0x0 0x14c02000 0x1000>;
> +			ranges = <0x0 0x0 0x0 0x14c02000 0x1000>;
> +			#address-cells = <2>;
> +			#size-cells = <1>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		serial12: serial@14c33b00 {
> +			compatible = "ns16550a";
> +			reg = <0x0 0x14c33b00 0x100>;
> +			clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
> +			interrupts-extended =
> +				<&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +			reg-shift = <2>;
> +			status = "disabled";
> +		};
> +	};
> +};
> +
> +&soc0 {

This is the base DTSI, there is no existing node to override. Just
define complete SoC node in one place like every other vendor.


> +	intc0: interrupt-controller@12100000 {
> +		compatible = "simple-mfd";

NAK, never tested.

Not allowed, see bindings. And test it next time.


Best regards,
Krzysztof

RE: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Ryan Chen]

> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device
> tree
> 
> On 12/06/2025 12:09, Ryan Chen wrote:
> > This add the initial device tree support for the ASPEED AST2700 SoC.
> >
> > - Add top-level compatible string "aspeed,ast2700" and set up
> > address-cells/size-cells for 64-bit address space.
> > - Describe a quad-core ARM Cortex-A35 CPU cluster with L2 cache,
> > including cache properties and PSCI enable-method.
> > - Add PMU and ARMv8 timer nodes with correct PPI interrupt wiring.
> > - Model the dual-SoC architecture with two simple-bus nodes:
> > soc0 (@0x10000000) and soc1 (@0x14000000).
> > - Add syscon nodes for both SoCs (syscon0, syscon1) with clock/reset
> > cell definitions and address mapping.
> > - Add GICv3 interrupt controller node under soc0, with full register
> > mapping and interrupt properties.
> > - Hierarchical interrupt controller structure:
> >   - intc0 under soc0, with child intc0_11 node.
> >   - intc1 under soc1, with child intc1_0~intc1_5 nodes.
> > - Add serial4 node under soc0, others serial node under soc1.
> >
> > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> > ---
> >  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 380
> > ++++++++++++++++++++++
> >  1 file changed, 380 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> > b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> > new file mode 100644
> > index 000000000000..d197187bcf9f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> > @@ -0,0 +1,380 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later #include
> > +<dt-bindings/clock/aspeed,ast2700-scu.h>
> > +#include <dt-bindings/reset/aspeed,ast2700-scu.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	#address-cells = <2>;
> > +	#size-cells = <1>;
> > +	interrupt-parent = <&gic>;
> > +
> > +	cpus {
> > +		#address-cells = <2>;
> > +		#size-cells = <0>;
> > +
> > +		cpu0: cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> > +			reg = <0x0 0x0>;
> > +			enable-method = "psci";
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> > +		};
> > +
> > +		cpu1: cpu@1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> > +			enable-method = "psci";
> > +			reg = <0x0 0x1>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> > +		};
> > +
> > +		cpu2: cpu@2 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> > +			enable-method = "psci";
> > +			reg = <0x0 0x2>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> > +		};
> > +
> > +		cpu3: cpu@3 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> > +			enable-method = "psci";
> > +			reg = <0x0 0x3>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> > +		};
> > +
> > +		l2: l2-cache0 {
> > +			compatible = "cache";
> > +			cache-level = <2>;
> > +			cache-unified;
> > +			cache-size = <0x80000>;
> > +			cache-line-size = <64>;
> > +			cache-sets = <1024>;
> > +		};
> > +	};
> > +
> > +	arm-pmu {
> > +		compatible = "arm,cortex-a35-pmu";
> > +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>;
> > +	};
> > +
> > +	psci {
> > +		compatible = "arm,psci-1.0";
> > +		method = "smc";
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>;
> > +		arm,cpu-registers-not-fw-configured;
> > +		always-on;
> > +	};
> > +
> > +	soc0: soc@10000000 {
> > +		compatible = "simple-bus";
> > +		reg = <0x0 0x10000000 0x10000000>;
> > +		#address-cells = <2>;
> > +		#size-cells = <1>;
> > +		ranges;
> > +
> > +		syscon0: syscon@12c02000 {
> > +			compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
> > +			reg = <0x0 0x12c02000 0x1000>;
> > +			ranges = <0x0 0x0 0 0x12c02000 0x1000>;
> > +			#address-cells = <2>;
> > +			#size-cells = <1>;
> > +			#clock-cells = <1>;
> > +			#reset-cells = <1>;
> > +		};
> > +
> > +		gic: interrupt-controller@12200000 {
> > +			compatible = "arm,gic-v3";
> > +			reg = <0 0x12200000 0x10000>, /* GICD */
> > +			      <0 0x12280000 0x80000>, /* GICR */
> > +			      <0 0x40440000 0x1000>;  /* GICC */
> > +			#interrupt-cells = <3>;
> > +			interrupt-controller;
> > +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>;
> > +			interrupt-parent = <&gic>;
> > +		};
> > +
> > +		serial4: serial@12c1a000 {
> > +			compatible = "ns16550a";
> > +			reg = <0x0 0x12c1a000 0x1000>;
> > +			clocks = <&syscon0 SCU0_CLK_GATE_UART4CLK>;
> > +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > +			reg-shift = <2>;
> > +			status = "disabled";
> > +		};
> > +	};
> > +
> > +	soc1: soc@14000000 {
> > +		compatible = "simple-bus";
> > +		reg = <0x0 0x14000000 0x10000000>;
> > +		#address-cells = <2>;
> > +		#size-cells = <1>;
> > +		ranges;
> > +
> > +		syscon1: syscon@14c02000 {
> > +			compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
> > +			reg = <0x0 0x14c02000 0x1000>;
> > +			ranges = <0x0 0x0 0x0 0x14c02000 0x1000>;
> > +			#address-cells = <2>;
> > +			#size-cells = <1>;
> > +			#clock-cells = <1>;
> > +			#reset-cells = <1>;
> > +		};
> > +
> > +		serial12: serial@14c33b00 {
> > +			compatible = "ns16550a";
> > +			reg = <0x0 0x14c33b00 0x100>;
> > +			clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
> > +			interrupts-extended =
> > +				<&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>;
> > +			reg-shift = <2>;
> > +			status = "disabled";
> > +		};
> > +	};
> > +};
> > +
> > +&soc0 {
> 
> This is the base DTSI, there is no existing node to override. Just define
> complete SoC node in one place like every other vendor.

My original is use this way, but when I do checkpatch, get
CHECK: line length of 106 exceeds 100 columns.
interrupts = <GIC_SPI 192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
That the reason modify by this way.

> 
> 
> > +	intc0: interrupt-controller@12100000 {
> > +		compatible = "simple-mfd";
> 
> NAK, never tested.
> 
> Not allowed, see bindings. And test it next time.

Got it, will update by following. 
Intc0: bus@12100000 {
        compatible = "simple-bus";
        #address-cells = <2>;
        #size-cells = <1>;
        reg = <0 0x12100000 0x4000>;
		ranges = <0x0 0x0 0x0 0x12100000 0x4000>;
		#address-cells = <2>;
        #size-cells = <1>;

        intc0_11: interrupt-controller@1b00 {
               compatible = "aspeed,ast2700-intc-ic";
               reg = <0x0 0x1b00 0x10>;
> 
> 
> Best regards,
> Krzysztof

Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Krzysztof Kozlowski]

On 13/06/2025 04:29, Ryan Chen wrote:
>> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device
>> tree
>>
>> On 12/06/2025 12:09, Ryan Chen wrote:
>>> This add the initial device tree support for the ASPEED AST2700 SoC.
>>>
>>> - Add top-level compatible string "aspeed,ast2700" and set up
>>> address-cells/size-cells for 64-bit address space.
>>> - Describe a quad-core ARM Cortex-A35 CPU cluster with L2 cache,
>>> including cache properties and PSCI enable-method.
>>> - Add PMU and ARMv8 timer nodes with correct PPI interrupt wiring.
>>> - Model the dual-SoC architecture with two simple-bus nodes:
>>> soc0 (@0x10000000) and soc1 (@0x14000000).
>>> - Add syscon nodes for both SoCs (syscon0, syscon1) with clock/reset
>>> cell definitions and address mapping.
>>> - Add GICv3 interrupt controller node under soc0, with full register
>>> mapping and interrupt properties.
>>> - Hierarchical interrupt controller structure:
>>>   - intc0 under soc0, with child intc0_11 node.
>>>   - intc1 under soc1, with child intc1_0~intc1_5 nodes.
>>> - Add serial4 node under soc0, others serial node under soc1.
>>>
>>> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
>>> ---
>>>  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 380
>>> ++++++++++++++++++++++
>>>  1 file changed, 380 insertions(+)
>>>  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>> b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>> new file mode 100644
>>> index 000000000000..d197187bcf9f
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>> @@ -0,0 +1,380 @@
>>> +// SPDX-License-Identifier: GPL-2.0-or-later #include
>>> +<dt-bindings/clock/aspeed,ast2700-scu.h>
>>> +#include <dt-bindings/reset/aspeed,ast2700-scu.h>
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> +/ {
>>> +	#address-cells = <2>;
>>> +	#size-cells = <1>;
>>> +	interrupt-parent = <&gic>;
>>> +
>>> +	cpus {
>>> +		#address-cells = <2>;
>>> +		#size-cells = <0>;
>>> +
>>> +		cpu0: cpu@0 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a35";
>>> +			reg = <0x0 0x0>;
>>> +			enable-method = "psci";
>>> +			i-cache-size = <0x8000>;
>>> +			i-cache-line-size = <64>;
>>> +			i-cache-sets = <256>;
>>> +			d-cache-size = <0x8000>;
>>> +			d-cache-line-size = <64>;
>>> +			d-cache-sets = <128>;
>>> +			next-level-cache = <&l2>;
>>> +		};
>>> +
>>> +		cpu1: cpu@1 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a35";
>>> +			enable-method = "psci";
>>> +			reg = <0x0 0x1>;
>>> +			i-cache-size = <0x8000>;
>>> +			i-cache-line-size = <64>;
>>> +			i-cache-sets = <256>;
>>> +			d-cache-size = <0x8000>;
>>> +			d-cache-line-size = <64>;
>>> +			d-cache-sets = <128>;
>>> +			next-level-cache = <&l2>;
>>> +		};
>>> +
>>> +		cpu2: cpu@2 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a35";
>>> +			enable-method = "psci";
>>> +			reg = <0x0 0x2>;
>>> +			i-cache-size = <0x8000>;
>>> +			i-cache-line-size = <64>;
>>> +			i-cache-sets = <256>;
>>> +			d-cache-size = <0x8000>;
>>> +			d-cache-line-size = <64>;
>>> +			d-cache-sets = <128>;
>>> +			next-level-cache = <&l2>;
>>> +		};
>>> +
>>> +		cpu3: cpu@3 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a35";
>>> +			enable-method = "psci";
>>> +			reg = <0x0 0x3>;
>>> +			i-cache-size = <0x8000>;
>>> +			i-cache-line-size = <64>;
>>> +			i-cache-sets = <256>;
>>> +			d-cache-size = <0x8000>;
>>> +			d-cache-line-size = <64>;
>>> +			d-cache-sets = <128>;
>>> +			next-level-cache = <&l2>;
>>> +		};
>>> +
>>> +		l2: l2-cache0 {
>>> +			compatible = "cache";
>>> +			cache-level = <2>;
>>> +			cache-unified;
>>> +			cache-size = <0x80000>;
>>> +			cache-line-size = <64>;
>>> +			cache-sets = <1024>;
>>> +		};
>>> +	};
>>> +
>>> +	arm-pmu {
>>> +		compatible = "arm,cortex-a35-pmu";
>>> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
>> IRQ_TYPE_LEVEL_HIGH)>;
>>> +	};
>>> +
>>> +	psci {
>>> +		compatible = "arm,psci-1.0";
>>> +		method = "smc";
>>> +	};
>>> +
>>> +	timer {
>>> +		compatible = "arm,armv8-timer";
>>> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>> IRQ_TYPE_LEVEL_LOW)>,
>>> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
>> IRQ_TYPE_LEVEL_LOW)>,
>>> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
>> IRQ_TYPE_LEVEL_LOW)>,
>>> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
>> IRQ_TYPE_LEVEL_LOW)>;
>>> +		arm,cpu-registers-not-fw-configured;
>>> +		always-on;
>>> +	};
>>> +
>>> +	soc0: soc@10000000 {
>>> +		compatible = "simple-bus";
>>> +		reg = <0x0 0x10000000 0x10000000>;
>>> +		#address-cells = <2>;
>>> +		#size-cells = <1>;
>>> +		ranges;
>>> +
>>> +		syscon0: syscon@12c02000 {
>>> +			compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
>>> +			reg = <0x0 0x12c02000 0x1000>;
>>> +			ranges = <0x0 0x0 0 0x12c02000 0x1000>;
>>> +			#address-cells = <2>;
>>> +			#size-cells = <1>;
>>> +			#clock-cells = <1>;
>>> +			#reset-cells = <1>;
>>> +		};
>>> +
>>> +		gic: interrupt-controller@12200000 {
>>> +			compatible = "arm,gic-v3";
>>> +			reg = <0 0x12200000 0x10000>, /* GICD */
>>> +			      <0 0x12280000 0x80000>, /* GICR */
>>> +			      <0 0x40440000 0x1000>;  /* GICC */
>>> +			#interrupt-cells = <3>;
>>> +			interrupt-controller;
>>> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
>> IRQ_TYPE_LEVEL_HIGH)>;
>>> +			interrupt-parent = <&gic>;
>>> +		};
>>> +
>>> +		serial4: serial@12c1a000 {
>>> +			compatible = "ns16550a";
>>> +			reg = <0x0 0x12c1a000 0x1000>;
>>> +			clocks = <&syscon0 SCU0_CLK_GATE_UART4CLK>;
>>> +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
>>> +			reg-shift = <2>;
>>> +			status = "disabled";
>>> +		};
>>> +	};
>>> +
>>> +	soc1: soc@14000000 {
>>> +		compatible = "simple-bus";
>>> +		reg = <0x0 0x14000000 0x10000000>;
>>> +		#address-cells = <2>;
>>> +		#size-cells = <1>;
>>> +		ranges;
>>> +
>>> +		syscon1: syscon@14c02000 {
>>> +			compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
>>> +			reg = <0x0 0x14c02000 0x1000>;
>>> +			ranges = <0x0 0x0 0x0 0x14c02000 0x1000>;
>>> +			#address-cells = <2>;
>>> +			#size-cells = <1>;
>>> +			#clock-cells = <1>;
>>> +			#reset-cells = <1>;
>>> +		};
>>> +
>>> +		serial12: serial@14c33b00 {
>>> +			compatible = "ns16550a";
>>> +			reg = <0x0 0x14c33b00 0x100>;
>>> +			clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
>>> +			interrupts-extended =
>>> +				<&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) |
>> IRQ_TYPE_LEVEL_HIGH)>;
>>> +			reg-shift = <2>;
>>> +			status = "disabled";
>>> +		};
>>> +	};
>>> +};
>>> +
>>> +&soc0 {
>>
>> This is the base DTSI, there is no existing node to override. Just define
>> complete SoC node in one place like every other vendor.
> 
> My original is use this way, but when I do checkpatch, get
> CHECK: line length of 106 exceeds 100 columns.
> interrupts = <GIC_SPI 192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> That the reason modify by this way.

Look how other recent, most developed platforms do it and learn from
them instead of coming with own, confusing style.

> 
>>
>>
>>> +	intc0: interrupt-controller@12100000 {
>>> +		compatible = "simple-mfd";
>>
>> NAK, never tested.
>>
>> Not allowed, see bindings. And test it next time.
> 
> Got it, will update by following. 
> Intc0: bus@12100000 {
>         compatible = "simple-bus";
>         #address-cells = <2>;
>         #size-cells = <1>;
>         reg = <0 0x12100000 0x4000>;
> 		ranges = <0x0 0x0 0x0 0x12100000 0x4000>;
> 		#address-cells = <2>;

Does not follow DTS coding style and anyway, what sort of bus is this?



Best regards,
Krzysztof

RE: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Ryan Chen]

> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device
> tree
> 
> On 13/06/2025 04:29, Ryan Chen wrote:
> >> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700
> >> SoC device tree
> >>
> >> On 12/06/2025 12:09, Ryan Chen wrote:
> >>> This add the initial device tree support for the ASPEED AST2700 SoC.
> >>>
> >>> - Add top-level compatible string "aspeed,ast2700" and set up
> >>> address-cells/size-cells for 64-bit address space.
> >>> - Describe a quad-core ARM Cortex-A35 CPU cluster with L2 cache,
> >>> including cache properties and PSCI enable-method.
> >>> - Add PMU and ARMv8 timer nodes with correct PPI interrupt wiring.
> >>> - Model the dual-SoC architecture with two simple-bus nodes:
> >>> soc0 (@0x10000000) and soc1 (@0x14000000).
> >>> - Add syscon nodes for both SoCs (syscon0, syscon1) with clock/reset
> >>> cell definitions and address mapping.
> >>> - Add GICv3 interrupt controller node under soc0, with full register
> >>> mapping and interrupt properties.
> >>> - Hierarchical interrupt controller structure:
> >>>   - intc0 under soc0, with child intc0_11 node.
> >>>   - intc1 under soc1, with child intc1_0~intc1_5 nodes.
> >>> - Add serial4 node under soc0, others serial node under soc1.
> >>>
> >>> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> >>> ---
> >>>  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 380
> >>> ++++++++++++++++++++++
> >>>  1 file changed, 380 insertions(+)
> >>>  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >>>
> >>> diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >>> b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >>> new file mode 100644
> >>> index 000000000000..d197187bcf9f
> >>> --- /dev/null
> >>> +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >>> @@ -0,0 +1,380 @@
> >>> +// SPDX-License-Identifier: GPL-2.0-or-later #include
> >>> +<dt-bindings/clock/aspeed,ast2700-scu.h>
> >>> +#include <dt-bindings/reset/aspeed,ast2700-scu.h>
> >>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> >>> +
> >>> +/ {
> >>> +	#address-cells = <2>;
> >>> +	#size-cells = <1>;
> >>> +	interrupt-parent = <&gic>;
> >>> +
> >>> +	cpus {
> >>> +		#address-cells = <2>;
> >>> +		#size-cells = <0>;
> >>> +
> >>> +		cpu0: cpu@0 {
> >>> +			device_type = "cpu";
> >>> +			compatible = "arm,cortex-a35";
> >>> +			reg = <0x0 0x0>;
> >>> +			enable-method = "psci";
> >>> +			i-cache-size = <0x8000>;
> >>> +			i-cache-line-size = <64>;
> >>> +			i-cache-sets = <256>;
> >>> +			d-cache-size = <0x8000>;
> >>> +			d-cache-line-size = <64>;
> >>> +			d-cache-sets = <128>;
> >>> +			next-level-cache = <&l2>;
> >>> +		};
> >>> +
> >>> +		cpu1: cpu@1 {
> >>> +			device_type = "cpu";
> >>> +			compatible = "arm,cortex-a35";
> >>> +			enable-method = "psci";
> >>> +			reg = <0x0 0x1>;
> >>> +			i-cache-size = <0x8000>;
> >>> +			i-cache-line-size = <64>;
> >>> +			i-cache-sets = <256>;
> >>> +			d-cache-size = <0x8000>;
> >>> +			d-cache-line-size = <64>;
> >>> +			d-cache-sets = <128>;
> >>> +			next-level-cache = <&l2>;
> >>> +		};
> >>> +
> >>> +		cpu2: cpu@2 {
> >>> +			device_type = "cpu";
> >>> +			compatible = "arm,cortex-a35";
> >>> +			enable-method = "psci";
> >>> +			reg = <0x0 0x2>;
> >>> +			i-cache-size = <0x8000>;
> >>> +			i-cache-line-size = <64>;
> >>> +			i-cache-sets = <256>;
> >>> +			d-cache-size = <0x8000>;
> >>> +			d-cache-line-size = <64>;
> >>> +			d-cache-sets = <128>;
> >>> +			next-level-cache = <&l2>;
> >>> +		};
> >>> +
> >>> +		cpu3: cpu@3 {
> >>> +			device_type = "cpu";
> >>> +			compatible = "arm,cortex-a35";
> >>> +			enable-method = "psci";
> >>> +			reg = <0x0 0x3>;
> >>> +			i-cache-size = <0x8000>;
> >>> +			i-cache-line-size = <64>;
> >>> +			i-cache-sets = <256>;
> >>> +			d-cache-size = <0x8000>;
> >>> +			d-cache-line-size = <64>;
> >>> +			d-cache-sets = <128>;
> >>> +			next-level-cache = <&l2>;
> >>> +		};
> >>> +
> >>> +		l2: l2-cache0 {
> >>> +			compatible = "cache";
> >>> +			cache-level = <2>;
> >>> +			cache-unified;
> >>> +			cache-size = <0x80000>;
> >>> +			cache-line-size = <64>;
> >>> +			cache-sets = <1024>;
> >>> +		};
> >>> +	};
> >>> +
> >>> +	arm-pmu {
> >>> +		compatible = "arm,cortex-a35-pmu";
> >>> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
> >> IRQ_TYPE_LEVEL_HIGH)>;
> >>> +	};
> >>> +
> >>> +	psci {
> >>> +		compatible = "arm,psci-1.0";
> >>> +		method = "smc";
> >>> +	};
> >>> +
> >>> +	timer {
> >>> +		compatible = "arm,armv8-timer";
> >>> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> >> IRQ_TYPE_LEVEL_LOW)>,
> >>> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
> >> IRQ_TYPE_LEVEL_LOW)>,
> >>> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
> >> IRQ_TYPE_LEVEL_LOW)>,
> >>> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
> >> IRQ_TYPE_LEVEL_LOW)>;
> >>> +		arm,cpu-registers-not-fw-configured;
> >>> +		always-on;
> >>> +	};
> >>> +
> >>> +	soc0: soc@10000000 {
> >>> +		compatible = "simple-bus";
> >>> +		reg = <0x0 0x10000000 0x10000000>;
> >>> +		#address-cells = <2>;
> >>> +		#size-cells = <1>;
> >>> +		ranges;
> >>> +
> >>> +		syscon0: syscon@12c02000 {
> >>> +			compatible = "aspeed,ast2700-scu0", "syscon",
> "simple-mfd";
> >>> +			reg = <0x0 0x12c02000 0x1000>;
> >>> +			ranges = <0x0 0x0 0 0x12c02000 0x1000>;
> >>> +			#address-cells = <2>;
> >>> +			#size-cells = <1>;
> >>> +			#clock-cells = <1>;
> >>> +			#reset-cells = <1>;
> >>> +		};
> >>> +
> >>> +		gic: interrupt-controller@12200000 {
> >>> +			compatible = "arm,gic-v3";
> >>> +			reg = <0 0x12200000 0x10000>, /* GICD */
> >>> +			      <0 0x12280000 0x80000>, /* GICR */
> >>> +			      <0 0x40440000 0x1000>;  /* GICC */
> >>> +			#interrupt-cells = <3>;
> >>> +			interrupt-controller;
> >>> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> >> IRQ_TYPE_LEVEL_HIGH)>;
> >>> +			interrupt-parent = <&gic>;
> >>> +		};
> >>> +
> >>> +		serial4: serial@12c1a000 {
> >>> +			compatible = "ns16550a";
> >>> +			reg = <0x0 0x12c1a000 0x1000>;
> >>> +			clocks = <&syscon0 SCU0_CLK_GATE_UART4CLK>;
> >>> +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> >>> +			reg-shift = <2>;
> >>> +			status = "disabled";
> >>> +		};
> >>> +	};
> >>> +
> >>> +	soc1: soc@14000000 {
> >>> +		compatible = "simple-bus";
> >>> +		reg = <0x0 0x14000000 0x10000000>;
> >>> +		#address-cells = <2>;
> >>> +		#size-cells = <1>;
> >>> +		ranges;
> >>> +
> >>> +		syscon1: syscon@14c02000 {
> >>> +			compatible = "aspeed,ast2700-scu1", "syscon",
> "simple-mfd";
> >>> +			reg = <0x0 0x14c02000 0x1000>;
> >>> +			ranges = <0x0 0x0 0x0 0x14c02000 0x1000>;
> >>> +			#address-cells = <2>;
> >>> +			#size-cells = <1>;
> >>> +			#clock-cells = <1>;
> >>> +			#reset-cells = <1>;
> >>> +		};
> >>> +
> >>> +		serial12: serial@14c33b00 {
> >>> +			compatible = "ns16550a";
> >>> +			reg = <0x0 0x14c33b00 0x100>;
> >>> +			clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
> >>> +			interrupts-extended =
> >>> +				<&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) |
> >> IRQ_TYPE_LEVEL_HIGH)>;
> >>> +			reg-shift = <2>;
> >>> +			status = "disabled";
> >>> +		};
> >>> +	};
> >>> +};
> >>> +
> >>> +&soc0 {
> >>
> >> This is the base DTSI, there is no existing node to override. Just
> >> define complete SoC node in one place like every other vendor.
> >
> > My original is use this way, but when I do checkpatch, get
> > CHECK: line length of 106 exceeds 100 columns.
> > interrupts = <GIC_SPI 192 (GIC_CPU_MASK_SIMPLE(4) |
> > IRQ_TYPE_LEVEL_HIGH)>, That the reason modify by this way.
> 
> Look how other recent, most developed platforms do it and learn from them
> instead of coming with own, confusing style.

Thanks, I will refer this to modify.
https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/broadcom/bcm2712.dtsi#L580-L589
> 
> >
> >>
> >>
> >>> +	intc0: interrupt-controller@12100000 {
> >>> +		compatible = "simple-mfd";
> >>
> >> NAK, never tested.
> >>
> >> Not allowed, see bindings. And test it next time.
> >
> > Got it, will update by following.
> > Intc0: bus@12100000 {
> >         compatible = "simple-bus";
> >         #address-cells = <2>;
> >         #size-cells = <1>;
> >         reg = <0 0x12100000 0x4000>;
> > 		ranges = <0x0 0x0 0x0 0x12100000 0x4000>;
> > 		#address-cells = <2>;
> 
> Does not follow DTS coding style and anyway, what sort of bus is this?

Sorry, for miss-lead. intc0 is like the global base for inte0_11 interrupt-controller. 
So, I use simple-mfd. 
       intc0: interrupt-controller@12100000 {
                compatible = "simple-mfd";
					.....
                intc0_11: interrupt-controller@1b00 {
					......
                };
        };

But I don't know your previous "NAK, never tested" mean.
I did make CHECK_DTBS=y arch/arm64/boot/dts/aspeed/ don't see the fail with
intc0: interrupt-controller@12100000 {
	compatible = "simple-mfd";

So, could you point me more test instruction for this? 

> 
> 
> 
> Best regards,
> Krzysztof

Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Krzysztof Kozlowski]

On 16/06/2025 04:24, Ryan Chen wrote:
>> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device
>> tree
>>
>> On 13/06/2025 04:29, Ryan Chen wrote:
>>>> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700
>>>> SoC device tree
>>>>
>>>> On 12/06/2025 12:09, Ryan Chen wrote:
>>>>> This add the initial device tree support for the ASPEED AST2700 SoC.
>>>>>
>>>>> - Add top-level compatible string "aspeed,ast2700" and set up
>>>>> address-cells/size-cells for 64-bit address space.
>>>>> - Describe a quad-core ARM Cortex-A35 CPU cluster with L2 cache,
>>>>> including cache properties and PSCI enable-method.
>>>>> - Add PMU and ARMv8 timer nodes with correct PPI interrupt wiring.
>>>>> - Model the dual-SoC architecture with two simple-bus nodes:
>>>>> soc0 (@0x10000000) and soc1 (@0x14000000).
>>>>> - Add syscon nodes for both SoCs (syscon0, syscon1) with clock/reset
>>>>> cell definitions and address mapping.
>>>>> - Add GICv3 interrupt controller node under soc0, with full register
>>>>> mapping and interrupt properties.
>>>>> - Hierarchical interrupt controller structure:
>>>>>   - intc0 under soc0, with child intc0_11 node.
>>>>>   - intc1 under soc1, with child intc1_0~intc1_5 nodes.
>>>>> - Add serial4 node under soc0, others serial node under soc1.
>>>>>
>>>>> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
>>>>> ---
>>>>>  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 380
>>>>> ++++++++++++++++++++++
>>>>>  1 file changed, 380 insertions(+)
>>>>>  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>>>> b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>>>> new file mode 100644
>>>>> index 000000000000..d197187bcf9f
>>>>> --- /dev/null
>>>>> +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>>>>> @@ -0,0 +1,380 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0-or-later #include
>>>>> +<dt-bindings/clock/aspeed,ast2700-scu.h>
>>>>> +#include <dt-bindings/reset/aspeed,ast2700-scu.h>
>>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>> +
>>>>> +/ {
>>>>> +	#address-cells = <2>;
>>>>> +	#size-cells = <1>;
>>>>> +	interrupt-parent = <&gic>;
>>>>> +
>>>>> +	cpus {
>>>>> +		#address-cells = <2>;
>>>>> +		#size-cells = <0>;
>>>>> +
>>>>> +		cpu0: cpu@0 {
>>>>> +			device_type = "cpu";
>>>>> +			compatible = "arm,cortex-a35";
>>>>> +			reg = <0x0 0x0>;
>>>>> +			enable-method = "psci";
>>>>> +			i-cache-size = <0x8000>;
>>>>> +			i-cache-line-size = <64>;
>>>>> +			i-cache-sets = <256>;
>>>>> +			d-cache-size = <0x8000>;
>>>>> +			d-cache-line-size = <64>;
>>>>> +			d-cache-sets = <128>;
>>>>> +			next-level-cache = <&l2>;
>>>>> +		};
>>>>> +
>>>>> +		cpu1: cpu@1 {
>>>>> +			device_type = "cpu";
>>>>> +			compatible = "arm,cortex-a35";
>>>>> +			enable-method = "psci";
>>>>> +			reg = <0x0 0x1>;
>>>>> +			i-cache-size = <0x8000>;
>>>>> +			i-cache-line-size = <64>;
>>>>> +			i-cache-sets = <256>;
>>>>> +			d-cache-size = <0x8000>;
>>>>> +			d-cache-line-size = <64>;
>>>>> +			d-cache-sets = <128>;
>>>>> +			next-level-cache = <&l2>;
>>>>> +		};
>>>>> +
>>>>> +		cpu2: cpu@2 {
>>>>> +			device_type = "cpu";
>>>>> +			compatible = "arm,cortex-a35";
>>>>> +			enable-method = "psci";
>>>>> +			reg = <0x0 0x2>;
>>>>> +			i-cache-size = <0x8000>;
>>>>> +			i-cache-line-size = <64>;
>>>>> +			i-cache-sets = <256>;
>>>>> +			d-cache-size = <0x8000>;
>>>>> +			d-cache-line-size = <64>;
>>>>> +			d-cache-sets = <128>;
>>>>> +			next-level-cache = <&l2>;
>>>>> +		};
>>>>> +
>>>>> +		cpu3: cpu@3 {
>>>>> +			device_type = "cpu";
>>>>> +			compatible = "arm,cortex-a35";
>>>>> +			enable-method = "psci";
>>>>> +			reg = <0x0 0x3>;
>>>>> +			i-cache-size = <0x8000>;
>>>>> +			i-cache-line-size = <64>;
>>>>> +			i-cache-sets = <256>;
>>>>> +			d-cache-size = <0x8000>;
>>>>> +			d-cache-line-size = <64>;
>>>>> +			d-cache-sets = <128>;
>>>>> +			next-level-cache = <&l2>;
>>>>> +		};
>>>>> +
>>>>> +		l2: l2-cache0 {
>>>>> +			compatible = "cache";
>>>>> +			cache-level = <2>;
>>>>> +			cache-unified;
>>>>> +			cache-size = <0x80000>;
>>>>> +			cache-line-size = <64>;
>>>>> +			cache-sets = <1024>;
>>>>> +		};
>>>>> +	};
>>>>> +
>>>>> +	arm-pmu {
>>>>> +		compatible = "arm,cortex-a35-pmu";
>>>>> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
>>>> IRQ_TYPE_LEVEL_HIGH)>;
>>>>> +	};
>>>>> +
>>>>> +	psci {
>>>>> +		compatible = "arm,psci-1.0";
>>>>> +		method = "smc";
>>>>> +	};
>>>>> +
>>>>> +	timer {
>>>>> +		compatible = "arm,armv8-timer";
>>>>> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>>>> IRQ_TYPE_LEVEL_LOW)>,
>>>>> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
>>>> IRQ_TYPE_LEVEL_LOW)>,
>>>>> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
>>>> IRQ_TYPE_LEVEL_LOW)>,
>>>>> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
>>>> IRQ_TYPE_LEVEL_LOW)>;
>>>>> +		arm,cpu-registers-not-fw-configured;
>>>>> +		always-on;
>>>>> +	};
>>>>> +
>>>>> +	soc0: soc@10000000 {
>>>>> +		compatible = "simple-bus";
>>>>> +		reg = <0x0 0x10000000 0x10000000>;
>>>>> +		#address-cells = <2>;
>>>>> +		#size-cells = <1>;
>>>>> +		ranges;
>>>>> +
>>>>> +		syscon0: syscon@12c02000 {
>>>>> +			compatible = "aspeed,ast2700-scu0", "syscon",
>> "simple-mfd";
>>>>> +			reg = <0x0 0x12c02000 0x1000>;
>>>>> +			ranges = <0x0 0x0 0 0x12c02000 0x1000>;
>>>>> +			#address-cells = <2>;
>>>>> +			#size-cells = <1>;
>>>>> +			#clock-cells = <1>;
>>>>> +			#reset-cells = <1>;
>>>>> +		};
>>>>> +
>>>>> +		gic: interrupt-controller@12200000 {
>>>>> +			compatible = "arm,gic-v3";
>>>>> +			reg = <0 0x12200000 0x10000>, /* GICD */
>>>>> +			      <0 0x12280000 0x80000>, /* GICR */
>>>>> +			      <0 0x40440000 0x1000>;  /* GICC */
>>>>> +			#interrupt-cells = <3>;
>>>>> +			interrupt-controller;
>>>>> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
>>>> IRQ_TYPE_LEVEL_HIGH)>;
>>>>> +			interrupt-parent = <&gic>;
>>>>> +		};
>>>>> +
>>>>> +		serial4: serial@12c1a000 {
>>>>> +			compatible = "ns16550a";
>>>>> +			reg = <0x0 0x12c1a000 0x1000>;
>>>>> +			clocks = <&syscon0 SCU0_CLK_GATE_UART4CLK>;
>>>>> +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +			reg-shift = <2>;
>>>>> +			status = "disabled";
>>>>> +		};
>>>>> +	};
>>>>> +
>>>>> +	soc1: soc@14000000 {
>>>>> +		compatible = "simple-bus";
>>>>> +		reg = <0x0 0x14000000 0x10000000>;
>>>>> +		#address-cells = <2>;
>>>>> +		#size-cells = <1>;
>>>>> +		ranges;
>>>>> +
>>>>> +		syscon1: syscon@14c02000 {
>>>>> +			compatible = "aspeed,ast2700-scu1", "syscon",
>> "simple-mfd";
>>>>> +			reg = <0x0 0x14c02000 0x1000>;
>>>>> +			ranges = <0x0 0x0 0x0 0x14c02000 0x1000>;
>>>>> +			#address-cells = <2>;
>>>>> +			#size-cells = <1>;
>>>>> +			#clock-cells = <1>;
>>>>> +			#reset-cells = <1>;
>>>>> +		};
>>>>> +
>>>>> +		serial12: serial@14c33b00 {
>>>>> +			compatible = "ns16550a";
>>>>> +			reg = <0x0 0x14c33b00 0x100>;
>>>>> +			clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
>>>>> +			interrupts-extended =
>>>>> +				<&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) |
>>>> IRQ_TYPE_LEVEL_HIGH)>;
>>>>> +			reg-shift = <2>;
>>>>> +			status = "disabled";
>>>>> +		};
>>>>> +	};
>>>>> +};
>>>>> +
>>>>> +&soc0 {
>>>>
>>>> This is the base DTSI, there is no existing node to override. Just
>>>> define complete SoC node in one place like every other vendor.
>>>
>>> My original is use this way, but when I do checkpatch, get
>>> CHECK: line length of 106 exceeds 100 columns.
>>> interrupts = <GIC_SPI 192 (GIC_CPU_MASK_SIMPLE(4) |
>>> IRQ_TYPE_LEVEL_HIGH)>, That the reason modify by this way.
>>
>> Look how other recent, most developed platforms do it and learn from them
>> instead of coming with own, confusing style.
> 
> Thanks, I will refer this to modify.
> https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/broadcom/bcm2712.dtsi#L580-L589
>>
>>>
>>>>
>>>>
>>>>> +	intc0: interrupt-controller@12100000 {
>>>>> +		compatible = "simple-mfd";
>>>>
>>>> NAK, never tested.
>>>>
>>>> Not allowed, see bindings. And test it next time.
>>>
>>> Got it, will update by following.
>>> Intc0: bus@12100000 {
>>>         compatible = "simple-bus";
>>>         #address-cells = <2>;
>>>         #size-cells = <1>;
>>>         reg = <0 0x12100000 0x4000>;
>>> 		ranges = <0x0 0x0 0x0 0x12100000 0x4000>;
>>> 		#address-cells = <2>;
>>
>> Does not follow DTS coding style and anyway, what sort of bus is this?
> 
> Sorry, for miss-lead. intc0 is like the global base for inte0_11 interrupt-controller. 

So that's not a bus, thus do not use simple-bus for that. Define
bindings for your device.

> So, I use simple-mfd. 
>        intc0: interrupt-controller@12100000 {
>                 compatible = "simple-mfd";
> 					.....
>                 intc0_11: interrupt-controller@1b00 {
> 					......
>                 };
>         };
> 
> But I don't know your previous "NAK, never tested" mean.
> I did make CHECK_DTBS=y arch/arm64/boot/dts/aspeed/ don't see the fail with
> intc0: interrupt-controller@12100000 {
> 	compatible = "simple-mfd";
> 
> So, could you point me more test instruction for this? 
See syscon.yaml. And writing bindings or talks on conferences:
simple-mfd cannot be alone.


Best regards,
Krzysztof

RE: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Ryan Chen]

> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device
> tree
> 
> On 16/06/2025 04:24, Ryan Chen wrote:
> >> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700
> >> SoC device tree
> >>
> >> On 13/06/2025 04:29, Ryan Chen wrote:
> >>>> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700
> >>>> SoC device tree
> >>>>
> >>>> On 12/06/2025 12:09, Ryan Chen wrote:
> >>>>> This add the initial device tree support for the ASPEED AST2700 SoC.
> >>>>>
> >>>>> - Add top-level compatible string "aspeed,ast2700" and set up
> >>>>> address-cells/size-cells for 64-bit address space.
> >>>>> - Describe a quad-core ARM Cortex-A35 CPU cluster with L2 cache,
> >>>>> including cache properties and PSCI enable-method.
> >>>>> - Add PMU and ARMv8 timer nodes with correct PPI interrupt wiring.
> >>>>> - Model the dual-SoC architecture with two simple-bus nodes:
> >>>>> soc0 (@0x10000000) and soc1 (@0x14000000).
> >>>>> - Add syscon nodes for both SoCs (syscon0, syscon1) with
> >>>>> clock/reset cell definitions and address mapping.
> >>>>> - Add GICv3 interrupt controller node under soc0, with full
> >>>>> register mapping and interrupt properties.
> >>>>> - Hierarchical interrupt controller structure:
> >>>>>   - intc0 under soc0, with child intc0_11 node.
> >>>>>   - intc1 under soc1, with child intc1_0~intc1_5 nodes.
> >>>>> - Add serial4 node under soc0, others serial node under soc1.
> >>>>>
> >>>>> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> >>>>> ---
> >>>>>  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 380
> >>>>> ++++++++++++++++++++++
> >>>>>  1 file changed, 380 insertions(+)  create mode 100644
> >>>>> arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >>>>>
> >>>>> diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >>>>> b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >>>>> new file mode 100644
> >>>>> index 000000000000..d197187bcf9f
> >>>>> --- /dev/null
> >>>>> +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >>>>> @@ -0,0 +1,380 @@
> >>>>> +// SPDX-License-Identifier: GPL-2.0-or-later #include
> >>>>> +<dt-bindings/clock/aspeed,ast2700-scu.h>
> >>>>> +#include <dt-bindings/reset/aspeed,ast2700-scu.h>
> >>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>>> +
> >>>>> +/ {
> >>>>> +	#address-cells = <2>;
> >>>>> +	#size-cells = <1>;
> >>>>> +	interrupt-parent = <&gic>;
> >>>>> +
> >>>>> +	cpus {
> >>>>> +		#address-cells = <2>;
> >>>>> +		#size-cells = <0>;
> >>>>> +
> >>>>> +		cpu0: cpu@0 {
> >>>>> +			device_type = "cpu";
> >>>>> +			compatible = "arm,cortex-a35";
> >>>>> +			reg = <0x0 0x0>;
> >>>>> +			enable-method = "psci";
> >>>>> +			i-cache-size = <0x8000>;
> >>>>> +			i-cache-line-size = <64>;
> >>>>> +			i-cache-sets = <256>;
> >>>>> +			d-cache-size = <0x8000>;
> >>>>> +			d-cache-line-size = <64>;
> >>>>> +			d-cache-sets = <128>;
> >>>>> +			next-level-cache = <&l2>;
> >>>>> +		};
> >>>>> +
> >>>>> +		cpu1: cpu@1 {
> >>>>> +			device_type = "cpu";
> >>>>> +			compatible = "arm,cortex-a35";
> >>>>> +			enable-method = "psci";
> >>>>> +			reg = <0x0 0x1>;
> >>>>> +			i-cache-size = <0x8000>;
> >>>>> +			i-cache-line-size = <64>;
> >>>>> +			i-cache-sets = <256>;
> >>>>> +			d-cache-size = <0x8000>;
> >>>>> +			d-cache-line-size = <64>;
> >>>>> +			d-cache-sets = <128>;
> >>>>> +			next-level-cache = <&l2>;
> >>>>> +		};
> >>>>> +
> >>>>> +		cpu2: cpu@2 {
> >>>>> +			device_type = "cpu";
> >>>>> +			compatible = "arm,cortex-a35";
> >>>>> +			enable-method = "psci";
> >>>>> +			reg = <0x0 0x2>;
> >>>>> +			i-cache-size = <0x8000>;
> >>>>> +			i-cache-line-size = <64>;
> >>>>> +			i-cache-sets = <256>;
> >>>>> +			d-cache-size = <0x8000>;
> >>>>> +			d-cache-line-size = <64>;
> >>>>> +			d-cache-sets = <128>;
> >>>>> +			next-level-cache = <&l2>;
> >>>>> +		};
> >>>>> +
> >>>>> +		cpu3: cpu@3 {
> >>>>> +			device_type = "cpu";
> >>>>> +			compatible = "arm,cortex-a35";
> >>>>> +			enable-method = "psci";
> >>>>> +			reg = <0x0 0x3>;
> >>>>> +			i-cache-size = <0x8000>;
> >>>>> +			i-cache-line-size = <64>;
> >>>>> +			i-cache-sets = <256>;
> >>>>> +			d-cache-size = <0x8000>;
> >>>>> +			d-cache-line-size = <64>;
> >>>>> +			d-cache-sets = <128>;
> >>>>> +			next-level-cache = <&l2>;
> >>>>> +		};
> >>>>> +
> >>>>> +		l2: l2-cache0 {
> >>>>> +			compatible = "cache";
> >>>>> +			cache-level = <2>;
> >>>>> +			cache-unified;
> >>>>> +			cache-size = <0x80000>;
> >>>>> +			cache-line-size = <64>;
> >>>>> +			cache-sets = <1024>;
> >>>>> +		};
> >>>>> +	};
> >>>>> +
> >>>>> +	arm-pmu {
> >>>>> +		compatible = "arm,cortex-a35-pmu";
> >>>>> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
> >>>> IRQ_TYPE_LEVEL_HIGH)>;
> >>>>> +	};
> >>>>> +
> >>>>> +	psci {
> >>>>> +		compatible = "arm,psci-1.0";
> >>>>> +		method = "smc";
> >>>>> +	};
> >>>>> +
> >>>>> +	timer {
> >>>>> +		compatible = "arm,armv8-timer";
> >>>>> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> >>>> IRQ_TYPE_LEVEL_LOW)>,
> >>>>> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
> >>>> IRQ_TYPE_LEVEL_LOW)>,
> >>>>> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
> >>>> IRQ_TYPE_LEVEL_LOW)>,
> >>>>> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
> >>>> IRQ_TYPE_LEVEL_LOW)>;
> >>>>> +		arm,cpu-registers-not-fw-configured;
> >>>>> +		always-on;
> >>>>> +	};
> >>>>> +
> >>>>> +	soc0: soc@10000000 {
> >>>>> +		compatible = "simple-bus";
> >>>>> +		reg = <0x0 0x10000000 0x10000000>;
> >>>>> +		#address-cells = <2>;
> >>>>> +		#size-cells = <1>;
> >>>>> +		ranges;
> >>>>> +
> >>>>> +		syscon0: syscon@12c02000 {
> >>>>> +			compatible = "aspeed,ast2700-scu0", "syscon",
> >> "simple-mfd";
> >>>>> +			reg = <0x0 0x12c02000 0x1000>;
> >>>>> +			ranges = <0x0 0x0 0 0x12c02000 0x1000>;
> >>>>> +			#address-cells = <2>;
> >>>>> +			#size-cells = <1>;
> >>>>> +			#clock-cells = <1>;
> >>>>> +			#reset-cells = <1>;
> >>>>> +		};
> >>>>> +
> >>>>> +		gic: interrupt-controller@12200000 {
> >>>>> +			compatible = "arm,gic-v3";
> >>>>> +			reg = <0 0x12200000 0x10000>, /* GICD */
> >>>>> +			      <0 0x12280000 0x80000>, /* GICR */
> >>>>> +			      <0 0x40440000 0x1000>;  /* GICC */
> >>>>> +			#interrupt-cells = <3>;
> >>>>> +			interrupt-controller;
> >>>>> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> >>>> IRQ_TYPE_LEVEL_HIGH)>;
> >>>>> +			interrupt-parent = <&gic>;
> >>>>> +		};
> >>>>> +
> >>>>> +		serial4: serial@12c1a000 {
> >>>>> +			compatible = "ns16550a";
> >>>>> +			reg = <0x0 0x12c1a000 0x1000>;
> >>>>> +			clocks = <&syscon0 SCU0_CLK_GATE_UART4CLK>;
> >>>>> +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> >>>>> +			reg-shift = <2>;
> >>>>> +			status = "disabled";
> >>>>> +		};
> >>>>> +	};
> >>>>> +
> >>>>> +	soc1: soc@14000000 {
> >>>>> +		compatible = "simple-bus";
> >>>>> +		reg = <0x0 0x14000000 0x10000000>;
> >>>>> +		#address-cells = <2>;
> >>>>> +		#size-cells = <1>;
> >>>>> +		ranges;
> >>>>> +
> >>>>> +		syscon1: syscon@14c02000 {
> >>>>> +			compatible = "aspeed,ast2700-scu1", "syscon",
> >> "simple-mfd";
> >>>>> +			reg = <0x0 0x14c02000 0x1000>;
> >>>>> +			ranges = <0x0 0x0 0x0 0x14c02000 0x1000>;
> >>>>> +			#address-cells = <2>;
> >>>>> +			#size-cells = <1>;
> >>>>> +			#clock-cells = <1>;
> >>>>> +			#reset-cells = <1>;
> >>>>> +		};
> >>>>> +
> >>>>> +		serial12: serial@14c33b00 {
> >>>>> +			compatible = "ns16550a";
> >>>>> +			reg = <0x0 0x14c33b00 0x100>;
> >>>>> +			clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>;
> >>>>> +			interrupts-extended =
> >>>>> +				<&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) |
> >>>> IRQ_TYPE_LEVEL_HIGH)>;
> >>>>> +			reg-shift = <2>;
> >>>>> +			status = "disabled";
> >>>>> +		};
> >>>>> +	};
> >>>>> +};
> >>>>> +
> >>>>> +&soc0 {
> >>>>
> >>>> This is the base DTSI, there is no existing node to override. Just
> >>>> define complete SoC node in one place like every other vendor.
> >>>
> >>> My original is use this way, but when I do checkpatch, get
> >>> CHECK: line length of 106 exceeds 100 columns.
> >>> interrupts = <GIC_SPI 192 (GIC_CPU_MASK_SIMPLE(4) |
> >>> IRQ_TYPE_LEVEL_HIGH)>, That the reason modify by this way.
> >>
> >> Look how other recent, most developed platforms do it and learn from
> >> them instead of coming with own, confusing style.
> >
> > Thanks, I will refer this to modify.
> > https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/broa
> > dcom/bcm2712.dtsi#L580-L589
> >>
> >>>
> >>>>
> >>>>
> >>>>> +	intc0: interrupt-controller@12100000 {
> >>>>> +		compatible = "simple-mfd";
> >>>>
> >>>> NAK, never tested.
> >>>>
> >>>> Not allowed, see bindings. And test it next time.
> >>>
> >>> Got it, will update by following.
> >>> Intc0: bus@12100000 {
> >>>         compatible = "simple-bus";
> >>>         #address-cells = <2>;
> >>>         #size-cells = <1>;
> >>>         reg = <0 0x12100000 0x4000>;
> >>> 		ranges = <0x0 0x0 0x0 0x12100000 0x4000>;
> >>> 		#address-cells = <2>;
> >>
> >> Does not follow DTS coding style and anyway, what sort of bus is this?
> >
> > Sorry, for miss-lead. intc0 is like the global base for inte0_11
> interrupt-controller.
> 
> So that's not a bus, thus do not use simple-bus for that. Define bindings for
> your device.
> 
> > So, I use simple-mfd.
> >        intc0: interrupt-controller@12100000 {
> >                 compatible = "simple-mfd";
> > 					.....
> >                 intc0_11: interrupt-controller@1b00 {
> > 					......
> >                 };
> >         };
> >
> > But I don't know your previous "NAK, never tested" mean.
> > I did make CHECK_DTBS=y arch/arm64/boot/dts/aspeed/ don't see the fail
> > with
> > intc0: interrupt-controller@12100000 {
> > 	compatible = "simple-mfd";
> >
> > So, could you point me more test instruction for this?
> See syscon.yaml. And writing bindings or talks on conferences:
> simple-mfd cannot be alone.
> 

        intc0: interrupt-controller@12100000 {
Sorry, do you mean add by following? 
				 compatible = "aspeed,intc-controller", "simple-mfd";
 					.....
                 intc0_11: interrupt-controller@1b00 {
					compatible = "aspeed,ast2700-intc-ic";
 					......
                 };
         };
> 
> Best regards,
> Krzysztof

Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Krzysztof Kozlowski]

On 16/06/2025 08:32, Ryan Chen wrote:
>>>
>>> But I don't know your previous "NAK, never tested" mean.
>>> I did make CHECK_DTBS=y arch/arm64/boot/dts/aspeed/ don't see the fail
>>> with
>>> intc0: interrupt-controller@12100000 {
>>> 	compatible = "simple-mfd";
>>>
>>> So, could you point me more test instruction for this?
>> See syscon.yaml. And writing bindings or talks on conferences:
>> simple-mfd cannot be alone.
>>
> 
>         intc0: interrupt-controller@12100000 {
> Sorry, do you mean add by following? 
> 				 compatible = "aspeed,intc-controller", "simple-mfd";
>  					.....
>                  intc0_11: interrupt-controller@1b00 {
> 					compatible = "aspeed,ast2700-intc-ic";
>  					......
>                  };
>          };

Maybe, but you said this is base address, so how can it be some separate
device?

I mean really, don't add fake nodes just to satisfy some device
instantiation. Describe what this really is. That is the job of DTS. Not
some fake nodes.

Best regards,
Krzysztof

RE: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Ryan Chen]

> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device
> tree
> 
> On 16/06/2025 08:32, Ryan Chen wrote:
> >>>
> >>> But I don't know your previous "NAK, never tested" mean.
> >>> I did make CHECK_DTBS=y arch/arm64/boot/dts/aspeed/ don't see the
> >>> fail with
> >>> intc0: interrupt-controller@12100000 {
> >>> 	compatible = "simple-mfd";
> >>>
> >>> So, could you point me more test instruction for this?
> >> See syscon.yaml. And writing bindings or talks on conferences:
> >> simple-mfd cannot be alone.
> >>
> >
> >         intc0: interrupt-controller@12100000 { Sorry, do you mean add
> > by following?
> > 				 compatible = "aspeed,intc-controller", "simple-mfd";
> >  					.....
> >                  intc0_11: interrupt-controller@1b00 {
> > 					compatible = "aspeed,ast2700-intc-ic";
> >  					......
> >                  };
> >          };
> 
> Maybe, but you said this is base address, so how can it be some separate
> device?
> 
> I mean really, don't add fake nodes just to satisfy some device instantiation.
> Describe what this really is. That is the job of DTS. Not some fake nodes.


Understood. Let me explain more about the hardware layout.
The interrupt controller space is decoded starting from 0x12100000, 
which includes both a set of global configuration registers and
individual interrupt controller instances.

The region at 0x12100000 contains global interrupt control registers
(e.g., protect config, interrupt routing etc.).

The actual interrupt controller logic starts at 0x12101b00, where each sub-controller instance
(e.g., intc0_11, intc0_12, etc.) has its own set of registers.




> 
> Best regards,
> Krzysztof

Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Krzysztof Kozlowski]

On 16/06/2025 08:54, Ryan Chen wrote:
>> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device
>> tree
>>
>> On 16/06/2025 08:32, Ryan Chen wrote:
>>>>>
>>>>> But I don't know your previous "NAK, never tested" mean.
>>>>> I did make CHECK_DTBS=y arch/arm64/boot/dts/aspeed/ don't see the
>>>>> fail with
>>>>> intc0: interrupt-controller@12100000 {
>>>>> 	compatible = "simple-mfd";
>>>>>
>>>>> So, could you point me more test instruction for this?
>>>> See syscon.yaml. And writing bindings or talks on conferences:
>>>> simple-mfd cannot be alone.
>>>>
>>>
>>>         intc0: interrupt-controller@12100000 { Sorry, do you mean add
>>> by following?
>>> 				 compatible = "aspeed,intc-controller", "simple-mfd";
>>>  					.....
>>>                  intc0_11: interrupt-controller@1b00 {
>>> 					compatible = "aspeed,ast2700-intc-ic";
>>>  					......
>>>                  };
>>>          };
>>
>> Maybe, but you said this is base address, so how can it be some separate
>> device?
>>
>> I mean really, don't add fake nodes just to satisfy some device instantiation.
>> Describe what this really is. That is the job of DTS. Not some fake nodes.
> 
> 
> Understood. Let me explain more about the hardware layout.
> The interrupt controller space is decoded starting from 0x12100000, 
> which includes both a set of global configuration registers and
> individual interrupt controller instances.
> 
> The region at 0x12100000 contains global interrupt control registers
> (e.g., protect config, interrupt routing etc.).

This does not explain me why global controller registers are a BUS or
MFD as you claimed here.

> 
> The actual interrupt controller logic starts at 0x12101b00, where each sub-controller instance
> (e.g., intc0_11, intc0_12, etc.) has its own set of registers.

I don't know what is a "global controller register" and "own set of
registers". If you have device spanning over multiple memory blocks,
device takes multiple 'reg' entries for example. There are many other
configurations, depending on real hardware and relationships. Just look
at other DTS.

Best regards,
Krzysztof

RE: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Ryan Chen]

> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device
> tree
> 
> On 16/06/2025 08:54, Ryan Chen wrote:
> >> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700
> >> SoC device tree
> >>
> >> On 16/06/2025 08:32, Ryan Chen wrote:
> >>>>>
> >>>>> But I don't know your previous "NAK, never tested" mean.
> >>>>> I did make CHECK_DTBS=y arch/arm64/boot/dts/aspeed/ don't see the
> >>>>> fail with
> >>>>> intc0: interrupt-controller@12100000 {
> >>>>> 	compatible = "simple-mfd";
> >>>>>
> >>>>> So, could you point me more test instruction for this?
> >>>> See syscon.yaml. And writing bindings or talks on conferences:
> >>>> simple-mfd cannot be alone.
> >>>>
> >>>
> >>>         intc0: interrupt-controller@12100000 { Sorry, do you mean
> >>> add by following?
> >>> 				 compatible = "aspeed,intc-controller", "simple-mfd";
> >>>  					.....
> >>>                  intc0_11: interrupt-controller@1b00 {
> >>> 					compatible = "aspeed,ast2700-intc-ic";
> >>>  					......
> >>>                  };
> >>>          };
> >>
> >> Maybe, but you said this is base address, so how can it be some
> >> separate device?
> >>
> >> I mean really, don't add fake nodes just to satisfy some device instantiation.
> >> Describe what this really is. That is the job of DTS. Not some fake nodes.
> >
> >
> > Understood. Let me explain more about the hardware layout.
> > The interrupt controller space is decoded starting from 0x12100000,
> > which includes both a set of global configuration registers and
> > individual interrupt controller instances.
> >
> > The region at 0x12100000 contains global interrupt control registers
> > (e.g., protect config, interrupt routing etc.).
> 
> This does not explain me why global controller registers are a BUS or MFD as
> you claimed here.
> >
> > The actual interrupt controller logic starts at 0x12101b00, where each
> > sub-controller instance (e.g., intc0_11, intc0_12, etc.) has its own set of
> registers.
> 
> I don't know what is a "global controller register" and "own set of registers". If
> you have device spanning over multiple memory blocks, device takes multiple
> 'reg' entries for example. There are many other configurations, depending on
> real hardware and relationships. Just look at other DTS.


Here are two possible representations of the interrupt controller layout for the AST2700 platform:
Please advise which approach would be more appropriate or preferred? 

Option 1: Hierarchical representation with a parent node
This models the entire interrupt controller registers space (start from 0x12100000), 
where the parent node includes the global register area and acts as a container for per-instance sub-controllers:

    intc0: interrupt-controller@12100000 {
        compatible = "aspeed,intc-controller";
        reg = <0 0x12100000 0x4000>;
		...................
        intc0_11: interrupt-controller@1b00 {
            compatible = "aspeed,ast2700-intc-ic";
            reg = <0x1b00 0x100>;
			...................        };
    };
And I find the others dtsi have global register use syscon ex.
https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/sprd/ums512.dtsi#L177-L192

Option 2: Flat representation with only the per-domain node
This focuses on just the interrupt controller logic at 0x12101b00, skipping the global register modeling:

    intc0_11: interrupt-controller@12101b00 {
        compatible = "aspeed,ast2700-intc-ic";
        reg = <0 0x12101b00 0x100>;
		...................
    };




> 
> Best regards,
> Krzysztof

Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Krzysztof Kozlowski]

On 16/06/2025 09:52, Ryan Chen wrote:
> 
>> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device
>> tree
>>
>> On 16/06/2025 08:54, Ryan Chen wrote:
>>>> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700
>>>> SoC device tree
>>>>
>>>> On 16/06/2025 08:32, Ryan Chen wrote:
>>>>>>>
>>>>>>> But I don't know your previous "NAK, never tested" mean.
>>>>>>> I did make CHECK_DTBS=y arch/arm64/boot/dts/aspeed/ don't see the
>>>>>>> fail with
>>>>>>> intc0: interrupt-controller@12100000 {
>>>>>>> 	compatible = "simple-mfd";
>>>>>>>
>>>>>>> So, could you point me more test instruction for this?
>>>>>> See syscon.yaml. And writing bindings or talks on conferences:
>>>>>> simple-mfd cannot be alone.
>>>>>>
>>>>>
>>>>>         intc0: interrupt-controller@12100000 { Sorry, do you mean
>>>>> add by following?
>>>>> 				 compatible = "aspeed,intc-controller", "simple-mfd";
>>>>>  					.....
>>>>>                  intc0_11: interrupt-controller@1b00 {
>>>>> 					compatible = "aspeed,ast2700-intc-ic";
>>>>>  					......
>>>>>                  };
>>>>>          };
>>>>
>>>> Maybe, but you said this is base address, so how can it be some
>>>> separate device?
>>>>
>>>> I mean really, don't add fake nodes just to satisfy some device instantiation.
>>>> Describe what this really is. That is the job of DTS. Not some fake nodes.
>>>
>>>
>>> Understood. Let me explain more about the hardware layout.
>>> The interrupt controller space is decoded starting from 0x12100000,
>>> which includes both a set of global configuration registers and
>>> individual interrupt controller instances.
>>>
>>> The region at 0x12100000 contains global interrupt control registers
>>> (e.g., protect config, interrupt routing etc.).
>>
>> This does not explain me why global controller registers are a BUS or MFD as
>> you claimed here.
>>>
>>> The actual interrupt controller logic starts at 0x12101b00, where each
>>> sub-controller instance (e.g., intc0_11, intc0_12, etc.) has its own set of
>> registers.
>>
>> I don't know what is a "global controller register" and "own set of registers". If
>> you have device spanning over multiple memory blocks, device takes multiple
>> 'reg' entries for example. There are many other configurations, depending on
>> real hardware and relationships. Just look at other DTS.
> 
> 
> Here are two possible representations of the interrupt controller layout for the AST2700 platform:
> Please advise which approach would be more appropriate or preferred? 
> 
> Option 1: Hierarchical representation with a parent node
> This models the entire interrupt controller registers space (start from 0x12100000), 
> where the parent node includes the global register area and acts as a container for per-instance sub-controllers:
> 
>     intc0: interrupt-controller@12100000 {
>         compatible = "aspeed,intc-controller";
>         reg = <0 0x12100000 0x4000>;
> 		...................
>         intc0_11: interrupt-controller@1b00 {
>             compatible = "aspeed,ast2700-intc-ic";
>             reg = <0x1b00 0x100>;
> 			...................        };
>     };
> And I find the others dtsi have global register use syscon ex.
> https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/sprd/ums512.dtsi#L177-L192
> 
> Option 2: Flat representation with only the per-domain node
> This focuses on just the interrupt controller logic at 0x12101b00, skipping the global register modeling:
> 
>     intc0_11: interrupt-controller@12101b00 {
>         compatible = "aspeed,ast2700-intc-ic";
>         reg = <0 0x12101b00 0x100>;
> 		...................
>     };
> 


I don't understand this: you already have a binding for this, you
already described the device, so why now this is being changed?

You are supposed to send complete bindings for your device (see writing
bindings). Not some half-baked parts and then half year later different
DTS which points that your bindings were just incomplete.

Look how a completely new SoC is supposed to be upstreamed, on the day
of public announcement of the hardware:

https://lore.kernel.org/all/20231121-topic-sm8650-upstream-dt-v3-0-db9d0507ffd3@linaro.org/

Are all or most bindings posted? Yes
Is DTS for all devices from above bindings posted? Yes
Do we see complete picture? Yes

I still have no clue what is global interrupt registers. I already said
it, but you keep repeating the same. I have no clue.

Why this would be a parent?

Why this would not be a parent?

Best regards,
Krzysztof

Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Krzysztof Kozlowski]

On 12/06/2025 12:09, Ryan Chen wrote:
> +
> +	soc0: soc@10000000 {
> +		compatible = "simple-bus";
> +		reg = <0x0 0x10000000 0x10000000>;
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		syscon0: syscon@12c02000 {
> +			compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";

This makes no sense - no children here.

> +			reg = <0x0 0x12c02000 0x1000>;
> +			ranges = <0x0 0x0 0 0x12c02000 0x1000>;

Neither this.

> +			#address-cells = <2>;
> +			#size-cells = <1>;

Nor this.


Best regards,
Krzysztof

RE: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Ryan Chen]

> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device
> tree
> 
> On 12/06/2025 12:09, Ryan Chen wrote:
> > +
> > +	soc0: soc@10000000 {
> > +		compatible = "simple-bus";
> > +		reg = <0x0 0x10000000 0x10000000>;
> > +		#address-cells = <2>;
> > +		#size-cells = <1>;
> > +		ranges;
> > +
> > +		syscon0: syscon@12c02000 {
> > +			compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
> 
> This makes no sense - no children here.
> 
> > +			reg = <0x0 0x12c02000 0x1000>;
> > +			ranges = <0x0 0x0 0 0x12c02000 0x1000>;
> 
> Neither this.
> 
> > +			#address-cells = <2>;
> > +			#size-cells = <1>;
> 
> Nor this.


I will add by following. 
                 syscon0: syscon@12c02000 {
                        compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
                        reg = <0x0 0x12c02000 0x0 0x1000>;
                        ranges = <0x0 0x0 0 0x12c02000 0 0x1000>;
                        #address-cells = <2>;
                        #size-cells = <2>;
                        #clock-cells = <1>;
                        #reset-cells = <1>;

                        silicon-id@0 {
                                compatible = "aspeed,ast2700-silicon-id", "aspeed,silicon-id";
                                reg = <0 0x0 0 0x4>;
                        };

                        scu_ic0: interrupt-controller@1D0 {
                                #interrupt-cells = <1>;
                                compatible = "aspeed,ast2700-scu-ic0";
                                reg = <0 0x1d0 0 0xc>;
                                interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                        };

                        scu_ic1: interrupt-controller@1E0 {
                                #interrupt-cells = <1>;
                                compatible = "aspeed,ast2700-scu-ic1";
                                reg = <0 0x1e0 0 0xc>;
                                interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                        };

                        pinctrl0: pinctrl@400 {
                                compatible = "aspeed,ast2700-soc0-pinctrl";
                                reg = <0 0x400 0 0x600>;
                        };
                };

              syscon1: syscon@14c02000 {
                        compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
                        reg = <0x0 0x14c02000 0x0 0x1000>;
                        ranges = <0x0 0x0 0x0 0x14c02000 0x0 0x1000>;
                        #address-cells = <2>;
                        #size-cells = <2>;
                        #clock-cells = <1>;
                        #reset-cells = <1>;

                        scu_ic2: interrupt-controller@100 {
                                #interrupt-cells = <1>;
                                compatible = "aspeed,ast2700-scu-ic2";
                                reg = <0 0x100 0 0x8>;
                                interrupts-extended = <&intc1_5 0>;
                                interrupt-controller;
                        };

                        scu_ic3: interrupt-controller@108 {
                                #interrupt-cells = <1>;
                                compatible = "aspeed,ast2700-scu-ic3";
                                reg = <0 0x108 0 0x8>;
                                interrupts-extended = <&intc1_5 26>;
                                interrupt-controller;
                        };

                        pinctrl1: pinctrl@400 {
                                compatible = "aspeed,ast2700-soc1-pinctrl";
                                reg = <0x0 0x400 0x0 0x100>;
                        };
                };

> 
> 
> Best regards,
> Krzysztof

[PATCH v0 4/5] arm64: dts: aspeed: Add AST2700 EVB device tree

[Ryan Chen]

- Add ast2700-evb.dts for the ASPEED AST2700 Evaluation Board.
- Set board model and compatible strings: "aspeed,ast2700-evb",
"aspeed,ast2700".
- Reference the common AST2700 SoC device tree aspeed-g7.dtsi.
- Define memory layout and reserved-memory regions for
MCU firmware, ATF, and OP-TEE.
- Add OP-TEE firmware node with SMC method.
- Set up serial12 as the default console.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 arch/arm64/boot/dts/Makefile               |  1 +
 arch/arm64/boot/dts/aspeed/Makefile        |  4 ++
 arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 54 ++++++++++++++++++++++
 3 files changed, 59 insertions(+)
 create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
 create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 79b73a21ddc2..d9c3e58b9ca5 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -35,3 +35,4 @@ subdir-y += tesla
 subdir-y += ti
 subdir-y += toshiba
 subdir-y += xilinx
+subdir-y += aspeed
diff --git a/arch/arm64/boot/dts/aspeed/Makefile b/arch/arm64/boot/dts/aspeed/Makefile
new file mode 100644
index 000000000000..ffe7e15017cc
--- /dev/null
+++ b/arch/arm64/boot/dts/aspeed/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+dtb-$(CONFIG_ARCH_ASPEED) += \
+	ast2700-evb.dtb
diff --git a/arch/arm64/boot/dts/aspeed/ast2700-evb.dts b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
new file mode 100644
index 000000000000..ecd4b55931e7
--- /dev/null
+++ b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+#include "aspeed-g7.dtsi"
+
+/ {
+	model = "ASPEED ast2700 Development Board";
+	compatible = "aspeed,ast2700-evb", "aspeed,ast2700";
+
+	aliases {
+		serial12 = &serial12;
+	};
+
+	chosen {
+		stdout-path = &serial12;
+	};
+
+	firmware {
+		optee: optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+
+	memory@400000000 {
+		device_type = "memory";
+		reg = <0x4 0x00000000 0x40000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		mcu_fw: mcu-firmware@42fe00000 {
+			reg = <0x4 0x2fe00000 0x200000>;
+			no-map;
+		};
+
+		atf: trusted-firmware-a@430000000 {
+			reg = <0x4 0x30000000 0x80000>;
+			no-map;
+		};
+
+		optee_core: optee-core@430080000 {
+			reg = <0x4 0x30080000 0x1000000>;
+			no-map;
+		};
+	};
+};
+
+&serial12 {
+	status = "okay";
+};
-- 
2.34.1

Re: [PATCH v0 4/5] arm64: dts: aspeed: Add AST2700 EVB device tree

[Krzysztof Kozlowski]

On 12/06/2025 12:09, Ryan Chen wrote:
> - Add ast2700-evb.dts for the ASPEED AST2700 Evaluation Board.
> - Set board model and compatible strings: "aspeed,ast2700-evb",
> "aspeed,ast2700".
> - Reference the common AST2700 SoC device tree aspeed-g7.dtsi.
> - Define memory layout and reserved-memory regions for
> MCU firmware, ATF, and OP-TEE.
> - Add OP-TEE firmware node with SMC method.
> - Set up serial12 as the default console.
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>

How this can be patch 0?

You need to start using standard tools: git and b4 (see submitting
patches and other process docs).


Best regards,
Krzysztof

Re: [PATCH v0 4/5] arm64: dts: aspeed: Add AST2700 EVB device tree

[Krzysztof Kozlowski]

On 12/06/2025 12:14, Krzysztof Kozlowski wrote:
> On 12/06/2025 12:09, Ryan Chen wrote:
>> - Add ast2700-evb.dts for the ASPEED AST2700 Evaluation Board.
>> - Set board model and compatible strings: "aspeed,ast2700-evb",
>> "aspeed,ast2700".
>> - Reference the common AST2700 SoC device tree aspeed-g7.dtsi.
>> - Define memory layout and reserved-memory regions for
>> MCU firmware, ATF, and OP-TEE.
>> - Add OP-TEE firmware node with SMC method.
>> - Set up serial12 as the default console.
>>
>> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> 
> How this can be patch 0?
> 

I meant: v0.

> You need to start using standard tools: git and b4 (see submitting
> patches and other process docs).
> 
> 

Best regards,
Krzysztof

[PATCH v0 5/5] arm64: configs: Update defconfig for AST2700 platform support

[Ryan Chen]

- Enable options for ASPEED AST2700 SoC.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 897fc686e6a9..c9d90aa07e59 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -38,6 +38,7 @@ CONFIG_ARCH_AIROHA=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_ALPINE=y
 CONFIG_ARCH_APPLE=y
+CONFIG_ARCH_ASPEED=y
 CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM2835=y
 CONFIG_ARCH_BCM_IPROC=y
-- 
2.34.1

Re: [PATCH v0 5/5] arm64: configs: Update defconfig for AST2700 platform support

[Krzysztof Kozlowski]

On 12/06/2025 12:09, Ryan Chen wrote:
> - Enable options for ASPEED AST2700 SoC.

Why is this "-"? Is this a patch format?

Look at other commits to this file. You can use `git log -- PATH` to
understand how people write commits.

Best regards,
Krzysztof

Re: [PATCH v0 0/5] Add initial AST2700 SoC support

[Rob Herring (Arm)]

On Thu, 12 Jun 2025 18:09:28 +0800, Ryan Chen wrote:
> This patch series introduces initial support for the Aspeed AST2700 SoC
> and the AST2700 Evaluation Board (EVB) to the Linux kernel. The AST2700
> is the 7th generation Baseboard Management Controller (BMC) SoC from Aspeed,
> featuring improved performance, enhanced security, and expanded I/O
> capabilities compared to previous generations.
> 
> The patchset includes the following changes:
> - Device tree bindings for AST2700 boards.
> - Addition of the AST2700 platform to the Kconfig menu.
> - Basic device tree for the AST2700 SoC.
> - Device tree for the AST2700-EVB.
> - Updated defconfig to enable essential options for AST2700.
> 
> Ryan Chen (5):
>   dt-bindings: arm: aspeed: Add AST2700 board compatible
>   arm64: Kconfig: Add Aspeed SoC family (ast2700) platform option
>   arm64: dts: aspeed: Add initial AST2700 SoC device tree
>   arm64: dts: aspeed: Add AST2700 EVB device tree
>   arm64: configs: Update defconfig for AST2700 platform support
> 
>  .../bindings/arm/aspeed/aspeed.yaml           |   5 +
>  arch/arm64/Kconfig.platforms                  |   6 +
>  arch/arm64/boot/dts/Makefile                  |   1 +
>  arch/arm64/boot/dts/aspeed/Makefile           |   4 +
>  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi     | 380 ++++++++++++++++++
>  arch/arm64/boot/dts/aspeed/ast2700-evb.dts    |  54 +++
>  arch/arm64/configs/defconfig                  |   1 +
>  7 files changed, 451 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
>  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
>  create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> 
> --
> 2.34.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: attempting to guess base-commit...
 Base: tags/v6.16-rc1 (exact match)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/aspeed/' for 20250612100933.3007673-1-ryan_chen@aspeedtech.com:

arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: serial@14c33b00 (ns16550a): 'pinctrl-0' is a dependency of 'pinctrl-names'
	from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-consumer.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@100 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 0, 3844]] is too short
	from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@110 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 1, 3844]] is too short
	from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@120 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 2, 3844]] is too short
	from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@130 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 3, 3844]] is too short
	from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@140 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 4, 3844]] is too short
	from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@150 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 5, 3844]] is too short
	from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#

Re: [PATCH v0 0/5] Add initial AST2700 SoC support

[Andrew Jeffery]

On Thu, 2025-06-12 at 15:12 -0500, Rob Herring (Arm) wrote:
> 
> On Thu, 12 Jun 2025 18:09:28 +0800, Ryan Chen wrote:
> > This patch series introduces initial support for the Aspeed AST2700 SoC
> > and the AST2700 Evaluation Board (EVB) to the Linux kernel. The AST2700
> > is the 7th generation Baseboard Management Controller (BMC) SoC from Aspeed,
> > featuring improved performance, enhanced security, and expanded I/O
> > capabilities compared to previous generations.
> > 
> > The patchset includes the following changes:
> > - Device tree bindings for AST2700 boards.
> > - Addition of the AST2700 platform to the Kconfig menu.
> > - Basic device tree for the AST2700 SoC.
> > - Device tree for the AST2700-EVB.
> > - Updated defconfig to enable essential options for AST2700.
> > 
> > Ryan Chen (5):
> >   dt-bindings: arm: aspeed: Add AST2700 board compatible
> >   arm64: Kconfig: Add Aspeed SoC family (ast2700) platform option
> >   arm64: dts: aspeed: Add initial AST2700 SoC device tree
> >   arm64: dts: aspeed: Add AST2700 EVB device tree
> >   arm64: configs: Update defconfig for AST2700 platform support
> > 
> >  .../bindings/arm/aspeed/aspeed.yaml           |   5 +
> >  arch/arm64/Kconfig.platforms                  |   6 +
> >  arch/arm64/boot/dts/Makefile                  |   1 +
> >  arch/arm64/boot/dts/aspeed/Makefile           |   4 +
> >  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi     | 380 ++++++++++++++++++
> >  arch/arm64/boot/dts/aspeed/ast2700-evb.dts    |  54 +++
> >  arch/arm64/configs/defconfig                  |   1 +
> >  7 files changed, 451 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
> >  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> >  create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> > 
> > --
> > 2.34.1
> > 
> > 
> > 
> 
> 
> My bot found new DTB warnings on the .dts files added or changed in this
> series.
> 
> Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
> are fixed by another series. Ultimately, it is up to the platform
> maintainer whether these warnings are acceptable or not. No need to reply
> unless the platform maintainer has comments.
> 
> If you already ran DT checks and didn't see these error(s), then
> make sure dt-schema is up to date:
> 
>   pip3 install dtschema --upgrade
> 
> 
> This patch series was applied (using b4) to base:
>  Base: attempting to guess base-commit...
>  Base: tags/v6.16-rc1 (exact match)
> 
> If this is not the correct base, please add 'base-commit' tag
> (or use b4 which does this automatically)
> 
> New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/aspeed/' for 20250612100933.3007673-1-ryan_chen@aspeedtech.com:
> 
> arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: serial@14c33b00 (ns16550a): 'pinctrl-0' is a dependency of 'pinctrl-names'
>         from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-consumer.yaml#
> arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@100 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 0, 3844]] is too short
>         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@110 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 1, 3844]] is too short
>         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@120 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 2, 3844]] is too short
>         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@130 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 3, 3844]] is too short
>         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@140 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 4, 3844]] is too short
>         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@150 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 5, 3844]] is too short
>         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> 

To draw a line in the sand here: while the existing Aspeed devicetrees
(AST2600 and below) produce warnings, I won't accept devicetree patches
for the AST2700 and related boards unless they are warning-free.

Please make sure to test with the dt_binding_check and dtbs_check
targets (or equivalent) before sending your patches.

Andrew

Re: [PATCH v0 0/5] Add initial AST2700 SoC support

[Rob Herring]

On Fri, Jun 13, 2025 at 02:59:43PM +0930, Andrew Jeffery wrote:
> On Thu, 2025-06-12 at 15:12 -0500, Rob Herring (Arm) wrote:
> > 
> > On Thu, 12 Jun 2025 18:09:28 +0800, Ryan Chen wrote:
> > > This patch series introduces initial support for the Aspeed AST2700 SoC
> > > and the AST2700 Evaluation Board (EVB) to the Linux kernel. The AST2700
> > > is the 7th generation Baseboard Management Controller (BMC) SoC from Aspeed,
> > > featuring improved performance, enhanced security, and expanded I/O
> > > capabilities compared to previous generations.
> > > 
> > > The patchset includes the following changes:
> > > - Device tree bindings for AST2700 boards.
> > > - Addition of the AST2700 platform to the Kconfig menu.
> > > - Basic device tree for the AST2700 SoC.
> > > - Device tree for the AST2700-EVB.
> > > - Updated defconfig to enable essential options for AST2700.
> > > 
> > > Ryan Chen (5):
> > >   dt-bindings: arm: aspeed: Add AST2700 board compatible
> > >   arm64: Kconfig: Add Aspeed SoC family (ast2700) platform option
> > >   arm64: dts: aspeed: Add initial AST2700 SoC device tree
> > >   arm64: dts: aspeed: Add AST2700 EVB device tree
> > >   arm64: configs: Update defconfig for AST2700 platform support
> > > 
> > >  .../bindings/arm/aspeed/aspeed.yaml           |   5 +
> > >  arch/arm64/Kconfig.platforms                  |   6 +
> > >  arch/arm64/boot/dts/Makefile                  |   1 +
> > >  arch/arm64/boot/dts/aspeed/Makefile           |   4 +
> > >  arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi     | 380 ++++++++++++++++++
> > >  arch/arm64/boot/dts/aspeed/ast2700-evb.dts    |  54 +++
> > >  arch/arm64/configs/defconfig                  |   1 +
> > >  7 files changed, 451 insertions(+)
> > >  create mode 100644 arch/arm64/boot/dts/aspeed/Makefile
> > >  create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi
> > >  create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts
> > > 
> > > --
> > > 2.34.1
> > > 
> > > 
> > > 
> > 
> > 
> > My bot found new DTB warnings on the .dts files added or changed in this
> > series.
> > 
> > Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
> > are fixed by another series. Ultimately, it is up to the platform
> > maintainer whether these warnings are acceptable or not. No need to reply
> > unless the platform maintainer has comments.
> > 
> > If you already ran DT checks and didn't see these error(s), then
> > make sure dt-schema is up to date:
> > 
> >   pip3 install dtschema --upgrade
> > 
> > 
> > This patch series was applied (using b4) to base:
> >  Base: attempting to guess base-commit...
> >  Base: tags/v6.16-rc1 (exact match)
> > 
> > If this is not the correct base, please add 'base-commit' tag
> > (or use b4 which does this automatically)
> > 
> > New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/aspeed/' for 20250612100933.3007673-1-ryan_chen@aspeedtech.com:
> > 
> > arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: serial@14c33b00 (ns16550a): 'pinctrl-0' is a dependency of 'pinctrl-names'
> >         from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-consumer.yaml#
> > arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@100 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 0, 3844]] is too short
> >         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> > arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@110 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 1, 3844]] is too short
> >         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> > arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@120 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 2, 3844]] is too short
> >         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> > arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@130 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 3, 3844]] is too short
> >         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> > arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@140 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 4, 3844]] is too short
> >         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> > arch/arm64/boot/dts/aspeed/ast2700-evb.dtb: interrupt-controller@150 (aspeed,ast2700-intc-ic): interrupts-extended: [[6, 5, 3844]] is too short
> >         from schema $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
> > 
> 
> To draw a line in the sand here: while the existing Aspeed devicetrees
> (AST2600 and below) produce warnings, I won't accept devicetree patches
> for the AST2700 and related boards unless they are warning-free.

Thank you. If you hadn't said it, I would have. Hopefully there's some 
IP reuse that will get the older stuff fixed (if the fix is in the 
schema).

Rob