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b=VdVV4V5YyBeklNYMLlTDcpWHCtmgoy7lcLNQr36qF84kCLsoNnb/nc/Hd9v1lTf/W o7qbp9x44oun7kbQvUe1AOhr/28CoD/9ZLPqBuhRng+BHIx/JHeb6ciGFQoJxTeeJ5 6uIXhQua2Lqsdmq12APk08T5vkuCOZib9/0JV6nZ0DSnQMto9gc1Wu0T8aXW2IVjyD 4vXyYoPEoBWLrCr9l6ecnygTl2IFeqaZfamMw5da2cGnJiDGnq7Jc5yqLvuq7W4oRs RsM0t4sks6ZqXJ8i6dPi0oTJP+hNR7qCT98HzKgUy21OVHfLmENgNSWZsQUDj3efHO AmDX4/IYAwGBw== Received: from [192.168.68.117] (unknown [180.150.112.139]) by mail.codeconstruct.com.au (Postfix) with ESMTPSA id 1C32964952; Fri, 6 Nov 2026 12:50:45 +0800 (AWST) Message-ID: <7eda59ffde46142602c6d8e425fd4097872ee8c4.camel@codeconstruct.com.au> Subject: Re: [PATCH v4 3/3] ARM: dts: aspeed: add Intel JNCRP BMC From: Andrew Jeffery To: Dawid Glazik , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, maciej.lawniczak@intel.com, Andrew Lunn Date: Fri, 06 Nov 2026 15:20:44 +1030 In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-0+deb13u1 X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , Precedence: list X-Archived-By: MIME-Version: 1.0 X-Spam-Status: No, score=-20.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Mon, 2026-10-26 at 17:40 +0100, Dawid Glazik wrote: > Add the initial AST2600 device tree for the Intel JNCRP BMC platform. Can you please provide more information about the platform design and its purpose? >=20 > Signed-off-by: Dawid Glazik > Reviewed-by: Andrew Lunn > --- > v4: > =C2=A0 - Rebased onto aspeed/arm/dt of bmc/linux.git, no other changes > v3: > =C2=A0 - Sorted nodes alphabetically > =C2=A0 - Sorted properties per dts-coding-style > =C2=A0 - Removed lpc-snoop label > =C2=A0 - Removed &i3c_global since it's enabled by default > =C2=A0 - Added &kcs3 and replaced flash layout with 128MB one > =C2=A0 - Restored Reviewed-by from Andrew Lunn, dropped by mistake in v2 > v2: > =C2=A0 - Reviewed-by: Andrew Lunn for nodes: &mdio1, &mac1 > =C2=A0 - Replace bootargs console=3DttyS4,115200n8 with stdout-path =3D &= uart5 > --- > =C2=A0arch/arm/boot/dts/aspeed/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 1 + > =C2=A0.../dts/aspeed/aspeed-bmc-intel-jncrp.dts=C2=A0=C2=A0=C2=A0=C2=A0 |= 276 ++++++++++++++++++ > =C2=A02 files changed, 277 insertions(+) > =C2=A0create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-intel-jncrp.= dts >=20 > diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed= /Makefile > index 1e4154f12228..5e685a625883 100644 > --- a/arch/arm/boot/dts/aspeed/Makefile > +++ b/arch/arm/boot/dts/aspeed/Makefile > @@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_ASPEED) +=3D \ > =C2=A0 aspeed-bmc-ibm-sbp1.dtb \ > =C2=A0 aspeed-bmc-ibm-system1.dtb \ > =C2=A0 aspeed-bmc-intel-avcrp.dtb \ > + aspeed-bmc-intel-jncrp.dtb \ > =C2=A0 aspeed-bmc-intel-s2600wf.dtb \ > =C2=A0 aspeed-bmc-inspur-fp5280g2.dtb \ > =C2=A0 aspeed-bmc-inspur-nf5280m6.dtb \ > diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-intel-jncrp.dts b/arch/a= rm/boot/dts/aspeed/aspeed-bmc-intel-jncrp.dts > new file mode 100644 > index 000000000000..e66ea7f00fed > --- /dev/null > +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-intel-jncrp.dts > @@ -0,0 +1,276 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +// Copyright 2025 Intel Corporation > + > +/dts-v1/; > + > +#include "aspeed-g6.dtsi" > +#include > + > +/ { > + compatible =3D "intel,jncrp-bmc", "aspeed,ast2600"; > + model =3D "Intel JNCRP BMC"; > + > + aliases { > + serial4 =3D &uart5; > + }; > + > + chosen { > + bootargs =3D "earlycon"; Please remove bootargs here, earlycon is for debugging. Andrew