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24 Jun 2025 03:50:10 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Tue, 24 Jun 2025 13:50:06 +0300 (EEST) To: Jacky Chou cc: "bhelgaas@google.com" , "lpieralisi@kernel.org" , "kwilczynski@kernel.org" , "mani@kernel.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "joel@jms.id.au" , "andrew@codeconstruct.com.au" , "vkoul@kernel.org" , "kishon@kernel.org" , "linus.walleij@linaro.org" , "p.zabel@pengutronix.de" , "linux-aspeed@lists.ozlabs.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , LKML , "linux-phy@lists.infradead.org" , "openbmc@lists.ozlabs.org" , "linux-gpio@vger.kernel.org" , "elbadrym@google.com" , "romlem@google.com" , "anhphan@google.com" , "wak@google.com" , "yuxiaozhang@google.com" , BMC-SW Subject: Re: [PATCH 7/7] pci: aspeed: Add ASPEED PCIe host controller driver In-Reply-To: Message-ID: References: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> <20250613033001.3153637-8-jacky_chou@aspeedtech.com> <40d1c5bd-0457-55ea-2514-ba27e6a4c720@linux.intel.com> X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Mon, 23 Jun 2025, Jacky Chou wrote: > > > +static bool aspeed_ast2700_get_link(struct aspeed_pcie *pcie) { > > > + u32 reg; > > > + bool link; > > > + > > > + regmap_read(pcie->pciephy, PEHR_MISC_300, ®); > > > + if (reg & CAPABILITY_GEN2) { > > > + regmap_read(pcie->pciephy, PEHR_MISC_344, ®); > > > + link = !!(reg & LINK_STATUS_GEN2); > > > + } else { > > > + regmap_read(pcie->pciephy, PEHR_MISC_358, ®); > > > + link = !!(reg & LINK_STATUS_GEN4); > > > > While I don't entirely know the meaning of these bits, what if the link is not > > using maximum speed it is capable of, does this check misbehave? > > > > In our AST2700, there are gen4 RC and gen2 RC. > Therefore, here will get capability to confirm it is gen2 or gen4. > And the link status is in different register. Okay, but then I'm a bit worried the naming of the defines as "Link Status" has a well-known meaning in PCIe Spec so it is confusing to call something else LINK_STATUS_*. Does that name come from some AST spec? In not, change the define naming. If yes, you should prefix it with so it is clear this is not referring to a generic PCIe thing and I suggest also adding a comment above those defines too so anyone looking them later won't wonder if you're just duplicating something from the PCIe spec. -- i.