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Wed, 08 Jul 2026 08:38:23 -0700 (PDT) Received: from gregwork.sec.9e.network ([188.111.3.154]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47a9e4d8410sm44254136f8f.15.2026.07.08.08.38.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2026 08:38:22 -0700 (PDT) From: =?UTF-8?q?Gr=C3=A9goire=20Layet?= To: joel@jms.id.au, andrew@codeconstruct.com.au, lkundrak@v3.sk, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: andrew@lunn.ch, jacky_chou@aspeedtech.com, yh_chung@aspeedtech.com, ninad@linux.ibm.com, anirudhsriniv@gmail.com, linux-serial@vger.kernel.org, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Gr=C3=A9goire=20Layet?= Subject: [PATCH v4 0/7] soc: aspeed: Add BMC and host driver for PCIe BMC device Date: Wed, 8 Jul 2026 15:35:52 +0000 Message-ID: X-Mailer: git-send-email 2.54.0 X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a v4 for upstreaming the VUART over PCIe BMC device driver. The initial driver is from the ASPEED kernel SDK (master-v6.18) [1]. There are two drivers: a BMC-side driver and a host-side driver. Together they enable host<->BMC VUART communication via PCIe. The virtual UART is an 8250-compatible register set. On the AST2600, two VUARTs can be exposed over PCI via the PCI BMC device. The host cannot access the BMC's memory. Only the exposed features are accessible. These are the KCS4 channel and 2 VUARTs. There is also some mailbox register functionality for a communication between the host and the BMC. More information can be found here [2]. The v3 and this v4 mainly modifies the BMC driver and focuses on VUART. The BMC driver is now incorporated into the '8250_aspeed_vuart' driver. A specific flag can be set to indicate that the VUART should be used over PCI. Several changes have been made to the 8250 device tree binding and the 'aspeed-g6.dtsi'. This v4 serves as a resend of the v3 while applying Krzysztof's review. Changes since v3 [3]: - Add the aspeed,ast2600-vuart compatible entry to the '8250' DT binding - Add the aspeed,ast2600-vuart compatible property in 'aspeed-g6.dtsi' - Add the aspeed,vuart-over-pci boolean property to the '8250' DT binding, only for the aspeed,ast2600-vuart - Add the syscon phandle property required for aspeed,vuart-over-pci. - Add the aspeed,vuart-over-pci flag and syscon phandle to the vuart3 and vuart4 - Cleanup the VUART over PCI code in the '8250_aspeed_vuart' driver. - Further cleanup of the host side driver. The host-side driver is still in /soc/aspeed/, as it is very specific to this SoC for me. I didn't receive any feedback on where to put this driver. I can, of course, change this to the relevant location. It's important to consider that the host driver will do multiple functions. The AST2600 also supports LPC over PCI, with a specific KCS channel (KCS4). This driver should also be used to enable the IPMI automatically via this KCS channel. The UART and the IPMI will depend on the same PCI resource (BAR1), so this must be configured in one driver. As with v3, VUART data flow and MSI interrupts have been verified working on the test hardware. Tested on: BMC: - Asus IPMI Kommando Card R1.01, AST2600 A3. - OpenBMC Host: - Linux kernel v7.0.0 This series only supports AST2600; the AST2700 is not supported. Same as v3, I would like to know whether I should add the 'lpc-io-reg' and 'lpc-interrupt' values to the vuart3 and vuart4 nodes directly in the 'aspeed-g6.dtsi'. The host driver is not capable of finding the vuart address on its own, so they are hardcoded to 0x3f8 and 0x2f8. It will not work with other addresses, so perhaps they should be in the .dtsi to ensure the correct configuration for the 2 vuart over PCI. For the interrupt number, my test is working with interrupt = 0 for vuart3 and interrupt = 1 for vuart4. I don't fully understand how the silicon routes MSI numbers to the VUART but the following combination is working : | host MSI idx | BMC lpc-interrupts | VUART3 | 16 | 0 | VUART4 | 17 | 1 | The original ASPEED driver used MSI index 15 for the VUART4. I tested every lpc-interrupts on the BMC from 0 to 15, but none of them worked with the host MSI index set to 15. For me, the silicon only routes the MSI index 16 to VUART3 and 17 to VUART4, and the lpc-interrupt needs to match the 4 least significant bits. I might be wrong on this explanation but the data path is working with those numbers. There is no explanation for any of this in the datasheet. [1]: https://github.com/AspeedTech-BMC/linux/tree/aspeed-master-v6.18/drivers/soc/aspeed [2]: https://lore.kernel.org/linux-aspeed/CAFi2wKYOAotiezepDqaR5PZDqDaPKKDfAEnpx5EHC0mL39hy6w@mail.gmail.com/ [3]: https://lore.kernel.org/linux-aspeed/cover.1782224059.git.gregoire.layet@9elements.com/ Grégoire Layet (7): dt-bindings: serial: 8250: aspeed: add compatible string for ast2600 dt-bindings: serial: 8250: aspeed: add aspeed,vuart-over-pci bool prop serial: 8250_aspeed_vuart: add aspeed,ast2600-vuart compatible string serial: 8250_aspeed_vuart: add VUART over PCI soc: aspeed: add host-side PCIe BMC device driver ARM: dts: aspeed: g6: Change vuart compatible string for ast2600 ARM: dts: aspeed: g6: add aspeed,vuart-over-pci prop to vuart3 and 4 .../devicetree/bindings/serial/8250.yaml | 46 ++++- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 12 +- drivers/soc/aspeed/Kconfig | 15 ++ drivers/soc/aspeed/Makefile | 1 + drivers/soc/aspeed/aspeed-host-bmc-dev.c | 174 ++++++++++++++++++ drivers/tty/serial/8250/8250_aspeed_vuart.c | 87 +++++++++ 6 files changed, 323 insertions(+), 12 deletions(-) create mode 100644 drivers/soc/aspeed/aspeed-host-bmc-dev.c base-commit: 564edaca14861ba9e58d4e646d272c677296d285 -- 2.54.0