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h=Subject:From:To:Cc:Date:In-Reply-To:References; b=ck4KNK93oNFOKpL0t5ECzFTFAm6r2CgNMF/Tb2zwmGPh+HR2xnErZiTYVLNQdKXgL b9boyAHmUkwvivRGZstj7UDqgmciRPlIeOtoimn3N5XRZQ6R9oBC/M0ly8Sc4ufX5l iiiJ5a4lHOH+MruCaCiyuLeZVijM6HV5+Pg33m1vdW4PDBYkBQrD/Wo08jABrGmPCY PWJg87ONt1ShjPxtzyysKYv9nhK5UScccXz6DNKMPRPZhquFavdn9I6NnhsNA3ixmE 1abdUpm6UGviduDtzScA7R5JClHHRENS8TC1ThX8eHK0db+PRcKwQ7Naofn8YS3cQ8 KFDL8tsJqlCCA== Received: from [192.168.68.112] (203-173-1-6.dyn.iinet.net.au [203.173.1.6]) by mail.codeconstruct.com.au (Postfix) with ESMTPSA id CF2B976191; Wed, 19 Feb 2025 09:04:31 +0800 (AWST) Message-ID: Subject: Re: [PATCH v1 3/3] soc: aspeed: lpc-pcc: Add PCC controller support From: Andrew Jeffery To: Kevin Chen , "joel@jms.id.au" , Z-ChiaWei Wang , "linux-aspeed@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Mo Elbadry Cc: "tomer.maimon" , Krzysztof Kozlowski , "lee@kernel.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" Date: Wed, 19 Feb 2025 11:34:31 +1030 In-Reply-To: References: <20250217114831.3225970-1-kevin_chen@aspeedtech.com> <20250217114831.3225970-4-kevin_chen@aspeedtech.com> <6fd7cd57261ddf9831f57dc4c637b24e9f8982d9.camel@codeconstruct.com.au> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.4-2 X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: MIME-Version: 1.0 On Tue, 2025-02-18 at 11:11 +0000, Kevin Chen wrote: > > On Mon, 2025-02-17 at 13:00 +0100, Krzysztof Kozlowski wrote: > > > On 17/02/2025 12:48, Kevin Chen wrote: > > > > + > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pcc->mdev.parent =3D dev= ; > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pcc->mdev.minor =3D MISC= _DYNAMIC_MINOR; > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pcc->mdev.name =3D devm_= kasprintf(dev, GFP_KERNEL, > > > > "%s%d", > > > > DEVICE_NAME, > > > >=20 > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0pcc->mdev_id); > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pcc->mdev.fops =3D &pcc_= fops; > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0rc =3D misc_register(&pc= c->mdev); > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (rc) { > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0dev_err(dev, "Couldn't register misc > > > > device\n"); > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0goto err_free_kfifo; > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > > >=20 > > > You cannot expose user-space interfaces from SoC drivers. Use > > > appropriate subsystem for this with proper ABI documentation. > > >=20 > > > See: > > > https://lore.kernel.org/all/bc5118f2-8982-46ff-bc75-d0c71475e909@app.= f > > > astmail.com/ > > > and more discussions on LKML > >=20 > > Further, drivers/misc/aspeed-lpc-snoop.c already exists: > >=20 > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/comm= it/?id=3D > > 9f4f9ae81d0affc182f54dd00285ddb90e0b3ae1 > >=20 > > Kevin: Did you consider reworking it? > Andrew: No, I do not rework it but add the post code capture driver > using the SNOOP registers. As a result, I add some code in > aspeed_a2600_15 to check the SNOOP enable bit. PCC driver probe abort > if snoop is enabled. Hmm, I think OpenBMC's history regarding POST code support caused some confusion on my part. For whatever reason, the snoop device was used as a source of POST codes despite the existence of the dedicated POST code hardware since at least the AST2400, but... > PCC is used for port I/O byte snooping over eSPI. ... it seems that they're largely interchangeable, just with different hardware features (PCC has DMA)? My impression is that the snoop device could also be used over eSPI? >=20 >=20 > >=20 > > Nuvoton have a similar capability in their NPCM BMC SoC(s) with the > > "BPC" > > ("BIOS POST Code" controller). There should be some consensus on > > the binding > > and userspace interface. This is still the case. Andrew