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b=KMhiSzgs0FiJF1ZY/gHkQ+gt0zCunXJNaCStpNJfIiNdsSrkcKNb5QW4c5Grx5QBE ENlC2WhRG/AQG+nVfFt3lXtpRvLKPI2NNgQ9qbL7UR3SevefGE6eu+AJjhD3bpI9W5 NdlWFj4g10N/XCODybZzWndp94Kxey7+q8n6iayvQknF3uu7P7Hjm8WxrydLnQOWuE 9qrSj5odCfF9zbpupYHRX27hyo26d3auWuZsCYSgmwTzB+6twIozI8Lilaw0jUie/B O8QIOOAqxm2R99ITRmwjfSZaBV37z6Vl0/kSbm27JvCsd+Gkm6Pc+aJAldaXi+ik7J VM5DHsKt4rviQ== Received: from [192.168.68.115] (unknown [180.150.112.60]) by mail.codeconstruct.com.au (Postfix) with ESMTPSA id D19B36597C; Thu, 26 Mar 2026 14:10:10 +0800 (AWST) Message-ID: Subject: Re: [PATCH v5 3/8] ARM: dts: aspeed: yosemite5: Add new SGPIO line names and rename signal From: Andrew Jeffery To: Kevin Tung Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Amithash Prasasd , Kevin Tung , Ken Chen , Leo Yang , Jackson Liu , Daniel Hsu Date: Thu, 26 Mar 2026 16:40:10 +1030 In-Reply-To: References: <20260223-yv5_revise_dts-v5-0-fc913e902488@gmail.com> <20260223-yv5_revise_dts-v5-3-fc913e902488@gmail.com> <391b9b912492c07fd1fd7a737b7f49382d361fe2.camel@codeconstruct.com.au> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-0+deb13u1 X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Hi Kevin, On Mon, 2026-03-09 at 11:34 -0700, Kevin Tung wrote: > > Broadly, it feels a lot like you're revising platform designs, then > > trying to make the one devicetree fit the current design, and are not > > explicitly communicating that this is what you're doing. > >=20 > > If that _is_ what you're doing, then we can come up with much better > > schemes to handle it that aren't a constant stream of compatibility > > breaks. > >=20 > > I need you to engage with this concern. > >=20 > Thanks for your feedback. I realize there may be a lack of knowledge > on my side regarding the best practices here. > Could you kindly guide me on how we might implement a better approach > that avoids a constant stream of compatibility breaks? > I=E2=80=99d like to ensure we handle this correctly and align with the > expected workflow. Sure, see the reply I just sent here: https://lore.kernel.org/all/d7794f74b26bbc1ee0a70e39c5671acc018f80eb.camel@= codeconstruct.com.au/ >=20 > > From inspection, I only find patches 1, 4 and 7 of this series to be > > something I'd consider applying without further discussion. > >=20 > Got it. Should I split patches 1, 4, and 7 into a separate series? > This would keep the current series shorter by excluding items that > don=E2=80=99t require further discussion. >=20 I am okay with that, so long as it makes sense in the context of the discussion linked above. Andrew