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h=Subject:From:To:Cc:Date:In-Reply-To:References; b=Hm0yU3a2z4bD4DKGw34ZbPDfR4rW6dPHM7WeC4kQPhcDJVhiSCwheDLG7f3xa0io2 5H/RYHexWp3moLpTsY05ufX3r1a7hG4pRri3O9/rWF1BwkofObOZcvlSrYycV0aCvw REsTNvcvGFUcT+RqwUVeaChsa7nLBkhXXYTFN8O8177yP4u0tm+ranaQChlIQQVTQT QSxuaeyPqBJSz/3EpmlmIJ1R7MiYaGKmPVNyx4yJsBzcQ/5D86RLiQVhPG82yIAogi 0GKMzuIzyg1tVgF91bMvdOtfyWDX4m8iD7aYuO15s1k1US+vBSe2AcUbZpz7Lx2rFF Rt0o3NL2o9G0g== Received: from [192.168.68.113] (unknown [180.150.112.213]) by mail.codeconstruct.com.au (Postfix) with ESMTPSA id E4193766F5; Fri, 17 Oct 2025 13:42:41 +0800 (AWST) Message-ID: Subject: Re: [PATCH v2 2/2] ARM: dts: aspeed: add asrock x470d4u bmc From: Andrew Jeffery To: Tan Siewert , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley Cc: Zev Weiss , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Date: Fri, 17 Oct 2025 16:12:41 +1030 In-Reply-To: <20251011112124.17588-3-tan@siewert.io> References: <20251011112124.17588-1-tan@siewert.io> <20251011112124.17588-3-tan@siewert.io> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.1-1 X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 On Sat, 2025-10-11 at 13:21 +0200, Tan Siewert wrote: > The ASRock Rack X470D4U X470D4U is a single-socket X470-based microATX > motherboard for Ryzen processors with an AST2500 BMC and either 32MB or > 64MB SPI flash. >=20 > This mainboard exists in three known "flavors" which only differ in the > used host NIC, the BMC SPI size and some parts that may be un-populated. >=20 > To keep the complexity low with the BMC SPI, use the 32MB layout > regardless of the used SPI or mainboard flavor. >=20 > Signed-off-by: Tan Siewert > --- > v2: > =C2=A0 - fix led node names [robh] > =C2=A0 - fix missing gfx memory region and other offenses [Tan] > --- > =C2=A0arch/arm/boot/dts/aspeed/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 1 + > =C2=A0.../dts/aspeed/aspeed-bmc-asrock-x470d4u.dts=C2=A0 | 350 ++++++++++= ++++++++ > =C2=A02 files changed, 351 insertions(+) > =C2=A0create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d= 4u.dts >=20 > diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed= /Makefile > index 0f0b5b707654..c601af36915e 100644 > --- a/arch/arm/boot/dts/aspeed/Makefile > +++ b/arch/arm/boot/dts/aspeed/Makefile > @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ASPEED) +=3D \ > =C2=A0 aspeed-bmc-asrock-e3c256d4i.dtb \ > =C2=A0 aspeed-bmc-asrock-romed8hm3.dtb \ > =C2=A0 aspeed-bmc-asrock-spc621d8hm3.dtb \ > + aspeed-bmc-asrock-x470d4u.dtb \ > =C2=A0 aspeed-bmc-asrock-x570d4u.dtb \ > =C2=A0 aspeed-bmc-asus-x4tf.dtb \ > =C2=A0 aspeed-bmc-bytedance-g220a.dtb \ > diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts > new file mode 100644 > index 000000000000..e9804b0ace9f > --- /dev/null > +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts > @@ -0,0 +1,350 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/dts-v1/; > + > +#include "aspeed-g5.dtsi" > +#include > +#include > +#include > + > +/ { > + model =3D "Asrock Rack X470D4U-series BMC"; > + compatible =3D "asrock,x470d4u-bmc", "aspeed,ast2500"; > + > + aliases { > + serial4 =3D &uart5; > + }; > + > + chosen { > + stdout-path =3D &uart5; > + }; >=20 >=20 *snip* > nvmem-cell-names =3D "mac-address"; > +}; > + > +&mac1 { > + status =3D "okay"; > + pinctrl-names =3D "default"; > + pinctrl-0 =3D <&pinctrl_rmii2_default &pinctrl_mdio2_default>; If you're using NCSI you don't need the MDIO pins here, right? > + use-ncsi; > + > + nvmem-cells =3D <ð1_macaddress>; > + nvmem-cell-names =3D "mac-address"; > +}; > + Andrew