* [PATCH v2 1/4] ARM: dts: aspeed: Add sensors devices for Facebook
From: Vijay Khemka @ 2018-12-17 20:04 UTC (permalink / raw)
To: linux-aspeed
Added ADC and other sensor devices in Facebook Tiogapass device tree.
Signed-off-by: Vijay Khemka <vijaykhemka@fb.com>
---
.../dts/aspeed-bmc-facebook-tiogapass.dts | 23 +++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
index f8e7b71af7e6..64039dddd853 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
@@ -21,6 +21,17 @@
memory at 80000000 {
reg = <0x80000000 0x20000000>;
};
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>;
+ };
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 7>;
+ };
};
&fmc {
@@ -64,6 +75,10 @@
use-ncsi;
};
+&adc {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
//Airmax Conn B, CPU0 PIROM, CPU1 PIROM
@@ -122,6 +137,10 @@
&i2c8 {
status = "okay";
+ tmp421 at 1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
//Mezz Sensor SMBus
};
@@ -140,7 +159,7 @@
};
fan at 1 {
- reg = <0x00>;
- aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
};
--
2.17.1
^ permalink raw reply related
* [Potential Spoof] Re: [PATCH 1/4] ARM: dts: aspeed: Add sensors devices for Facebook
From: James Feist @ 2018-12-17 19:50 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <E3F1FFD7-1C5A-43DE-BCA6-5B50EEEF577F@fb.com>
On 12/17/18 11:39 AM, Vijay Khemka wrote:
>
>
> ?On 12/14/18, 12:42 PM, "Linux-aspeed on behalf of Vijay Khemka" <linux-aspeed-bounces+vijaykhemka=fb.com at lists.ozlabs.org on behalf of vijaykhemka@fb.com> wrote:
>
>
>
> On 12/14/18, 11:22 AM, "openbmc on behalf of Jae Hyun Yoo" <openbmc-bounces+vijaykhemka=fb.com at lists.ozlabs.org on behalf of jae.hyun.yoo@linux.intel.com> wrote:
>
> Hi Vijay,
>
> On 12/14/2018 10:11 AM, Vijay Khemka wrote:
> > On 12/13/18, 2:56 PM, "Joel Stanley" <joel@jms.id.au> wrote:
>
> <snip>
>
> > > + oemname0 = "MB_P3V3";
> > > + oemname1 = "MB_P5V";
> > > + oemname2 = "MB_P12V";
> > > + oemname3 = "MB_P1V05";
> > > + oemname4 = "MB_PVNN_PCH_STBY";
> > > + oemname5 = "MB_P3V3_STBY";
> > > + oemname6 = "MB_P5V_STBY";
> >
> > "oemname" isn't part of the upstream bindings. Is this something you
> > have patches for?
> > This is a workaround field used by dbus-sensors application to avoid overlay for dynamic detection of devices based on json file definition.
> >
> > Can you please also review other 3 patches in this series.
> >
> >
>
> These oemname settings should not be added into here. You can add these
> information into configuration of entity manager which uses overlay
> templates for dbus-sensors. Also, as Joel said, "oemname" isn't part of
> the upstream bindings.
>
> Overlay templates from entity manager is not working for fan and adc sensors that's why it is a workaround suggested by James Feist (Author of dbus-sensors).
>
> @james.feist at linux.intel.com,
> Please comment on above patch, please advise if I need to fix this.
Yes, this is a workaround. It should not be added to your device tree.
This has already been fixed for the fans, someone just needs to spend a
little bit of time to fix the ADCs then it won't be needed.
Thanks,
James
>
> Cheers,
> Jae
>
>
>
>
^ permalink raw reply
* [Potential Spoof] Re: [PATCH 1/4] ARM: dts: aspeed: Add sensors devices for Facebook
From: Vijay Khemka @ 2018-12-17 19:39 UTC (permalink / raw)
To: linux-aspeed
?On 12/14/18, 12:42 PM, "Linux-aspeed on behalf of Vijay Khemka" <linux-aspeed-bounces+vijaykhemka=fb.com at lists.ozlabs.org on behalf of vijaykhemka@fb.com> wrote:
On 12/14/18, 11:22 AM, "openbmc on behalf of Jae Hyun Yoo" <openbmc-bounces+vijaykhemka=fb.com at lists.ozlabs.org on behalf of jae.hyun.yoo@linux.intel.com> wrote:
Hi Vijay,
On 12/14/2018 10:11 AM, Vijay Khemka wrote:
> On 12/13/18, 2:56 PM, "Joel Stanley" <joel@jms.id.au> wrote:
<snip>
> > + oemname0 = "MB_P3V3";
> > + oemname1 = "MB_P5V";
> > + oemname2 = "MB_P12V";
> > + oemname3 = "MB_P1V05";
> > + oemname4 = "MB_PVNN_PCH_STBY";
> > + oemname5 = "MB_P3V3_STBY";
> > + oemname6 = "MB_P5V_STBY";
>
> "oemname" isn't part of the upstream bindings. Is this something you
> have patches for?
> This is a workaround field used by dbus-sensors application to avoid overlay for dynamic detection of devices based on json file definition.
>
> Can you please also review other 3 patches in this series.
>
>
These oemname settings should not be added into here. You can add these
information into configuration of entity manager which uses overlay
templates for dbus-sensors. Also, as Joel said, "oemname" isn't part of
the upstream bindings.
Overlay templates from entity manager is not working for fan and adc sensors that's why it is a workaround suggested by James Feist (Author of dbus-sensors).
@james.feist at linux.intel.com,
Please comment on above patch, please advise if I need to fix this.
Cheers,
Jae
^ permalink raw reply
* [PATCH -next] media: platform: Fix missing spin_lock_init()
From: Wei Yongjun @ 2018-12-17 12:14 UTC (permalink / raw)
To: linux-aspeed
The driver allocates the spinlock but not initialize it.
Use spin_lock_init() on it to initialize it correctly.
This is detected by Coccinelle semantic patch.
Fixes: d2b4387f3bdf ("media: platform: Add Aspeed Video Engine driver")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
---
drivers/media/platform/aspeed-video.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c
index dfec813..692e08e 100644
--- a/drivers/media/platform/aspeed-video.c
+++ b/drivers/media/platform/aspeed-video.c
@@ -1661,6 +1661,7 @@ static int aspeed_video_probe(struct platform_device *pdev)
video->frame_rate = 30;
video->dev = &pdev->dev;
+ spin_lock_init(&video->lock);
mutex_init(&video->video_lock);
init_waitqueue_head(&video->wait);
INIT_DELAYED_WORK(&video->res_work, aspeed_video_resolution_work);
^ permalink raw reply related
* [PATCH 2/2] dt-bindings: edac: Aspeed AST2500
From: Stefan Schaeckeler @ 2018-12-17 6:01 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1545026517-64069-1-git-send-email-schaecsn@gmx.net>
From: Stefan M Schaeckeler <sschaeck@cisco.com>
Add support for the Aspeed AST2500 SoC EDAC driver.
Signed-off-by: Stefan M Schaeckeler <sschaeck@cisco.com>
---
.../bindings/edac/aspeed-sdram-edac.txt | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
new file mode 100644
index 000000000000..57ba852883c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
@@ -0,0 +1,34 @@
+Aspeed AST2500 SoC EDAC device driver
+
+The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
+correction check).
+
+The memory controller supports SECDED (single bit error correction, double bit
+error detection) and single bit error auto scrubbing by reserving 8 bits for
+every 64 bit word (effectively reducing available memory to 8/9).
+
+First, ECC must be configured in u-boot. Then, this driver will expose error
+counters via the edac kernel framework.
+
+A note on memory organization in ECC mode: every 512 bytes are followed by 64
+bytes of ECC codes. The address remapping is done in hardware and is fully
+transparent to firmware and software. Because of this, ECC mode must be
+configured in u-boot as part of the memory initialization as one can not switch
+from one mode to another when executing in memory.
+
+
+
+Required properties:
+- compatible: should be "aspeed,ast2500-sdram-edac"
+- reg: sdram controller register set should be <0x1e6e0000 0x174>
+- interrupts: should be AVIC interrupt #0
+
+
+Example:
+
+ edac: sdram at 1e6e0000 {
+ compatible = "aspeed,ast2500-sdram-edac";
+ reg = <0x1e6e0000 0x174>;
+ interrupts = <0>;
+ status = "okay";
+ };
--
2.19.1
^ permalink raw reply related
* [PATCH 1/2] EDAC: Add Aspeed AST2500 EDAC driver
From: Stefan Schaeckeler @ 2018-12-17 6:01 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1545026517-64069-1-git-send-email-schaecsn@gmx.net>
From: Stefan M Schaeckeler <sschaeck@cisco.com>
Add support for the Aspeed AST2500 SoC EDAC driver.
Signed-off-by: Stefan M Schaeckeler <sschaeck@cisco.com>
---
MAINTAINERS | 6 +
arch/arm/boot/dts/aspeed-g5.dtsi | 7 +
drivers/edac/Kconfig | 7 +
drivers/edac/Makefile | 1 +
drivers/edac/aspeed_edac.c | 457 +++++++++++++++++++++++++++++++
5 files changed, 478 insertions(+)
create mode 100644 drivers/edac/aspeed_edac.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 3318f30903b2..1feb92b14029 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5315,6 +5315,12 @@ L: linux-edac at vger.kernel.org
S: Maintained
F: drivers/edac/amd64_edac*
+EDAC-AST2500
+M: Stefan Schaeckeler <sschaeck@cisco.com>
+S: Supported
+F: drivers/edac/aspeed_edac.c
+F: Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
+
EDAC-CALXEDA
M: Robert Richter <rric@kernel.org>
L: linux-edac at vger.kernel.org
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8..b4e479ab5a2d 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -47,6 +47,13 @@
reg = <0x80000000 0>;
};
+ edac: sdram at 1e6e0000 {
+ compatible = "aspeed,ast2500-sdram-edac";
+ reg = <0x1e6e0000 0x174>;
+ interrupts = <0>;
+ status = "disabled";
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 41c9ccdd20d6..67834430b0a1 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -475,4 +475,11 @@ config EDAC_QCOM
For debugging issues having to do with stability and overall system
health, you should probably say 'Y' here.
+config EDAC_ASPEED
+ tristate "Aspeed AST 2500 SoC"
+ depends on MACH_ASPEED_G5
+ help
+ Support for error detection and correction on the
+ Aspeed AST 2500 SoC.
+
endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 716096d08ea0..e1f23d4ff860 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -78,3 +78,4 @@ obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o
obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o
obj-$(CONFIG_EDAC_TI) += ti_edac.o
obj-$(CONFIG_EDAC_QCOM) += qcom_edac.o
+obj-$(CONFIG_EDAC_ASPEED) += aspeed_edac.o
diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
new file mode 100644
index 000000000000..d6ed119909eb
--- /dev/null
+++ b/drivers/edac/aspeed_edac.c
@@ -0,0 +1,457 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Cisco Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/edac.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/stop_machine.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <asm/page.h>
+#include "edac_module.h"
+
+
+#define DRV_NAME "aspeed-edac"
+
+
+/* registers */
+#define ASPEED_MCR_PROT 0x00 /* protection key register */
+#define ASPEED_MCR_CONF 0x04 /* configuration register */
+#define ASPEED_MCR_INTR_CTRL 0x50 /* interrupt control/status register */
+#define ASPEED_MCR_ADDR_UNREC 0x58 /* address of first un-recoverable error */
+#define ASPEED_MCR_ADDR_REC 0x5c /* address of last recoverable error */
+#define ASPEED_MCR_LAST ASPEED_MCR_ADDR_REC
+
+
+/* bits and masks */
+#define ASPEED_MCR_PROT_PASSWD 0xfc600309
+#define ASPEED_MCR_CONF_DRAM_TYPE BIT(4)
+#define ASPEED_MCR_CONF_ECC BIT(7)
+#define ASPEED_MCR_INTR_CTRL_CLEAR BIT(31)
+#define ASPEED_MCR_INTR_CTRL_CNT_REC GENMASK(23, 16)
+#define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)
+#define ASPEED_MCR_INTR_CTRL_ENABLE (BIT(0) | BIT(1))
+
+
+
+static int aspeed_edac_regmap_reg_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ void __iomem *regs = (void __iomem *)context;
+
+ /* enable write to MCR register set */
+ writel(ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT);
+
+ writel(val, regs + reg);
+
+ /* disable write to MCR register set */
+ writel(~ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT);
+
+ return 0;
+}
+
+
+static int aspeed_edac_regmap_reg_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+ void __iomem *regs = (void __iomem *)context;
+
+ *val = readl(regs + reg);
+
+ return 0;
+}
+
+static bool aspeed_edac_regmap_is_volatile(struct device *dev,
+ unsigned int reg)
+{
+ switch (reg) {
+ case ASPEED_MCR_PROT:
+ case ASPEED_MCR_INTR_CTRL:
+ case ASPEED_MCR_ADDR_UNREC:
+ case ASPEED_MCR_ADDR_REC:
+ return true;
+ default:
+ return false;
+ }
+}
+
+
+static const struct regmap_config aspeed_edac_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = ASPEED_MCR_LAST,
+ .reg_write = aspeed_edac_regmap_reg_write,
+ .reg_read = aspeed_edac_regmap_reg_read,
+ .volatile_reg = aspeed_edac_regmap_is_volatile,
+ .fast_io = true,
+};
+
+
+static struct regmap *aspeed_edac_regmap;
+
+
+static void aspeed_edac_count_rec(struct mem_ctl_info *mci,
+ u8 rec_cnt,
+ u32 rec_addr)
+{
+ struct csrow_info *csrow = mci->csrows[0];
+ u32 page, offset, syndrome;
+
+ if (rec_cnt > 0) {
+ /* report first few errors (if there are) */
+ /* note: no addresses are recorded */
+ if (rec_cnt > 1) {
+ page = 0; /* not available */
+ offset = 0; /* not available */
+ syndrome = 0; /* not available */
+ edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
+ rec_cnt-1, page, offset,
+ syndrome, 0, 0, -1,
+ "address(es) not available", "");
+ }
+
+ /* report last error */
+ /* note: rec_addr is the last recoverable error addr */
+ page = rec_addr >> PAGE_SHIFT;
+ offset = rec_addr & ~PAGE_MASK;
+ syndrome = 0; /* not available */
+ edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
+ csrow->first_page + page, offset, syndrome,
+ 0, 0, -1, "", "");
+ }
+}
+
+
+static void aspeed_edac_count_un_rec(struct mem_ctl_info *mci,
+ u8 un_rec_cnt,
+ u32 un_rec_addr)
+{
+ struct csrow_info *csrow = mci->csrows[0];
+ u32 page, offset, syndrome;
+
+ if (un_rec_cnt > 0) {
+ /* report 1. error */
+ /* note: un_rec_addr is the first unrecoverable error addr */
+ page = un_rec_addr >> PAGE_SHIFT;
+ offset = un_rec_addr & ~PAGE_MASK;
+ syndrome = 0; /* not available */
+ edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
+ csrow->first_page + page, offset, syndrome,
+ 0, 0, -1, "", "");
+
+ /* report further errors (if there are) */
+ /* note: no addresses are recorded */
+ if (un_rec_cnt > 1) {
+ page = 0; /* not available */
+ offset = 0; /* not available */
+ syndrome = 0; /* not available */
+ edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
+ un_rec_cnt-1, page, offset,
+ syndrome, 0, 0, -1,
+ "address(es) not available", "");
+ }
+ }
+}
+
+
+static void aspeed_edac_enable_interrupts(void)
+{
+
+ regmap_update_bits(aspeed_edac_regmap, ASPEED_MCR_INTR_CTRL,
+ ASPEED_MCR_INTR_CTRL_ENABLE,
+ ASPEED_MCR_INTR_CTRL_ENABLE);
+}
+
+
+static void aspeed_edac_disable_interrupts(void)
+{
+ regmap_update_bits(aspeed_edac_regmap, ASPEED_MCR_INTR_CTRL,
+ ASPEED_MCR_INTR_CTRL_ENABLE, 0);
+}
+
+
+static void aspeed_edac_clear_interrupts(void)
+{
+ regmap_update_bits(aspeed_edac_regmap, ASPEED_MCR_INTR_CTRL,
+ ASPEED_MCR_INTR_CTRL_CLEAR,
+ ASPEED_MCR_INTR_CTRL_CLEAR);
+
+ regmap_update_bits(aspeed_edac_regmap, ASPEED_MCR_INTR_CTRL,
+ ASPEED_MCR_INTR_CTRL_CLEAR, 0);
+}
+
+
+static irqreturn_t aspeed_edac_isr(int irq, void *arg)
+{
+ u8 rec_cnt, un_rec_cnt;
+ u32 rec_addr, un_rec_addr;
+ struct mem_ctl_info *mci = arg;
+ u32 reg50, reg5c, reg58;
+
+ regmap_read(aspeed_edac_regmap, ASPEED_MCR_INTR_CTRL, ®50);
+ dev_dbg(mci->pdev, "received edac interrupt w/ mmc register 50: 0x%x\n",
+ reg50);
+
+ /* collect data about recoverable and unrecoverable errors */
+ rec_cnt = (reg50 & ASPEED_MCR_INTR_CTRL_CNT_REC) >> 16;
+ un_rec_cnt = (reg50 & ASPEED_MCR_INTR_CTRL_CNT_UNREC) >> 12;
+
+ dev_dbg(mci->pdev, "%d recoverable interrupts and %d unrecoverable interrupts\n",
+ rec_cnt, un_rec_cnt);
+
+ regmap_read(aspeed_edac_regmap, ASPEED_MCR_ADDR_UNREC, ®58);
+ un_rec_addr = reg58 >> 4;
+
+ regmap_read(aspeed_edac_regmap, ASPEED_MCR_ADDR_REC, ®5c);
+ rec_addr = reg5c >> 4;
+
+ /* clear interrupt flags and error counters: */
+ aspeed_edac_clear_interrupts();
+
+ /* process recoverable and unrecoverable errors */
+ if (rec_cnt > 0)
+ aspeed_edac_count_rec(mci, rec_cnt, rec_addr);
+
+ if (un_rec_cnt > 0)
+ aspeed_edac_count_un_rec(mci, un_rec_cnt, un_rec_addr);
+
+ if ((rec_cnt == 0) && (un_rec_cnt == 0))
+ dev_dbg(mci->pdev, "received edac interrupt, but did not find any ecc counters\n");
+
+ regmap_read(aspeed_edac_regmap, ASPEED_MCR_INTR_CTRL, ®50);
+ dev_dbg(mci->pdev, "edac interrupt handled. mmc reg 50 is now: 0x%x\n",
+ reg50);
+
+ return IRQ_HANDLED;
+}
+
+
+static int aspeed_edac_config_irq(void *ctx,
+ struct platform_device *pdev)
+{
+ int irq;
+ int rc;
+
+ /* register interrupt handler */
+
+ irq = platform_get_irq(pdev, 0);
+ dev_dbg(&pdev->dev, "got irq %d\n", irq);
+ if (!irq)
+ return -ENODEV;
+
+ rc = devm_request_irq(&pdev->dev, irq, aspeed_edac_isr,
+ IRQF_TRIGGER_HIGH, DRV_NAME, ctx);
+ if (rc) {
+ dev_err(&pdev->dev, "unable to request irq %d\n", irq);
+ return rc;
+ }
+
+ /* enable interrupts */
+ aspeed_edac_enable_interrupts();
+
+ return 0;
+}
+
+
+static int aspeed_edac_init_csrows(struct mem_ctl_info *mci)
+{
+ struct csrow_info *csrow = mci->csrows[0];
+ struct dimm_info *dimm;
+ struct device_node *np;
+ u32 nr_pages, dram_type;
+ struct resource r;
+ u32 reg04;
+ int rc;
+
+ /* retrieve info about physical memory from device tree */
+ np = of_find_node_by_path("/memory");
+
+ if (!np) {
+ dev_err(mci->pdev, "dt: missing /memory node\n");
+ return -ENODEV;
+ };
+
+ rc = of_address_to_resource(np, 0, &r);
+
+ of_node_put(np);
+
+ if (rc) {
+ dev_err(mci->pdev, "dt: failed requesting resource for /memory node\n");
+ return rc;
+ };
+
+ dev_dbg(mci->pdev, "dt: /memory node resources: first page r.start=0x%x, resource_size=0x%x, PAGE_SHIFT macro=0x%x\n",
+ r.start, resource_size(&r), PAGE_SHIFT);
+
+ csrow->first_page = r.start >> PAGE_SHIFT;
+ nr_pages = resource_size(&r) >> PAGE_SHIFT;
+ csrow->last_page = csrow->first_page + nr_pages - 1;
+
+ regmap_read(aspeed_edac_regmap, ASPEED_MCR_CONF, ®04);
+ dram_type = (reg04 & ASPEED_MCR_CONF_DRAM_TYPE) ? MEM_DDR4 : MEM_DDR3;
+
+ dimm = csrow->channels[0]->dimm;
+ dimm->mtype = dram_type;
+ dimm->edac_mode = EDAC_SECDED;
+ dimm->nr_pages = nr_pages / csrow->nr_channels;
+
+ dev_dbg(mci->pdev, "initialized dimm with first_page=0x%lx and nr_pages=0x%x\n",
+ csrow->first_page, nr_pages);
+
+ return 0;
+}
+
+
+static int aspeed_edac_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ void __iomem *regs;
+ struct resource *res;
+ struct mem_ctl_info *mci;
+ struct edac_mc_layer layers[2];
+ struct device_node *np;
+ u32 reg04;
+ int rc;
+
+ /* setup regmap */
+ np = dev->of_node;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENOENT;
+
+ regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ aspeed_edac_regmap = devm_regmap_init(dev, NULL, (__force void *)regs,
+ &aspeed_edac_regmap_config);
+ if (IS_ERR(aspeed_edac_regmap))
+ return PTR_ERR(aspeed_edac_regmap);
+
+ /* bail out if ECC mode is not configured */
+ regmap_read(aspeed_edac_regmap, ASPEED_MCR_CONF, ®04);
+ if (!(reg04 & ASPEED_MCR_CONF_ECC)) {
+ dev_err(&pdev->dev, "ECC mode is not configured in u-boot\n");
+ return -EPERM;
+ }
+
+ edac_op_state = EDAC_OPSTATE_INT;
+
+ /* allocate & init EDAC MC data structure */
+ layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
+ layers[0].size = 1;
+ layers[0].is_virt_csrow = true;
+ layers[1].type = EDAC_MC_LAYER_CHANNEL;
+ layers[1].size = 1;
+ layers[1].is_virt_csrow = false;
+
+ mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
+ if (mci == NULL)
+ return -ENOMEM;
+
+ mci->pdev = &pdev->dev;
+ mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR4;
+ mci->edac_ctl_cap = EDAC_FLAG_SECDED;
+ mci->edac_cap = EDAC_FLAG_SECDED;
+ mci->scrub_cap = SCRUB_FLAG_HW_SRC;
+ mci->scrub_mode = SCRUB_HW_SRC;
+ mci->mod_name = DRV_NAME;
+ mci->ctl_name = "MIC";
+ mci->dev_name = dev_name(&pdev->dev);
+
+ rc = aspeed_edac_init_csrows(mci);
+ if (rc) {
+ dev_err(&pdev->dev, "failed to init csrows\n");
+ goto probe_exit02;
+ }
+
+ platform_set_drvdata(pdev, mci);
+
+ /* register with edac core */
+ rc = edac_mc_add_mc(mci);
+ if (rc) {
+ dev_err(&pdev->dev, "failed to register with EDAC core\n");
+ goto probe_exit02;
+ }
+
+ /* register interrupt handler and enable interrupts */
+ rc = aspeed_edac_config_irq(mci, pdev);
+ if (rc) {
+ dev_err(&pdev->dev, "failed setting up irq\n");
+ goto probe_exit01;
+ }
+
+ return 0;
+
+probe_exit01:
+ edac_mc_del_mc(&pdev->dev);
+probe_exit02:
+ edac_mc_free(mci);
+ return rc;
+}
+
+
+static int aspeed_edac_remove(struct platform_device *pdev)
+{
+ struct mem_ctl_info *mci;
+
+ /* disable interrupts */
+ aspeed_edac_disable_interrupts();
+
+ /* free resources */
+ mci = edac_mc_del_mc(&pdev->dev);
+ if (mci)
+ edac_mc_free(mci);
+
+ return 0;
+}
+
+
+static const struct of_device_id aspeed_edac_of_match[] = {
+ { .compatible = "aspeed,ast2500-sdram-edac" },
+ {},
+};
+
+
+static struct platform_driver aspeed_edac_driver = {
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = aspeed_edac_of_match
+ },
+ .probe = aspeed_edac_probe,
+ .remove = aspeed_edac_remove
+};
+
+
+static int __init aspeed_edac_init(void)
+{
+ return platform_driver_register(&aspeed_edac_driver);
+}
+
+
+static void __exit aspeed_edac_exit(void)
+{
+ platform_driver_unregister(&aspeed_edac_driver);
+}
+
+
+module_init(aspeed_edac_init);
+module_exit(aspeed_edac_exit);
+
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Stefan Schaeckeler <sschaeck@cisco.com>");
+MODULE_DESCRIPTION("Aspeed AST2500 EDAC driver");
+MODULE_VERSION("1.0");
--
2.19.1
^ permalink raw reply related
* [PATCH 0/2] Add support for the Aspeed AST2500 SoC EDAC driver.
From: Stefan Schaeckeler @ 2018-12-17 6:01 UTC (permalink / raw)
To: linux-aspeed
From: Stefan M Schaeckeler <schaecsn@gmx.net>
Add support for the Aspeed AST2500 SoC EDAC driver.
Note, I only have access to AST2500 hardware and documentation. The AST2500
documentation explicitly states that the sdram controller is not backward
compatible with AST2400 and hence this driver is not supporting it.
Best, Stefan
Stefan M Schaeckeler (2):
EDAC: Add Aspeed AST2500 EDAC driver
dt-bindings: edac: Aspeed AST2500
.../bindings/edac/aspeed-sdram-edac.txt | 34 ++
MAINTAINERS | 6 +
arch/arm/boot/dts/aspeed-g5.dtsi | 7 +
drivers/edac/Kconfig | 7 +
drivers/edac/Makefile | 1 +
drivers/edac/aspeed_edac.c | 457 ++++++++++++++++++
6 files changed, 512 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
create mode 100644 drivers/edac/aspeed_edac.c
--
2.19.1
^ permalink raw reply
* [PATCH] ARM: dts: aspeed: Add KCS support for LPC BMC
From: kbuild test robot @ 2018-12-16 8:13 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20181210200753.3018124-2-vijaykhemka@fb.com>
Hi Vijay,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on joel-aspeed/for-next]
[also build test ERROR on v4.20-rc6 next-20181214]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Vijay-Khemka/ARM-dts-aspeed-Add-KCS-support-for-LPC-BMC/20181211-074230
base: https://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git for-next
config: arm-multi_v5_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.2.0 make.cross ARCH=arm
All errors (new ones prefixed by >>):
>> Error: arch/arm/boot/dts/aspeed-g5.dtsi:333.45-46 syntax error
FATAL ERROR: Unable to parse input tree
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH] pinctrl: aspeed: Wrap -Woverride-init with cc-option
From: Linus Walleij @ 2018-12-16 0:23 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20181211000506.7559-1-natechancellor@gmail.com>
On Tue, Dec 11, 2018 at 1:05 AM Nathan Chancellor
<natechancellor@gmail.com> wrote:
> Clang does not support this option:
>
> warning: unknown warning option '-Woverride-init'; did you mean
> '-Woverride-module'? [-Wunknown-warning-option]
> 1 warning generated.
>
> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Patch applied with the ACKs!
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 5/7] [stable-4.19] i2c: aspeed: fix build warning
From: Brendan Higgins @ 2018-12-14 23:30 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20181214221023.3878670-6-arnd@arndb.de>
On Fri, Dec 14, 2018 at 2:12 PM Arnd Bergmann <arnd@arndb.de> wrote:
>
> Upstream commit 3e9efc3299dd ("i2c: aspeed: Handle master/slave combined irq events
> properly") reworked the interrupt handling and fixed a warning in the process:
>
> drivers/i2c/busses/i2c-aspeed.c: In function 'aspeed_i2c_bus_irq':
> drivers/i2c/busses/i2c-aspeed.c:567:1: error: label 'out' defined but not used [-Werror=unused-label]
>
> The warning is still present in v4.19.8 and can be fixed either by applying
> that original patch, or by adding a simple #ifdef.
>
> Here, I choose the second simpler option as the original patch seems too
> invasive for a stable backport.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Thanks!
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
^ permalink raw reply
* [PATCH 5/7] [stable-4.19] i2c: aspeed: fix build warning
From: Arnd Bergmann @ 2018-12-14 22:10 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20181214221023.3878670-1-arnd@arndb.de>
Upstream commit 3e9efc3299dd ("i2c: aspeed: Handle master/slave combined irq events
properly") reworked the interrupt handling and fixed a warning in the process:
drivers/i2c/busses/i2c-aspeed.c: In function 'aspeed_i2c_bus_irq':
drivers/i2c/busses/i2c-aspeed.c:567:1: error: label 'out' defined but not used [-Werror=unused-label]
The warning is still present in v4.19.8 and can be fixed either by applying
that original patch, or by adding a simple #ifdef.
Here, I choose the second simpler option as the original patch seems too
invasive for a stable backport.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/i2c/busses/i2c-aspeed.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c
index a4f956c6d567..a19fbff16861 100644
--- a/drivers/i2c/busses/i2c-aspeed.c
+++ b/drivers/i2c/busses/i2c-aspeed.c
@@ -555,7 +555,7 @@ static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
spin_lock(&bus->lock);
#if IS_ENABLED(CONFIG_I2C_SLAVE)
- if (aspeed_i2c_slave_irq(bus)) {
+ if (IS_ENABLED(CONFIG_I2C_SLAVE) && aspeed_i2c_slave_irq(bus)) {
dev_dbg(bus->dev, "irq handled by slave.\n");
ret = true;
goto out;
@@ -564,7 +564,9 @@ static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
ret = aspeed_i2c_master_irq(bus);
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
out:
+#endif
spin_unlock(&bus->lock);
return ret ? IRQ_HANDLED : IRQ_NONE;
}
--
2.20.0
^ permalink raw reply related
* [PATCH 0/7] v4.19-stable randconfig fixes
From: Arnd Bergmann @ 2018-12-14 22:10 UTC (permalink / raw)
To: linux-aspeed
Hi Greg,
I did some randconfig testing on linux-4.19 arm/arm64/x86. So far I needed
27 patches, most of which are also still needed in mainline Linux. I
had submitted some before, and others were not submitted previously
for some reason. I'll try to get those fixed in mainline and then
make sure we get them into 4.19 as well.
This series for now contains four patches that did make it into mainline:
2e6ae11dd0d1 ("slimbus: ngd: mark PM functions as __maybe_unused")
33f49571d750 ("staging: olpc_dcon: add a missing dependency")
0eeec01488da ("scsi: raid_attrs: fix unused variable warning")
11d4afd4ff66 ("sched/pelt: Fix warning and clean up IRQ PELT config")
Feel free to either cherry-pick those from mainline or apply the
patch from this series, whichever works best for you.
The other three patches are for warnings in code that got removed in
mainline kernels:
3e9efc3299dd ("i2c: aspeed: Handle master/slave combined irq events properly")
972910948fb6 ("ARM: dts: qcom: Remove Arrow SD600 eval board")
effec874792f ("drm/msm/dpu: Remove dpu_dbg")
My feeling was that it's safer to just address the warning by fixing
the code correctly in each of these cases, but if you disagree,
applying the mainline change should work equally well, so decide
for yourself.
Arnd
Arnd Bergmann (5):
scsi: raid_attrs: fix unused variable warning
slimbus: ngd: mark PM functions as __maybe_unused
[stable-4.19] i2c: aspeed: fix build warning
[stable-4.19] ARM: dts: qcom-apq8064-arrow-sd-600eval fix
graph_endpoint warning
[stable-4.19] drm/msm: fix address space warning
Lubomir Rintel (1):
staging: olpc_dcon: add a missing dependency
Vincent Guittot (1):
sched/pelt: Fix warning and clean up IRQ PELT config
arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts | 5 +++++
drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c | 8 ++++----
drivers/i2c/busses/i2c-aspeed.c | 4 +++-
drivers/scsi/raid_class.c | 4 +---
drivers/slimbus/qcom-ngd-ctrl.c | 6 ++----
drivers/staging/olpc_dcon/Kconfig | 1 +
init/Kconfig | 5 +++++
kernel/sched/core.c | 7 +++----
kernel/sched/fair.c | 2 +-
kernel/sched/pelt.c | 2 +-
kernel/sched/pelt.h | 2 +-
kernel/sched/sched.h | 5 ++---
12 files changed, 29 insertions(+), 22 deletions(-)
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: Andy Gross <andy.gross@linaro.org>
Cc: bp at alien8.de
Cc: Daniel Drake <dsd@laptop.org>
Cc: David Brown <david.brown@linaro.org>
Cc: dou_liyang at 163.com
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "James E.J. Bottomley" <jejb@linux.vnet.ibm.com>
Cc: Jens Frederich <jfrederich@gmail.com>
Cc: Lubomir Rintel <lkundrak@v3.sk>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: "Martin K. Petersen" <martin.petersen@oracle.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Vincent Guittot <vincent.guittot@linaro.org>
Cc: linux-arm-msm at vger.kernel.org
Cc: devicetree at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: freedreno at lists.freedesktop.org
Cc: linux-i2c at vger.kernel.org
Cc: openbmc at lists.ozlabs.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-aspeed at lists.ozlabs.org
Cc: linux-scsi at vger.kernel.org
--
2.20.0
^ permalink raw reply
* [PATCH 1/4] ARM: dts: aspeed: Add sensors devices for Facebook
From: Vijay Khemka @ 2018-12-14 20:41 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <c1e35845-cb07-048f-bcf7-d7239a387027@linux.intel.com>
?On 12/14/18, 11:22 AM, "openbmc on behalf of Jae Hyun Yoo" <openbmc-bounces+vijaykhemka=fb.com at lists.ozlabs.org on behalf of jae.hyun.yoo@linux.intel.com> wrote:
Hi Vijay,
On 12/14/2018 10:11 AM, Vijay Khemka wrote:
> On 12/13/18, 2:56 PM, "Joel Stanley" <joel@jms.id.au> wrote:
<snip>
> > + oemname0 = "MB_P3V3";
> > + oemname1 = "MB_P5V";
> > + oemname2 = "MB_P12V";
> > + oemname3 = "MB_P1V05";
> > + oemname4 = "MB_PVNN_PCH_STBY";
> > + oemname5 = "MB_P3V3_STBY";
> > + oemname6 = "MB_P5V_STBY";
>
> "oemname" isn't part of the upstream bindings. Is this something you
> have patches for?
> This is a workaround field used by dbus-sensors application to avoid overlay for dynamic detection of devices based on json file definition.
>
> Can you please also review other 3 patches in this series.
>
>
These oemname settings should not be added into here. You can add these
information into configuration of entity manager which uses overlay
templates for dbus-sensors. Also, as Joel said, "oemname" isn't part of
the upstream bindings.
Overlay templates from entity manager is not working for fan and adc sensors that's why it is a workaround suggested by James Feist (Author of dbus-sensors).
Cheers,
Jae
^ permalink raw reply
* [PATCH 1/4] ARM: dts: aspeed: Add sensors devices for Facebook
From: Jae Hyun Yoo @ 2018-12-14 19:18 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <B6C3C92D-1F9E-4425-ABF5-718D1A6755EB@fb.com>
Hi Vijay,
On 12/14/2018 10:11 AM, Vijay Khemka wrote:
> On 12/13/18, 2:56 PM, "Joel Stanley" <joel@jms.id.au> wrote:
<snip>
> > + oemname0 = "MB_P3V3";
> > + oemname1 = "MB_P5V";
> > + oemname2 = "MB_P12V";
> > + oemname3 = "MB_P1V05";
> > + oemname4 = "MB_PVNN_PCH_STBY";
> > + oemname5 = "MB_P3V3_STBY";
> > + oemname6 = "MB_P5V_STBY";
>
> "oemname" isn't part of the upstream bindings. Is this something you
> have patches for?
> This is a workaround field used by dbus-sensors application to avoid overlay for dynamic detection of devices based on json file definition.
>
> Can you please also review other 3 patches in this series.
>
>
These oemname settings should not be added into here. You can add these
information into configuration of entity manager which uses overlay
templates for dbus-sensors. Also, as Joel said, "oemname" isn't part of
the upstream bindings.
Cheers,
Jae
^ permalink raw reply
* [PATCH 1/4] ARM: dts: aspeed: Add sensors devices for Facebook
From: Vijay Khemka @ 2018-12-14 18:11 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CACPK8XfAXDHqWcD=OKm4UhCh-+-7GBxL02Fi9_jgdmo2ZQZSjg@mail.gmail.com>
On 12/13/18, 2:56 PM, "Joel Stanley" <joel@jms.id.au> wrote:
On Fri, 14 Dec 2018 at 06:23, Vijay Khemka <vijaykhemka@fb.com> wrote:
>
> Added ADC and other sensor devices in Facebook Tiogapass device tree.
>
> Signed-off-by: Vijay Khemka <vijaykhemka@fb.com>
> ---
> .../dts/aspeed-bmc-facebook-tiogapass.dts | 33 +++++++++++++++++--
> 1 file changed, 31 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
> index f8e7b71af7e6..58bbe08d3ba7 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
> @@ -21,6 +21,25 @@
> memory at 80000000 {
> reg = <0x80000000 0x20000000>;
> };
> +
> + iio-hwmon {
> + compatible = "iio-hwmon";
> + oemname0 = "MB_P3V3";
> + oemname1 = "MB_P5V";
> + oemname2 = "MB_P12V";
> + oemname3 = "MB_P1V05";
> + oemname4 = "MB_PVNN_PCH_STBY";
> + oemname5 = "MB_P3V3_STBY";
> + oemname6 = "MB_P5V_STBY";
"oemname" isn't part of the upstream bindings. Is this something you
have patches for?
This is a workaround field used by dbus-sensors application to avoid overlay for dynamic detection of devices based on json file definition.
Can you please also review other 3 patches in this series.
^ permalink raw reply
* [PATCH 2/2] clk: aspeed: Setup video engine clocking
From: Eddie James @ 2018-12-14 15:47 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CACPK8XcY_c9NzNv-WyZcz+mZ5c2jixyCzEQAK-+t0QvQ_uJXwg@mail.gmail.com>
On 12/13/2018 07:02 PM, Joel Stanley wrote:
> Hi Eddie,
>
> On Wed, 12 Dec 2018 at 06:42, Eddie James <eajames@linux.ibm.com> wrote:
>> Add the video engine reset bit. Add eclk mux and clock divider table.
>>
>> Signed-off-by: Eddie James <eajames@linux.ibm.com>
>> Acked-by: Stephen Boyd <sboyd@kernel.org>
>> ---
>> drivers/clk/clk-aspeed.c | 41 +++++++++++++++++++++++++++++++++++++++--
>> 1 file changed, 39 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
>> index 5961367..f16ce7d 100644
>> --- a/drivers/clk/clk-aspeed.c
>> +++ b/drivers/clk/clk-aspeed.c
>> @@ -87,7 +87,7 @@ struct aspeed_clk_gate {
>> /* TODO: ask Aspeed about the actual parent data */
>> static const struct aspeed_gate_data aspeed_gates[] = {
>> /* clk rst name parent flags */
>> - [ASPEED_CLK_GATE_ECLK] = { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
>> + [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
>
>> [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
>> [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
>> [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
>> @@ -113,6 +113,24 @@ struct aspeed_clk_gate {
>> [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
>> };
>>
>> +static const char * const eclk_parent_names[] = {
>> + "mpll",
> Is the mpll really an input to the eclk?
Yep, it's the default.
>
>> + "hpll",
>> + "dpll",
> We don't have a dpll in the driver that I can see.
True... I supposed I would just add the parent here now in case the dpll
clock is ever added.
>
>> +};
>> +
>> +static const struct clk_div_table ast2500_eclk_div_table[] = {
> Is the clocking setup different on the ast2400?
Yes, the dividers are the default ast2400 ones.
>
>> + { 0x0, 2 },
>> + { 0x1, 2 },
>> + { 0x2, 3 },
>> + { 0x3, 4 },
>> + { 0x4, 5 },
>> + { 0x5, 6 },
>> + { 0x6, 7 },
>> + { 0x7, 8 },
>> + { 0 }
>> +};
>> @@ -317,6 +338,7 @@ struct aspeed_reset {
>> [ASPEED_RESET_PECI] = 10,
>> [ASPEED_RESET_I2C] = 2,
>> [ASPEED_RESET_AHB] = 1,
>> + [ASPEED_RESET_VIDEO] = 6,
> You've added the reset line to the ASPEED_CLK_GATE_ECLK clock so you
> do not need to separately expose the reset controller. Instead
> enabling the clock will deassert the rest line for you.
>
> This means you should drop the change from the header too, and it
> affects the bindings document for the video engine.
I want that reset available separately for use in the video engine
actually. I could do without it, but it's somewhat useful.
Thanks,
Eddie
>
>> /*
>> * SCUD4 resets start at an offset to separate them from
>> @@ -522,6 +544,22 @@ static int aspeed_clk_probe(struct platform_device *pdev)
>> return PTR_ERR(hw);
>> aspeed_clk_data->hws[ASPEED_CLK_24M] = hw;
>>
>> + hw = clk_hw_register_mux(dev, "eclk-mux", eclk_parent_names,
>> + ARRAY_SIZE(eclk_parent_names), 0,
>> + scu_base + ASPEED_CLK_SELECTION, 2, 0x3, 0,
>> + &aspeed_clk_lock);
>> + if (IS_ERR(hw))
>> + return PTR_ERR(hw);
>> + aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw;
>> +
>> + hw = clk_hw_register_divider_table(dev, "eclk", "eclk-mux", 0,
>> + scu_base + ASPEED_CLK_SELECTION, 28,
>> + 3, 0, soc_data->eclk_div_table,
>> + &aspeed_clk_lock);
>> + if (IS_ERR(hw))
>> + return PTR_ERR(hw);
>> + aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw;
>> +
>> /*
>> * TODO: There are a number of clocks that not included in this driver
>> * as more information is required:
>> @@ -531,7 +569,6 @@ static int aspeed_clk_probe(struct platform_device *pdev)
>> * RGMII
>> * RMII
>> * UART[1..5] clock source mux
>> - * Video Engine (ECLK) mux and clock divider
>> */
>>
>> for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) {
>> --
>> 1.8.3.1
>>
^ permalink raw reply
* [PATCH v8 2/2] media: platform: Add Aspeed Video Engine driver
From: Eddie James @ 2018-12-14 15:41 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CACPK8XdQbq-9MbP7uMemyp0=Q+t1qnWNREdZRiyEcrART9vRig@mail.gmail.com>
On 12/13/2018 07:09 PM, Joel Stanley wrote:
> On Wed, 12 Dec 2018 at 04:09, Eddie James <eajames@linux.ibm.com> wrote:
>> The Video Engine (VE) embedded in the Aspeed AST2400 and AST2500 SOCs
>> can capture and compress video data from digital or analog sources. With
>> the Aspeed chip acting a service processor, the Video Engine can capture
>> the host processor graphics output.
>> +ASPEED VIDEO ENGINE DRIVER
>> +M: Eddie James <eajames@linux.ibm.com>
>> +L: linux-media at vger.kernel.org
>> +L: openbmc at lists.ozlabs.org (moderated for non-subscribers)
> We tend to use the linux-aspeed list for upstream kernel discussions.
> Up to you if you want to use the openbmc list though.
>
>> source "drivers/media/platform/omap/Kconfig"
>>
>> +config VIDEO_ASPEED
>> + tristate "Aspeed AST2400 and AST2500 Video Engine driver"
>> + depends on VIDEO_V4L2
>> + select VIDEOBUF2_DMA_CONTIG
>> + help
>> + Support for the Aspeed Video Engine (VE) embedded in the Aspeed
>> + AST2400 and AST2500 SOCs. The VE can capture and compress video data
>> + from digital or analog sources.
> This might need updating in response to my questions below about
> ast2400 testing.
>
>> +++ b/drivers/media/platform/aspeed-video.c
>> @@ -0,0 +1,1729 @@
>> +// SPDX-License-Identifier: GPL-2.0+
> You need to put this there as well:
>
> // Copyright 2018 IBM Corp
>
>
>> +static int aspeed_video_init(struct aspeed_video *video)
>> +{
>> + int irq;
>> + int rc;
>> + struct device *dev = video->dev;
>> +
>> + irq = irq_of_parse_and_map(dev->of_node, 0);
>> + if (!irq) {
>> + dev_err(dev, "Unable to find IRQ\n");
>> + return -ENODEV;
>> + }
>> +
>> + rc = devm_request_irq(dev, irq, aspeed_video_irq, IRQF_SHARED,
> The datasheet indicates this IRQ is for the video engline only, so I
> don't think you want IRQF_SHARED.
>
>> + DEVICE_NAME, video);
>> + if (rc < 0) {
>> + dev_err(dev, "Unable to request IRQ %d\n", irq);
>> + return rc;
>> + }
>> +
>> + video->eclk = devm_clk_get(dev, "eclk");
>> + if (IS_ERR(video->eclk)) {
>> + dev_err(dev, "Unable to get ECLK\n");
>> + return PTR_ERR(video->eclk);
>> + }
>> +
>> + video->vclk = devm_clk_get(dev, "vclk");
>> + if (IS_ERR(video->vclk)) {
>> + dev_err(dev, "Unable to get VCLK\n");
>> + return PTR_ERR(video->vclk);
>> + }
>> +
>> + video->rst = devm_reset_control_get_exclusive(dev, NULL);
>> + if (IS_ERR(video->rst)) {
>> + dev_err(dev, "Unable to get VE reset\n");
>> + return PTR_ERR(video->rst);
>> + }
> As discussed in the clock driver, this can go as you've already
> released the reset when enabling the eclk.
I use the reset control by itself during a resolution change, so I would
like to have it available.
>
> However, you're requesting the clock without enabling it. You need to
> do a clk_prepare_enable().
That's because the clock is only enabled when the device is opened. No
reason to turn it on at boot time.
>
>> +
>> + rc = of_reserved_mem_device_init(dev);
>> + if (rc) {
>> + dev_err(dev, "Unable to reserve memory\n");
>> + return rc;
>> + }
>> +
>> + rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
>> + if (rc) {
>> + dev_err(dev, "Failed to set DMA mask\n");
>> + of_reserved_mem_device_release(dev);
>> + return rc;
>> + }
>> +
>> + if (!aspeed_video_alloc_buf(video, &video->jpeg,
>> + VE_JPEG_HEADER_SIZE)) {
>> + dev_err(dev, "Failed to allocate DMA for JPEG header\n");
>> + of_reserved_mem_device_release(dev);
>> + return rc;
>> + }
>> +
>> + aspeed_video_init_jpeg_table(video->jpeg.virt, video->yuv420);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id aspeed_video_of_match[] = {
>> + { .compatible = "aspeed,ast2400-video-engine" },
> I noticed the clock driver did not have the changed required for the
> 2400. Have you tested this on the ast2400?
The clocking setup is different on the ast2400. Xiuzhi on the openbmc
list has been testing on the ast2400 successfully.
Thanks,
Eddie
>
>
>> + { .compatible = "aspeed,ast2500-video-engine" },
>> + {}
>> +};
>> +MODULE_DEVICE_TABLE(of, aspeed_video_of_match);
>> +
>> +static struct platform_driver aspeed_video_driver = {
>> + .driver = {
>> + .name = DEVICE_NAME,
>> + .of_match_table = aspeed_video_of_match,
>> + },
>> + .probe = aspeed_video_probe,
>> + .remove = aspeed_video_remove,
>> +};
^ permalink raw reply
* [PATCH] ARM: dts: aspeed: Add #interrupt-cells property to gpio controllers
From: Mark Walton @ 2018-12-14 12:07 UTC (permalink / raw)
To: linux-aspeed
Allows the GPIO controller to be used as an interrupt parent.
of_irq_find_parent() skips interrupt controller nodes that do
not have the #interrupt-cells property.
Signed-off-by: Mark Walton <mark.walton@serialtek.com>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 1 +
arch/arm/boot/dts/aspeed-g5.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 69f6b9d2e7e7..9549f867aa1e 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -197,6 +197,7 @@
gpio-ranges = <&pinctrl 0 0 220>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
+ #interrupt-cells = <2>;
};
timer: timer at 1e782000 {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8..a1999f3fe330 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -250,6 +250,7 @@
gpio-ranges = <&pinctrl 0 0 220>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
+ #interrupt-cells = <2>;
};
timer: timer at 1e782000 {
--
2.20.0
^ permalink raw reply related
* [PATCH v8 2/2] media: platform: Add Aspeed Video Engine driver
From: Joel Stanley @ 2018-12-14 1:09 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1544547421-25724-3-git-send-email-eajames@linux.ibm.com>
On Wed, 12 Dec 2018 at 04:09, Eddie James <eajames@linux.ibm.com> wrote:
>
> The Video Engine (VE) embedded in the Aspeed AST2400 and AST2500 SOCs
> can capture and compress video data from digital or analog sources. With
> the Aspeed chip acting a service processor, the Video Engine can capture
> the host processor graphics output.
> +ASPEED VIDEO ENGINE DRIVER
> +M: Eddie James <eajames@linux.ibm.com>
> +L: linux-media at vger.kernel.org
> +L: openbmc at lists.ozlabs.org (moderated for non-subscribers)
We tend to use the linux-aspeed list for upstream kernel discussions.
Up to you if you want to use the openbmc list though.
> source "drivers/media/platform/omap/Kconfig"
>
> +config VIDEO_ASPEED
> + tristate "Aspeed AST2400 and AST2500 Video Engine driver"
> + depends on VIDEO_V4L2
> + select VIDEOBUF2_DMA_CONTIG
> + help
> + Support for the Aspeed Video Engine (VE) embedded in the Aspeed
> + AST2400 and AST2500 SOCs. The VE can capture and compress video data
> + from digital or analog sources.
This might need updating in response to my questions below about
ast2400 testing.
> +++ b/drivers/media/platform/aspeed-video.c
> @@ -0,0 +1,1729 @@
> +// SPDX-License-Identifier: GPL-2.0+
You need to put this there as well:
// Copyright 2018 IBM Corp
> +static int aspeed_video_init(struct aspeed_video *video)
> +{
> + int irq;
> + int rc;
> + struct device *dev = video->dev;
> +
> + irq = irq_of_parse_and_map(dev->of_node, 0);
> + if (!irq) {
> + dev_err(dev, "Unable to find IRQ\n");
> + return -ENODEV;
> + }
> +
> + rc = devm_request_irq(dev, irq, aspeed_video_irq, IRQF_SHARED,
The datasheet indicates this IRQ is for the video engline only, so I
don't think you want IRQF_SHARED.
> + DEVICE_NAME, video);
> + if (rc < 0) {
> + dev_err(dev, "Unable to request IRQ %d\n", irq);
> + return rc;
> + }
> +
> + video->eclk = devm_clk_get(dev, "eclk");
> + if (IS_ERR(video->eclk)) {
> + dev_err(dev, "Unable to get ECLK\n");
> + return PTR_ERR(video->eclk);
> + }
> +
> + video->vclk = devm_clk_get(dev, "vclk");
> + if (IS_ERR(video->vclk)) {
> + dev_err(dev, "Unable to get VCLK\n");
> + return PTR_ERR(video->vclk);
> + }
> +
> + video->rst = devm_reset_control_get_exclusive(dev, NULL);
> + if (IS_ERR(video->rst)) {
> + dev_err(dev, "Unable to get VE reset\n");
> + return PTR_ERR(video->rst);
> + }
As discussed in the clock driver, this can go as you've already
released the reset when enabling the eclk.
However, you're requesting the clock without enabling it. You need to
do a clk_prepare_enable().
> +
> + rc = of_reserved_mem_device_init(dev);
> + if (rc) {
> + dev_err(dev, "Unable to reserve memory\n");
> + return rc;
> + }
> +
> + rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
> + if (rc) {
> + dev_err(dev, "Failed to set DMA mask\n");
> + of_reserved_mem_device_release(dev);
> + return rc;
> + }
> +
> + if (!aspeed_video_alloc_buf(video, &video->jpeg,
> + VE_JPEG_HEADER_SIZE)) {
> + dev_err(dev, "Failed to allocate DMA for JPEG header\n");
> + of_reserved_mem_device_release(dev);
> + return rc;
> + }
> +
> + aspeed_video_init_jpeg_table(video->jpeg.virt, video->yuv420);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id aspeed_video_of_match[] = {
> + { .compatible = "aspeed,ast2400-video-engine" },
I noticed the clock driver did not have the changed required for the
2400. Have you tested this on the ast2400?
> + { .compatible = "aspeed,ast2500-video-engine" },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, aspeed_video_of_match);
> +
> +static struct platform_driver aspeed_video_driver = {
> + .driver = {
> + .name = DEVICE_NAME,
> + .of_match_table = aspeed_video_of_match,
> + },
> + .probe = aspeed_video_probe,
> + .remove = aspeed_video_remove,
> +};
^ permalink raw reply
* [PATCH 2/2] clk: aspeed: Setup video engine clocking
From: Joel Stanley @ 2018-12-14 1:02 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1544559161-21468-3-git-send-email-eajames@linux.ibm.com>
Hi Eddie,
On Wed, 12 Dec 2018 at 06:42, Eddie James <eajames@linux.ibm.com> wrote:
>
> Add the video engine reset bit. Add eclk mux and clock divider table.
>
> Signed-off-by: Eddie James <eajames@linux.ibm.com>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> ---
> drivers/clk/clk-aspeed.c | 41 +++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 39 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
> index 5961367..f16ce7d 100644
> --- a/drivers/clk/clk-aspeed.c
> +++ b/drivers/clk/clk-aspeed.c
> @@ -87,7 +87,7 @@ struct aspeed_clk_gate {
> /* TODO: ask Aspeed about the actual parent data */
> static const struct aspeed_gate_data aspeed_gates[] = {
> /* clk rst name parent flags */
> - [ASPEED_CLK_GATE_ECLK] = { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
> + [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
> [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
> [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
> [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
> @@ -113,6 +113,24 @@ struct aspeed_clk_gate {
> [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
> };
>
> +static const char * const eclk_parent_names[] = {
> + "mpll",
Is the mpll really an input to the eclk?
> + "hpll",
> + "dpll",
We don't have a dpll in the driver that I can see.
> +};
> +
> +static const struct clk_div_table ast2500_eclk_div_table[] = {
Is the clocking setup different on the ast2400?
> + { 0x0, 2 },
> + { 0x1, 2 },
> + { 0x2, 3 },
> + { 0x3, 4 },
> + { 0x4, 5 },
> + { 0x5, 6 },
> + { 0x6, 7 },
> + { 0x7, 8 },
> + { 0 }
> +};
> @@ -317,6 +338,7 @@ struct aspeed_reset {
> [ASPEED_RESET_PECI] = 10,
> [ASPEED_RESET_I2C] = 2,
> [ASPEED_RESET_AHB] = 1,
> + [ASPEED_RESET_VIDEO] = 6,
You've added the reset line to the ASPEED_CLK_GATE_ECLK clock so you
do not need to separately expose the reset controller. Instead
enabling the clock will deassert the rest line for you.
This means you should drop the change from the header too, and it
affects the bindings document for the video engine.
>
> /*
> * SCUD4 resets start at an offset to separate them from
> @@ -522,6 +544,22 @@ static int aspeed_clk_probe(struct platform_device *pdev)
> return PTR_ERR(hw);
> aspeed_clk_data->hws[ASPEED_CLK_24M] = hw;
>
> + hw = clk_hw_register_mux(dev, "eclk-mux", eclk_parent_names,
> + ARRAY_SIZE(eclk_parent_names), 0,
> + scu_base + ASPEED_CLK_SELECTION, 2, 0x3, 0,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw;
> +
> + hw = clk_hw_register_divider_table(dev, "eclk", "eclk-mux", 0,
> + scu_base + ASPEED_CLK_SELECTION, 28,
> + 3, 0, soc_data->eclk_div_table,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw;
> +
> /*
> * TODO: There are a number of clocks that not included in this driver
> * as more information is required:
> @@ -531,7 +569,6 @@ static int aspeed_clk_probe(struct platform_device *pdev)
> * RGMII
> * RMII
> * UART[1..5] clock source mux
> - * Video Engine (ECLK) mux and clock divider
> */
>
> for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) {
> --
> 1.8.3.1
>
^ permalink raw reply
* [PATCH 1/4] ARM: dts: aspeed: Add sensors devices for Facebook
From: Joel Stanley @ 2018-12-13 22:56 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20181213195319.1333402-1-vijaykhemka@fb.com>
On Fri, 14 Dec 2018 at 06:23, Vijay Khemka <vijaykhemka@fb.com> wrote:
>
> Added ADC and other sensor devices in Facebook Tiogapass device tree.
>
> Signed-off-by: Vijay Khemka <vijaykhemka@fb.com>
> ---
> .../dts/aspeed-bmc-facebook-tiogapass.dts | 33 +++++++++++++++++--
> 1 file changed, 31 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
> index f8e7b71af7e6..58bbe08d3ba7 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
> @@ -21,6 +21,25 @@
> memory at 80000000 {
> reg = <0x80000000 0x20000000>;
> };
> +
> + iio-hwmon {
> + compatible = "iio-hwmon";
> + oemname0 = "MB_P3V3";
> + oemname1 = "MB_P5V";
> + oemname2 = "MB_P12V";
> + oemname3 = "MB_P1V05";
> + oemname4 = "MB_PVNN_PCH_STBY";
> + oemname5 = "MB_P3V3_STBY";
> + oemname6 = "MB_P5V_STBY";
"oemname" isn't part of the upstream bindings. Is this something you
have patches for?
The other parts of the patch lgtm.
> + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
> + <&adc 4>, <&adc 5>, <&adc 6>;
> + };
> +
> + iio-hwmon-battery {
> + oemname0 = "MB_P3V_BAT";
> + compatible = "iio-hwmon";
> + io-channels = <&adc 7>;
> + };
> };
>
> &fmc {
> @@ -64,6 +83,10 @@
> use-ncsi;
> };
>
> +&adc {
> + status = "okay";
> +};
> +
> &i2c0 {
> status = "okay";
> //Airmax Conn B, CPU0 PIROM, CPU1 PIROM
> @@ -122,6 +145,10 @@
>
> &i2c8 {
> status = "okay";
> + tmp421 at 1f {
> + compatible = "ti,tmp421";
> + reg = <0x1f>;
> + };
> //Mezz Sensor SMBus
> };
>
> @@ -134,13 +161,15 @@
> status = "okay";
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
> + oemname0 = "System_Fan_Connector_1";
> + oemname1 = "System_Fan_Connector_3";
> fan at 0 {
> reg = <0x00>;
> aspeed,fan-tach-ch = /bits/ 8 <0x00>;
> };
>
> fan at 1 {
> - reg = <0x00>;
> - aspeed,fan-tach-ch = /bits/ 8 <0x01>;
> + reg = <0x01>;
> + aspeed,fan-tach-ch = /bits/ 8 <0x02>;
> };
> };
> --
> 2.17.1
>
^ permalink raw reply
* [PATCH 4/4] ARM: dts: aspeed: Add lpc ctrl for Facebook
From: Vijay Khemka @ 2018-12-13 19:53 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20181213195319.1333402-1-vijaykhemka@fb.com>
Added lpc ctrl device to enable LPC clock in Facebook
Tiogapass device tree.
Signed-off-by: Vijay Khemka <vijaykhemka@fb.com>
---
.../boot/dts/aspeed-bmc-facebook-tiogapass.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
index b99751b3e080..084110007f5d 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
@@ -22,6 +22,17 @@
reg = <0x80000000 0x20000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region at 98000000 {
+ no-map;
+ reg = <0x98000000 0x00001000>; /* 4K */
+ };
+ };
+
iio-hwmon {
compatible = "iio-hwmon";
oemname0 = "MB_P3V3";
@@ -62,6 +73,12 @@
};
};
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
&uart1 {
// Host Console
status = "okay";
--
2.17.1
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: aspeed: Add KCS for Facebook
From: Vijay Khemka @ 2018-12-13 19:53 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20181213195319.1333402-1-vijaykhemka@fb.com>
Added kcs device in Facebook Tiogapass device tree.
Signed-off-by: Vijay Khemka <vijaykhemka@fb.com>
---
arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
index 58bbe08d3ba7..b99751b3e080 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
@@ -75,6 +75,18 @@
status = "okay";
};
+&kcs2 {
+ // BMC KCS channel 2
+ status = "okay";
+ kcs_addr = <0xca8>;
+};
+
+&kcs3 {
+ // BMC KCS channel 3
+ status = "okay";
+ kcs_addr = <0xca2>;
+};
+
&mac0 {
status = "okay";
--
2.17.1
^ permalink raw reply related
* [PATCH 2/4] ARM: dts: aspeed: Add KCS support for LPC BMC
From: Vijay Khemka @ 2018-12-13 19:53 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20181213195319.1333402-1-vijaykhemka@fb.com>
Added kcs device support for lpc BMC.
Signed-off-by: Vijay Khemka <vijaykhemka@fb.com>
---
arch/arm/boot/dts/aspeed-g5.dtsi | 33 +++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8..2743f400aa29 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -330,8 +330,32 @@
ranges = <0x0 0x1e789000 0x1000>;
lpc_bmc: lpc-bmc at 0 {
- compatible = "aspeed,ast2500-lpc-bmc";
+ compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
reg = <0x0 0x80>;
+ reg-io-width = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x80>;
+
+ kcs1: kcs1 at 0 {
+ compatible = "aspeed,ast2500-kcs-bmc";
+ interrupts = <8>;
+ kcs_chan = <1>;
+ status = "disabled";
+ };
+ kcs2: kcs2 at 0 {
+ compatible = "aspeed,ast2500-kcs-bmc";
+ interrupts = <8>;
+ kcs_chan = <2>;
+ status = "disabled";
+ };
+ kcs3: kcs3 at 0 {
+ compatible = "aspeed,ast2500-kcs-bmc";
+ interrupts = <8>;
+ kcs_chan = <3>;
+ status = "disabled";
+ };
};
lpc_host: lpc-host at 80 {
@@ -343,6 +367,13 @@
#size-cells = <1>;
ranges = <0x0 0x80 0x1e0>;
+ kcs4: kcs4 at 0 {
+ compatible = "aspeed,ast2500-kcs-bmc";
+ interrupts = <8>;
+ kcs_chan = <4>;
+ status = "disabled";
+ };
+
lpc_ctrl: lpc-ctrl at 0 {
compatible = "aspeed,ast2500-lpc-ctrl";
reg = <0x0 0x80>;
--
2.17.1
^ permalink raw reply related
* [PATCH 1/4] ARM: dts: aspeed: Add sensors devices for Facebook
From: Vijay Khemka @ 2018-12-13 19:53 UTC (permalink / raw)
To: linux-aspeed
Added ADC and other sensor devices in Facebook Tiogapass device tree.
Signed-off-by: Vijay Khemka <vijaykhemka@fb.com>
---
.../dts/aspeed-bmc-facebook-tiogapass.dts | 33 +++++++++++++++++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
index f8e7b71af7e6..58bbe08d3ba7 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
@@ -21,6 +21,25 @@
memory at 80000000 {
reg = <0x80000000 0x20000000>;
};
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ oemname0 = "MB_P3V3";
+ oemname1 = "MB_P5V";
+ oemname2 = "MB_P12V";
+ oemname3 = "MB_P1V05";
+ oemname4 = "MB_PVNN_PCH_STBY";
+ oemname5 = "MB_P3V3_STBY";
+ oemname6 = "MB_P5V_STBY";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>;
+ };
+
+ iio-hwmon-battery {
+ oemname0 = "MB_P3V_BAT";
+ compatible = "iio-hwmon";
+ io-channels = <&adc 7>;
+ };
};
&fmc {
@@ -64,6 +83,10 @@
use-ncsi;
};
+&adc {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
//Airmax Conn B, CPU0 PIROM, CPU1 PIROM
@@ -122,6 +145,10 @@
&i2c8 {
status = "okay";
+ tmp421 at 1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
//Mezz Sensor SMBus
};
@@ -134,13 +161,15 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
+ oemname0 = "System_Fan_Connector_1";
+ oemname1 = "System_Fan_Connector_3";
fan at 0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
fan at 1 {
- reg = <0x00>;
- aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
};
--
2.17.1
^ permalink raw reply related
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