* [v8] gpio: aspeed: Add SGPIO driver
From: Hongwei Zhang @ 2019-08-20 21:05 UTC (permalink / raw)
To: linux-aspeed
Hello,
This short series introduce dt-binding document and a driver for the
Aspeed AST2500 SGPIO controller. Please review.
[v8]: Changes between v7 and v8:
- v7 updates based on Linus' feedback
- since Linus has already merged sgpio-aspeed.txt, I only include
the driver here to avoid confusion.
[v7]: Changes between v6 and v7:
- fix missing variable 'reg' assign issue in aspeed_sgpio_set()
- v6 feedback updates
[v6]: Changes between v5 and v6:
- fix a bug in aspeed_sgpio_dir_out()
- v5 feedback updates, some comments cleanup
The related SGPM pinmux dt-binding document, dts, and pinctrl driver
updates have been accepted and merged:
_http://patchwork.ozlabs.org/patch/1110210/
Hongwei Zhang (1):
gpio: aspeed: Add SGPIO driver
drivers/gpio/sgpio-aspeed.c | 533 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 533 insertions(+)
create mode 100644 drivers/gpio/sgpio-aspeed.c
--
2.7.4
^ permalink raw reply
* [PATCH v2 2/2] watchdog: aspeed: Add support for AST2600
From: Guenter Roeck @ 2019-08-20 15:50 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190819051738.17370-3-joel@jms.id.au>
On Mon, Aug 19, 2019 at 02:47:38PM +0930, Joel Stanley wrote:
> From: Ryan Chen <ryan_chen@aspeedtech.com>
>
> The ast2600 can be supported by the same code as the ast2500.
>
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
> ---
> v2:
> Reuse ast2500 config structure
> ---
> drivers/watchdog/aspeed_wdt.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
> index cc71861e033a..5b64bc2e8788 100644
> --- a/drivers/watchdog/aspeed_wdt.c
> +++ b/drivers/watchdog/aspeed_wdt.c
> @@ -34,6 +34,7 @@ static const struct aspeed_wdt_config ast2500_config = {
> static const struct of_device_id aspeed_wdt_of_table[] = {
> { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
> { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
> + { .compatible = "aspeed,ast2600-wdt", .data = &ast2500_config },
> { },
> };
> MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
> @@ -259,7 +260,8 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
> set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
> }
>
> - if (of_device_is_compatible(np, "aspeed,ast2500-wdt")) {
> + if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
> + (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
> u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
>
> reg &= config->ext_pulse_width_mask;
^ permalink raw reply
* [PATCH v2 2/2] watchdog: aspeed: Add support for AST2600
From: Joel Stanley @ 2019-08-19 5:17 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190819051738.17370-1-joel@jms.id.au>
From: Ryan Chen <ryan_chen@aspeedtech.com>
The ast2600 can be supported by the same code as the ast2500.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v2:
Reuse ast2500 config structure
---
drivers/watchdog/aspeed_wdt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
index cc71861e033a..5b64bc2e8788 100644
--- a/drivers/watchdog/aspeed_wdt.c
+++ b/drivers/watchdog/aspeed_wdt.c
@@ -34,6 +34,7 @@ static const struct aspeed_wdt_config ast2500_config = {
static const struct of_device_id aspeed_wdt_of_table[] = {
{ .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
{ .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
+ { .compatible = "aspeed,ast2600-wdt", .data = &ast2500_config },
{ },
};
MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
@@ -259,7 +260,8 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
}
- if (of_device_is_compatible(np, "aspeed,ast2500-wdt")) {
+ if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
+ (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
reg &= config->ext_pulse_width_mask;
--
2.23.0.rc1
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: watchdog: Add ast2600 compatible
From: Joel Stanley @ 2019-08-19 5:17 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190819051738.17370-1-joel@jms.id.au>
This adds a compatible for the ast2600, a new ASPEED SoC.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
v2:
- Add Andrew's r-b
---
Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
index c5077a1f5cb3..d78d4a8fb868 100644
--- a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: must be one of:
- "aspeed,ast2400-wdt"
- "aspeed,ast2500-wdt"
+ - "aspeed,ast2600-wdt"
- reg: physical base address of the controller and length of memory mapped
region
--
2.23.0.rc1
^ permalink raw reply related
* [PATCH v2 0/2] watchdog: aspeed: Add support for ast2600
From: Joel Stanley @ 2019-08-19 5:17 UTC (permalink / raw)
To: linux-aspeed
Hello,
Here's a small patch series to enable the ast2600 watchdog.
v2 addresses Guenter's review.
Joel Stanley (1):
dt-bindings: watchdog: Add ast2600 compatible
Ryan Chen (1):
watchdog: aspeed: Add support for AST2600
Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 1 +
drivers/watchdog/aspeed_wdt.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
--
2.23.0.rc1
^ permalink raw reply
* [PATCH 2/2] clk: Add support for AST2600 SoC
From: Joel Stanley @ 2019-08-19 2:03 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190816171441.3B8F720665@mail.kernel.org>
On Fri, 16 Aug 2019 at 17:14, Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Joel Stanley (2019-08-16 08:58:06)
> > diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
> > new file mode 100644
> > index 000000000000..083d5299238c
> > --- /dev/null
> > +++ b/drivers/clk/clk-ast2600.c
> > @@ -0,0 +1,701 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +// Copyright IBM Corp
> > +// Copyright ASPEED Technology
> > +
> [...]
> > +#define ASPEED_DPLL_PARAM 0x260
> > +
> > +#define ASPEED_G6_STRAP1 0x500
> > +
> > +/* Globally visible clocks */
> > +static DEFINE_SPINLOCK(aspeed_clk_lock);
>
> I guess we can be guaranteed that the two drivers aren't compiled into
> the same image? Otherwise this will alias with clk-aspeed.c and make
> kallsyms annoying to use.
I will change the name.
>
> > +
> > +/* Keeps track of all clocks */
> > +static struct clk_hw_onecell_data *aspeed_g6_clk_data;
> > +
> > +static void __iomem *scu_g6_base;
> > +
> > +static const struct aspeed_gate_data aspeed_g6_gates[] = {
> > + /* clk rst name parent flags */
> > + [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
>
> Please document CLK_IS_CRITICAL usage. I guess it's memory so never turn
> it off?
Yes.
I added some comments and removed some uses that I didn't know the
reason for. We can add them back later if required, with the
reasoning.
> > +static const char * const vclk_parent_names[] = {
>
> Can you use the new way of specifying clk parents instead of just using
> strings?
How does this work? I had a browse of the APIs in clk-provider.h and
it appeared the functions all take char *s still.
> > + hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
>
> There aren't checks for if these things fail. I guess it doesn't matter
> and just let it fail hard?
I think that's sensible here. If the system has run out of memory this
early on then there's not going to be much that works.
Thanks for the review. I've fixed all of the style issues you
mentioned, but would appreciate some guidance on the parent API.
Cheers,
Joel
^ permalink raw reply
* [PATCH 1/2] dt-bindings: watchdog: Add ast2600 compatible
From: Andrew Jeffery @ 2019-08-19 0:16 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190816160347.23393-2-joel@jms.id.au>
On Sat, 17 Aug 2019, at 01:34, Joel Stanley wrote:
> This adds a compatible for the ast2600, a new ASPEED SoC.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
> b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
> index c5077a1f5cb3..d78d4a8fb868 100644
> --- a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
> +++ b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
> @@ -4,6 +4,7 @@ Required properties:
> - compatible: must be one of:
> - "aspeed,ast2400-wdt"
> - "aspeed,ast2500-wdt"
> + - "aspeed,ast2600-wdt"
>
> - reg: physical base address of the controller and length of memory mapped
> region
> --
> 2.23.0.rc1
>
>
^ permalink raw reply
* [PATCH 2/2] clk: Add support for AST2600 SoC
From: Stephen Boyd @ 2019-08-16 17:14 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190816155806.22869-3-joel@jms.id.au>
Quoting Joel Stanley (2019-08-16 08:58:06)
> diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
> new file mode 100644
> index 000000000000..083d5299238c
> --- /dev/null
> +++ b/drivers/clk/clk-ast2600.c
> @@ -0,0 +1,701 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +// Copyright IBM Corp
> +// Copyright ASPEED Technology
> +
[...]
> +#define ASPEED_DPLL_PARAM 0x260
> +
> +#define ASPEED_G6_STRAP1 0x500
> +
> +/* Globally visible clocks */
> +static DEFINE_SPINLOCK(aspeed_clk_lock);
I guess we can be guaranteed that the two drivers aren't compiled into
the same image? Otherwise this will alias with clk-aspeed.c and make
kallsyms annoying to use.
> +
> +/* Keeps track of all clocks */
> +static struct clk_hw_onecell_data *aspeed_g6_clk_data;
> +
> +static void __iomem *scu_g6_base;
> +
> +static const struct aspeed_gate_data aspeed_g6_gates[] = {
> + /* clk rst name parent flags */
> + [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
Please document CLK_IS_CRITICAL usage. I guess it's memory so never turn
it off?
> + [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
> + [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
> + /* vclk parent - dclk/d1clk/hclk/mclk */
> + [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
> + [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
> + /* From dpll */
> + [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
> + [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL },
> + [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
> + /* Reserved 8 */
> + [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
> + /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
> + [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */
> + /* Reserved 11/12 */
> + [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
> + [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
> + [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
> + /* Reserved 16/19 */
> + [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */
> + [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */
> + /* Reserved 22/23 */
> + [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */
> + [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */
> + /* Reserved 26 */
> + [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */
> + /* Reserved 28/29/30 */
> + [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, CLK_IS_CRITICAL }, /* LPC */
> + [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, CLK_IS_CRITICAL }, /* eSPI */
> + [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL },
> + /* Reserved 35 */
> + [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
> + [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
> + /* Reserved 38 RSA: no longer used */
> + /* Reserved 39 */
> + [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */
> + [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */
> + [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */
> + [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */
> + [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */
> + [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */
> + [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */
> + [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */
> + [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
> + [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
> + [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
> + [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
> + [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */
> + [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */
> + [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */
> + [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */
> + [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */
> + [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */
> + [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */
> + [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */
> + [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */
> + [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */
> + [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */
> +};
> +
> +static const char * const eclk_parent_names[] = { "mpll", "hpll", "dpll" };
> +
> +static const struct clk_div_table ast2600_eclk_div_table[] = {
> + { 0x0, 2 },
> + { 0x1, 2 },
> + { 0x2, 3 },
> + { 0x3, 4 },
> + { 0x4, 5 },
> + { 0x5, 6 },
> + { 0x6, 7 },
> + { 0x7, 8 },
> + { 0 }
> +};
> +
> +static const struct clk_div_table ast2600_mac_div_table[] = {
> + { 0x0, 4 },
> + { 0x1, 4 },
> + { 0x2, 6 },
> + { 0x3, 8 },
> + { 0x4, 10 },
> + { 0x5, 12 },
> + { 0x6, 14 },
> + { 0x7, 16 },
> + { 0 }
> +};
> +
> +static const struct clk_div_table ast2600_div_table[] = {
> + { 0x0, 4 },
> + { 0x1, 8 },
> + { 0x2, 12 },
> + { 0x3, 16 },
> + { 0x4, 20 },
> + { 0x5, 24 },
> + { 0x6, 28 },
> + { 0x7, 32 },
> + { 0 }
> +};
> +
> +/* For hpll/dpll/epll/mpll */
> +static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
> +{
> + unsigned int mult, div;
> +
> + if (val & BIT(24)) {
> + /* Pass through mode */
> + mult = div = 1;
> + } else {
> + /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
> + u32 m = val & 0x1fff;
> + u32 n = (val >> 13) & 0x3f;
> + u32 p = (val >> 19) & 0xf;
> + mult = (m + 1) / (n + 1);
> + div = (p + 1);
> + }
> + return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
> + mult, div);
> +};
> +
> +static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
> +{
> + unsigned int mult, div;
> +
> + if (val & BIT(20)) {
> + /* Pass through mode */
> + mult = div = 1;
> + } else {
> + /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
> + u32 m = (val >> 5) & 0x3f;
> + u32 od = (val >> 4) & 0x1;
> + u32 n = val & 0xf;
> +
> + mult = (2 - od) * (m + 2);
> + div = n + 1;
> + }
> + return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
> + mult, div);
> +};
> +
> +static u32 get_bit(u8 idx)
> +{
> + if (idx < 32)
> + return BIT(idx);
> + else
> + return BIT(idx - 32);
Please remove else and deindent last return.
> +}
> +
> +static u32 get_reset_reg(struct aspeed_clk_gate *gate)
> +{
> + if (gate->reset_idx < 32)
> + return ASPEED_G6_RESET_CTRL;
> + else
> + return ASPEED_G6_RESET_CTRL2;
Same comment.
> +}
> +
> +static u32 get_clock_reg(struct aspeed_clk_gate *gate)
> +{
> + if (gate->clock_idx < 32)
> + return ASPEED_G6_CLK_STOP_CTRL;
> + else
> + return ASPEED_G6_CLK_STOP_CTRL2;
Same comment.
> +}
> +
> +static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
> +{
> + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
> + u32 clk = get_bit(gate->clock_idx);
> + u32 rst = get_bit(gate->reset_idx);
> + u32 reg;
> + u32 enval;
> +
> + /*
> + * If the IP is in reset, treat the clock as not enabled,
> + * this happens with some clocks such as the USB one when
> + * coming from cold reset. Without this, aspeed_clk_enable()
> + * will fail to lift the reset.
> + */
> + if (gate->reset_idx >= 0) {
> + regmap_read(gate->map, get_reset_reg(gate), ®);
> +
> + if (reg & rst)
> + return 0;
> + }
> +
> + regmap_read(gate->map, get_clock_reg(gate), ®);
> +
> + enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
> +
> + return ((reg & clk) == enval) ? 1 : 0;
> +}
> +
> +static int aspeed_g6_clk_enable(struct clk_hw *hw)
> +{
> + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
> + unsigned long flags;
> + u32 clk = get_bit(gate->clock_idx);
> + u32 rst = get_bit(gate->reset_idx);
> +
> + spin_lock_irqsave(gate->lock, flags);
> +
> + if (aspeed_g6_clk_is_enabled(hw)) {
> + spin_unlock_irqrestore(gate->lock, flags);
> + return 0;
> + }
> +
> + if (gate->reset_idx >= 0) {
> + /* Put IP in reset */
> + regmap_write(gate->map, get_reset_reg(gate), rst);
> + /* Delay 100us */
> + udelay(100);
> + }
> +
> + /* Enable clock */
> + if (gate->flags & CLK_GATE_SET_TO_DISABLE)
> + regmap_write(gate->map, get_clock_reg(gate), clk);
> + else
> + /* Use set to clear register */
> + regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
Nitpick: Add braces on this because the comment is making it two lines.
> +
> + if (gate->reset_idx >= 0) {
> + /* A delay of 10ms is specified by the ASPEED docs */
> + mdelay(10);
> + /* Take IP out of reset */
> + regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
> + }
> +
> + spin_unlock_irqrestore(gate->lock, flags);
> +
> + return 0;
> +}
> +
> +static void aspeed_g6_clk_disable(struct clk_hw *hw)
> +{
> + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
> + unsigned long flags;
> + u32 clk = get_bit(gate->clock_idx);
> +
> + spin_lock_irqsave(gate->lock, flags);
> +
> + if (gate->flags & CLK_GATE_SET_TO_DISABLE)
> + regmap_write(gate->map, get_clock_reg(gate), clk);
> + else
> + /* Use set to clear register */
> + regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
Same nitpick
> +
> + spin_unlock_irqrestore(gate->lock, flags);
> +}
> +
> +static const struct clk_ops aspeed_g6_clk_gate_ops = {
> + .enable = aspeed_g6_clk_enable,
> + .disable = aspeed_g6_clk_disable,
> + .is_enabled = aspeed_g6_clk_is_enabled,
> +};
> +
> +static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct aspeed_reset *ar = to_aspeed_reset(rcdev);
> + u32 rst = get_bit(id);
> + u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
> +
> + /* Use set to clear register */
> + return regmap_write(ar->map, reg + 0x04, rst);
> +}
> +
> +static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct aspeed_reset *ar = to_aspeed_reset(rcdev);
> + u32 rst = get_bit(id);
> + u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
> +
> + return regmap_write(ar->map, reg, rst);
> +}
> +
> +static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct aspeed_reset *ar = to_aspeed_reset(rcdev);
> + int ret;
> + u32 val;
> + u32 rst = get_bit(id);
> + u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
> +
> + ret = regmap_read(ar->map, reg, &val);
> + if (ret)
> + return ret;
> +
> + return !!(val & rst);
> +}
> +
> +static const struct reset_control_ops aspeed_g6_reset_ops = {
> + .assert = aspeed_g6_reset_assert,
> + .deassert = aspeed_g6_reset_deassert,
> + .status = aspeed_g6_reset_status,
> +};
> +
> +static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
> + const char *name, const char *parent_name, unsigned long flags,
> + struct regmap *map, u8 clock_idx, u8 reset_idx,
> + u8 clk_gate_flags, spinlock_t *lock)
> +{
> + struct aspeed_clk_gate *gate;
> + struct clk_init_data init;
> + struct clk_hw *hw;
> + int ret;
> +
> + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> + if (!gate)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = name;
> + init.ops = &aspeed_g6_clk_gate_ops;
> + init.flags = flags;
> + init.parent_names = parent_name ? &parent_name : NULL;
> + init.num_parents = parent_name ? 1 : 0;
> +
> + gate->map = map;
> + gate->clock_idx = clock_idx;
> + gate->reset_idx = reset_idx;
> + gate->flags = clk_gate_flags;
> + gate->lock = lock;
> + gate->hw.init = &init;
> +
> + hw = &gate->hw;
> + ret = clk_hw_register(dev, hw);
> + if (ret) {
> + kfree(gate);
> + hw = ERR_PTR(ret);
> + }
> +
> + return hw;
> +}
> +
> +static const char * const vclk_parent_names[] = {
Can you use the new way of specifying clk parents instead of just using
strings?
> + "dpll",
> + "d1pll",
> + "hclk",
> + "mclk",
> +};
> +
> +static const char * const d1clk_parent_names[] = {
> + "dpll",
> + "epll",
> + "usb-phy-40m",
> + "gpioc6_clkin",
> + "dp_phy_pll",
> +};
> +
> +static int aspeed_g6_clk_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct aspeed_reset *ar;
> + struct regmap *map;
> + struct clk_hw *hw;
> + u32 val, rate;
> + int i, ret;
> +
> + map = syscon_node_to_regmap(dev->of_node);
> + if (IS_ERR(map)) {
> + dev_err(dev, "no syscon regmap\n");
> + return PTR_ERR(map);
> + }
> +
> + ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
> + if (!ar)
> + return -ENOMEM;
> +
> + ar->map = map;
> +
> + ar->rcdev.owner = THIS_MODULE;
> + ar->rcdev.nr_resets = 64;
> + ar->rcdev.ops = &aspeed_g6_reset_ops;
> + ar->rcdev.of_node = dev->of_node;
> +
> + ret = devm_reset_controller_register(dev, &ar->rcdev);
> + if (ret) {
> + dev_err(dev, "could not register reset controller\n");
> + return ret;
> + }
> +
> + /* UART clock div13 setting */
> + regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
> + if (val & UART_DIV13_EN)
> + rate = 24000000 / 13;
> + else
> + rate = 24000000;
> + hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
> +
> + /* UART6~13 clock div13 setting */
> + regmap_read(map, 0x80, &val);
> + if (val & BIT(31))
> + rate = 24000000 / 13;
> + else
> + rate = 24000000;
> + hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
> +
> + /* EMMC ext clock divider */
> + hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0,
> + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0,
> + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0,
> + ast2600_div_table,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
> +
> + /* SD/SDIO clock divider and gate */
> + hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
> + scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
> + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
> + ast2600_div_table,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
> +
> + /* MAC1/2 AHB bus clock divider */
> + hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
> + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
> + ast2600_mac_div_table,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
> +
> + /* MAC3/4 AHB bus clock divider */
> + hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
> + scu_g6_base + 0x310, 24, 3, 0,
> + ast2600_mac_div_table,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
> +
> + /* LPC Host (LHCLK) clock divider */
> + hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
> + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
> + ast2600_div_table,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
> +
> + /* gfx d1clk : use dp clk */
> + regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
> + /* SoC Display clock selection */
> + hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
> + ARRAY_SIZE(d1clk_parent_names), 0,
> + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
> +
> + //d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1
> + regmap_write(map, 0x308, 0x12000); //3x3 = 9
> +
> + /* P-Bus (BCLK) clock divider */
> + hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
> + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
> + ast2600_div_table,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
> +
> + /* Video Capture clock selection */
> + hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
> + ARRAY_SIZE(vclk_parent_names), 0,
> + scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
> +
> + /* Video Engine clock divider */
> + hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
> + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
> + ast2600_eclk_div_table,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
> +
> + for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
> + const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
> + u32 gate_flags;
> +
> + /* Special case: the USB port 1 clock (bit 14) is always
/*
* Please make multi-line comments like this
*/
> + * working the opposite way from the other ones.
> + */
> + gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
> + hw = aspeed_g6_clk_hw_register_gate(dev,
> + gd->name,
> + gd->parent_name,
> + gd->flags,
> + map,
> + gd->clock_idx,
> + gd->reset_idx,
> + gate_flags,
> + &aspeed_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[i] = hw;
> + }
> +
> + return 0;
> +};
> +
> +static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
> + { .compatible = "aspeed,ast2600-scu" },
> + { }
> +};
> +
> +static struct platform_driver aspeed_g6_clk_driver = {
> + .probe = aspeed_g6_clk_probe,
> + .driver = {
> + .name = "ast2600-clk",
> + .of_match_table = aspeed_g6_clk_dt_ids,
> + .suppress_bind_attrs = true,
> + },
> +};
> +builtin_platform_driver(aspeed_g6_clk_driver);
> +
> +static u32 ast2600_a0_axi_ahb_div_table[] = {
> + 2, 2, 3, 5,
> +};
> +
> +static u32 ast2600_a1_axi_ahb_div_table[] = {
> + 4, 6, 2, 4,
> +};
> +
> +static void __init aspeed_g6_cc(struct regmap *map)
> +{
> + struct clk_hw *hw;
> + u32 val, div, chip_id, axi_div, ahb_div;
> +
> + clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
Shouldn't this come from DT?
> +
> + /*
> + * High-speed PLL clock derived from the crystal. This the CPU clock,
> + * and we assume that it is enabled
> + */
> + regmap_read(map, ASPEED_HPLL_PARAM, &val);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
> +
> + regmap_read(map, ASPEED_MPLL_PARAM, &val);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
> +
> + regmap_read(map, ASPEED_DPLL_PARAM, &val);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
> +
> + regmap_read(map, ASPEED_EPLL_PARAM, &val);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
> +
> + regmap_read(map, ASPEED_APLL_PARAM, &val);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
> +
> + /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
> + regmap_read(map, ASPEED_G6_STRAP1, &val);
> + if (val & BIT(16))
> + axi_div = 1;
> + else
> + axi_div = 2;
> +
> + regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
> + if (chip_id & BIT(16))
> + ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];
> + else
> + ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
> +
> + hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
There aren't checks for if these things fail. I guess it doesn't matter
and just let it fail hard?
> + aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
> +
> + regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
> + val = (val >> 23) & 0x7;
> + div = 4 * (val + 1);
> + hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
> +
> + regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
> + val = (val >> 9) & 0x7;
> + div = 2 * (val + 1);
> + hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
> +
> + /* USB 2.0 port1 phy 40MHz clock */
> + hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
> +};
> +
> +static void __init aspeed_g6_cc_init(struct device_node *np)
> +{
> + struct regmap *map;
> + int ret;
> + int i;
> +
> + scu_g6_base = of_iomap(np, 0);
> + if (!scu_g6_base)
> + return;
> +
> + aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
> + ASPEED_G6_NUM_CLKS), GFP_KERNEL);
> + if (!aspeed_g6_clk_data)
> + return;
> +
> + /*
> + * This way all clocks fetched before the platform device probes,
> + * except those we assign here for early use, will be deferred.
> + */
> + for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
> + aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
> +
> + /*
> + * We check that the regmap works on this very first access,
> + * but as this is an MMIO-backed regmap, subsequent regmap
> + * access is not going to fail and we skip error checks from
> + * this point.
> + */
> + map = syscon_node_to_regmap(np);
> + if (IS_ERR(map)) {
> + pr_err("no syscon regmap\n");
> + return;
> + }
> +
> + aspeed_g6_cc(map);
> + aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
> + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
> + if (ret)
> + pr_err("failed to add DT provider: %d\n", ret);
> +};
> +CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);
> diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
> new file mode 100644
> index 000000000000..66567bd48d5b
> --- /dev/null
> +++ b/include/dt-bindings/clock/ast2600-clock.h
> @@ -0,0 +1,116 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
Is the parenthesis required? I don't think it is.
> +#ifndef DT_BINDINGS_AST2600_CLOCK_H
> +#define DT_BINDINGS_AST2600_CLOCK_H
> +
> +#define ASPEED_CLK_GATE_ECLK 0
> +#define ASPEED_CLK_GATE_GCLK 1
> +
> +#define ASPEED_CLK_GATE_MCLK 2
> +
> +#define ASPEED_CLK_GATE_VCLK 3
> +#define ASPEED_CLK_GATE_BCLK 4
^ permalink raw reply
* [PATCH 1/2] clk: aspeed: Move structures to header
From: Stephen Boyd @ 2019-08-16 17:01 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190816155806.22869-2-joel@jms.id.au>
Quoting Joel Stanley (2019-08-16 08:58:05)
> diff --git a/drivers/clk/clk-aspeed.h b/drivers/clk/clk-aspeed.h
> new file mode 100644
> index 000000000000..92d384367c25
> --- /dev/null
> +++ b/drivers/clk/clk-aspeed.h
> @@ -0,0 +1,74 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * Structures used by ASPEED clock drivers
> + *
> + * Copyright 2019 IBM Corp.
> + */
Please include reset.h (or whatever defines reset_controller_dev),
clk-provider.h, kernel.h (for container_of and types), and forward
declare struct regmap and clk_div_table here.
> +
> +/**
> + * struct aspeed_gate_data - Aspeed gated clocks
^ permalink raw reply
* [PATCH 2/2] watchdog: aspeed: Add support for AST2600
From: Guenter Roeck @ 2019-08-16 16:15 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190816160347.23393-3-joel@jms.id.au>
On Sat, Aug 17, 2019 at 01:33:47AM +0930, Joel Stanley wrote:
> From: Ryan Chen <ryan_chen@aspeedtech.com>
>
> The ast2600 can be supported by the same code as the ast2500.
>
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/watchdog/aspeed_wdt.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
> index cc71861e033a..94f73796ba9d 100644
> --- a/drivers/watchdog/aspeed_wdt.c
> +++ b/drivers/watchdog/aspeed_wdt.c
> @@ -31,9 +31,14 @@ static const struct aspeed_wdt_config ast2500_config = {
> .ext_pulse_width_mask = 0xfffff,
> };
>
> +static const struct aspeed_wdt_config ast2600_config = {
> + .ext_pulse_width_mask = 0xfffff,
> +};
> +
Why not just reuse ast2500_config ?
Guenter
> static const struct of_device_id aspeed_wdt_of_table[] = {
> { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
> { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
> + { .compatible = "aspeed,ast2600-wdt", .data = &ast2600_config },
> { },
> };
> MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
> @@ -259,7 +264,8 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
> set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
> }
>
> - if (of_device_is_compatible(np, "aspeed,ast2500-wdt")) {
> + if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
> + (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
> u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
>
> reg &= config->ext_pulse_width_mask;
> --
> 2.23.0.rc1
>
^ permalink raw reply
* [PATCH 2/2] watchdog: aspeed: Add support for AST2600
From: Joel Stanley @ 2019-08-16 16:03 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190816160347.23393-1-joel@jms.id.au>
From: Ryan Chen <ryan_chen@aspeedtech.com>
The ast2600 can be supported by the same code as the ast2500.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/watchdog/aspeed_wdt.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
index cc71861e033a..94f73796ba9d 100644
--- a/drivers/watchdog/aspeed_wdt.c
+++ b/drivers/watchdog/aspeed_wdt.c
@@ -31,9 +31,14 @@ static const struct aspeed_wdt_config ast2500_config = {
.ext_pulse_width_mask = 0xfffff,
};
+static const struct aspeed_wdt_config ast2600_config = {
+ .ext_pulse_width_mask = 0xfffff,
+};
+
static const struct of_device_id aspeed_wdt_of_table[] = {
{ .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
{ .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
+ { .compatible = "aspeed,ast2600-wdt", .data = &ast2600_config },
{ },
};
MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
@@ -259,7 +264,8 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
}
- if (of_device_is_compatible(np, "aspeed,ast2500-wdt")) {
+ if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
+ (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
reg &= config->ext_pulse_width_mask;
--
2.23.0.rc1
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: watchdog: Add ast2600 compatible
From: Joel Stanley @ 2019-08-16 16:03 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190816160347.23393-1-joel@jms.id.au>
This adds a compatible for the ast2600, a new ASPEED SoC.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
index c5077a1f5cb3..d78d4a8fb868 100644
--- a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: must be one of:
- "aspeed,ast2400-wdt"
- "aspeed,ast2500-wdt"
+ - "aspeed,ast2600-wdt"
- reg: physical base address of the controller and length of memory mapped
region
--
2.23.0.rc1
^ permalink raw reply related
* [PATCH 0/2] watchdog: aspeed: Add support for ast2600
From: Joel Stanley @ 2019-08-16 16:03 UTC (permalink / raw)
To: linux-aspeed
Hello,
Here's a small patch series to enable the ast2600 watchdog.
Joel Stanley (1):
dt-bindings: watchdog: Add ast2600 compatible
Ryan Chen (1):
watchdog: aspeed: Add support for AST2600
Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 1 +
drivers/watchdog/aspeed_wdt.c | 8 +++++++-
2 files changed, 8 insertions(+), 1 deletion(-)
--
2.23.0.rc1
^ permalink raw reply
* [PATCH 2/2] clk: Add support for AST2600 SoC
From: Joel Stanley @ 2019-08-16 15:58 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190816155806.22869-1-joel@jms.id.au>
The ast2600 is a new BMC SoC from ASPEED. It contains many more clocks
than the previous iterations, so support is broken out into it's own
driver.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-ast2600.c | 701 ++++++++++++++++++++++
include/dt-bindings/clock/ast2600-clock.h | 116 ++++
3 files changed, 818 insertions(+)
create mode 100644 drivers/clk/clk-ast2600.c
create mode 100644 include/dt-bindings/clock/ast2600-clock.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0cad76021297..0138fb14e6f8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
+obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
new file mode 100644
index 000000000000..083d5299238c
--- /dev/null
+++ b/drivers/clk/clk-ast2600.c
@@ -0,0 +1,701 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright IBM Corp
+// Copyright ASPEED Technology
+
+#define pr_fmt(fmt) "clk-ast2600: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include <dt-bindings/clock/ast2600-clock.h>
+
+#include "clk-aspeed.h"
+
+#define ASPEED_G6_NUM_CLKS 69
+
+#define ASPEED_G6_SILICON_REV 0x004
+
+#define ASPEED_G6_RESET_CTRL 0x040
+#define ASPEED_G6_RESET_CTRL2 0x050
+
+#define ASPEED_G6_CLK_STOP_CTRL 0x080
+#define ASPEED_G6_CLK_STOP_CTRL2 0x090
+
+#define ASPEED_G6_MISC_CTRL 0x0C0
+#define UART_DIV13_EN BIT(12)
+
+#define ASPEED_G6_CLK_SELECTION1 0x300
+#define ASPEED_G6_CLK_SELECTION2 0x304
+#define ASPEED_G6_CLK_SELECTION4 0x310
+
+#define ASPEED_HPLL_PARAM 0x200
+#define ASPEED_APLL_PARAM 0x210
+#define ASPEED_MPLL_PARAM 0x220
+#define ASPEED_EPLL_PARAM 0x240
+#define ASPEED_DPLL_PARAM 0x260
+
+#define ASPEED_G6_STRAP1 0x500
+
+/* Globally visible clocks */
+static DEFINE_SPINLOCK(aspeed_clk_lock);
+
+/* Keeps track of all clocks */
+static struct clk_hw_onecell_data *aspeed_g6_clk_data;
+
+static void __iomem *scu_g6_base;
+
+static const struct aspeed_gate_data aspeed_g6_gates[] = {
+ /* clk rst name parent flags */
+ [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
+ [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
+ [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
+ /* vclk parent - dclk/d1clk/hclk/mclk */
+ [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
+ [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
+ /* From dpll */
+ [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
+ [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL },
+ [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
+ /* Reserved 8 */
+ [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
+ /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
+ [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */
+ /* Reserved 11/12 */
+ [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
+ [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
+ [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
+ /* Reserved 16/19 */
+ [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */
+ [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */
+ /* Reserved 22/23 */
+ [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */
+ [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */
+ /* Reserved 26 */
+ [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */
+ /* Reserved 28/29/30 */
+ [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, CLK_IS_CRITICAL }, /* LPC */
+ [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, CLK_IS_CRITICAL }, /* eSPI */
+ [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL },
+ /* Reserved 35 */
+ [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
+ [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
+ /* Reserved 38 RSA: no longer used */
+ /* Reserved 39 */
+ [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */
+ [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */
+ [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */
+ [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */
+ [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */
+ [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */
+ [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */
+ [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */
+ [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
+ [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
+ [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
+ [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
+ [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */
+ [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */
+ [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */
+ [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */
+ [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */
+ [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */
+ [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */
+ [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */
+ [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */
+ [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */
+ [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */
+};
+
+static const char * const eclk_parent_names[] = { "mpll", "hpll", "dpll" };
+
+static const struct clk_div_table ast2600_eclk_div_table[] = {
+ { 0x0, 2 },
+ { 0x1, 2 },
+ { 0x2, 3 },
+ { 0x3, 4 },
+ { 0x4, 5 },
+ { 0x5, 6 },
+ { 0x6, 7 },
+ { 0x7, 8 },
+ { 0 }
+};
+
+static const struct clk_div_table ast2600_mac_div_table[] = {
+ { 0x0, 4 },
+ { 0x1, 4 },
+ { 0x2, 6 },
+ { 0x3, 8 },
+ { 0x4, 10 },
+ { 0x5, 12 },
+ { 0x6, 14 },
+ { 0x7, 16 },
+ { 0 }
+};
+
+static const struct clk_div_table ast2600_div_table[] = {
+ { 0x0, 4 },
+ { 0x1, 8 },
+ { 0x2, 12 },
+ { 0x3, 16 },
+ { 0x4, 20 },
+ { 0x5, 24 },
+ { 0x6, 28 },
+ { 0x7, 32 },
+ { 0 }
+};
+
+/* For hpll/dpll/epll/mpll */
+static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
+{
+ unsigned int mult, div;
+
+ if (val & BIT(24)) {
+ /* Pass through mode */
+ mult = div = 1;
+ } else {
+ /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
+ u32 m = val & 0x1fff;
+ u32 n = (val >> 13) & 0x3f;
+ u32 p = (val >> 19) & 0xf;
+ mult = (m + 1) / (n + 1);
+ div = (p + 1);
+ }
+ return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
+ mult, div);
+};
+
+static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
+{
+ unsigned int mult, div;
+
+ if (val & BIT(20)) {
+ /* Pass through mode */
+ mult = div = 1;
+ } else {
+ /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
+ u32 m = (val >> 5) & 0x3f;
+ u32 od = (val >> 4) & 0x1;
+ u32 n = val & 0xf;
+
+ mult = (2 - od) * (m + 2);
+ div = n + 1;
+ }
+ return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
+ mult, div);
+};
+
+static u32 get_bit(u8 idx)
+{
+ if (idx < 32)
+ return BIT(idx);
+ else
+ return BIT(idx - 32);
+}
+
+static u32 get_reset_reg(struct aspeed_clk_gate *gate)
+{
+ if (gate->reset_idx < 32)
+ return ASPEED_G6_RESET_CTRL;
+ else
+ return ASPEED_G6_RESET_CTRL2;
+}
+
+static u32 get_clock_reg(struct aspeed_clk_gate *gate)
+{
+ if (gate->clock_idx < 32)
+ return ASPEED_G6_CLK_STOP_CTRL;
+ else
+ return ASPEED_G6_CLK_STOP_CTRL2;
+}
+
+static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
+{
+ struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
+ u32 clk = get_bit(gate->clock_idx);
+ u32 rst = get_bit(gate->reset_idx);
+ u32 reg;
+ u32 enval;
+
+ /*
+ * If the IP is in reset, treat the clock as not enabled,
+ * this happens with some clocks such as the USB one when
+ * coming from cold reset. Without this, aspeed_clk_enable()
+ * will fail to lift the reset.
+ */
+ if (gate->reset_idx >= 0) {
+ regmap_read(gate->map, get_reset_reg(gate), ®);
+
+ if (reg & rst)
+ return 0;
+ }
+
+ regmap_read(gate->map, get_clock_reg(gate), ®);
+
+ enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
+
+ return ((reg & clk) == enval) ? 1 : 0;
+}
+
+static int aspeed_g6_clk_enable(struct clk_hw *hw)
+{
+ struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
+ unsigned long flags;
+ u32 clk = get_bit(gate->clock_idx);
+ u32 rst = get_bit(gate->reset_idx);
+
+ spin_lock_irqsave(gate->lock, flags);
+
+ if (aspeed_g6_clk_is_enabled(hw)) {
+ spin_unlock_irqrestore(gate->lock, flags);
+ return 0;
+ }
+
+ if (gate->reset_idx >= 0) {
+ /* Put IP in reset */
+ regmap_write(gate->map, get_reset_reg(gate), rst);
+ /* Delay 100us */
+ udelay(100);
+ }
+
+ /* Enable clock */
+ if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+ regmap_write(gate->map, get_clock_reg(gate), clk);
+ else
+ /* Use set to clear register */
+ regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
+
+ if (gate->reset_idx >= 0) {
+ /* A delay of 10ms is specified by the ASPEED docs */
+ mdelay(10);
+ /* Take IP out of reset */
+ regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
+ }
+
+ spin_unlock_irqrestore(gate->lock, flags);
+
+ return 0;
+}
+
+static void aspeed_g6_clk_disable(struct clk_hw *hw)
+{
+ struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
+ unsigned long flags;
+ u32 clk = get_bit(gate->clock_idx);
+
+ spin_lock_irqsave(gate->lock, flags);
+
+ if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+ regmap_write(gate->map, get_clock_reg(gate), clk);
+ else
+ /* Use set to clear register */
+ regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
+
+ spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static const struct clk_ops aspeed_g6_clk_gate_ops = {
+ .enable = aspeed_g6_clk_enable,
+ .disable = aspeed_g6_clk_disable,
+ .is_enabled = aspeed_g6_clk_is_enabled,
+};
+
+static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct aspeed_reset *ar = to_aspeed_reset(rcdev);
+ u32 rst = get_bit(id);
+ u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
+
+ /* Use set to clear register */
+ return regmap_write(ar->map, reg + 0x04, rst);
+}
+
+static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct aspeed_reset *ar = to_aspeed_reset(rcdev);
+ u32 rst = get_bit(id);
+ u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
+
+ return regmap_write(ar->map, reg, rst);
+}
+
+static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct aspeed_reset *ar = to_aspeed_reset(rcdev);
+ int ret;
+ u32 val;
+ u32 rst = get_bit(id);
+ u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
+
+ ret = regmap_read(ar->map, reg, &val);
+ if (ret)
+ return ret;
+
+ return !!(val & rst);
+}
+
+static const struct reset_control_ops aspeed_g6_reset_ops = {
+ .assert = aspeed_g6_reset_assert,
+ .deassert = aspeed_g6_reset_deassert,
+ .status = aspeed_g6_reset_status,
+};
+
+static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
+ const char *name, const char *parent_name, unsigned long flags,
+ struct regmap *map, u8 clock_idx, u8 reset_idx,
+ u8 clk_gate_flags, spinlock_t *lock)
+{
+ struct aspeed_clk_gate *gate;
+ struct clk_init_data init;
+ struct clk_hw *hw;
+ int ret;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &aspeed_g6_clk_gate_ops;
+ init.flags = flags;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+
+ gate->map = map;
+ gate->clock_idx = clock_idx;
+ gate->reset_idx = reset_idx;
+ gate->flags = clk_gate_flags;
+ gate->lock = lock;
+ gate->hw.init = &init;
+
+ hw = &gate->hw;
+ ret = clk_hw_register(dev, hw);
+ if (ret) {
+ kfree(gate);
+ hw = ERR_PTR(ret);
+ }
+
+ return hw;
+}
+
+static const char * const vclk_parent_names[] = {
+ "dpll",
+ "d1pll",
+ "hclk",
+ "mclk",
+};
+
+static const char * const d1clk_parent_names[] = {
+ "dpll",
+ "epll",
+ "usb-phy-40m",
+ "gpioc6_clkin",
+ "dp_phy_pll",
+};
+
+static int aspeed_g6_clk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct aspeed_reset *ar;
+ struct regmap *map;
+ struct clk_hw *hw;
+ u32 val, rate;
+ int i, ret;
+
+ map = syscon_node_to_regmap(dev->of_node);
+ if (IS_ERR(map)) {
+ dev_err(dev, "no syscon regmap\n");
+ return PTR_ERR(map);
+ }
+
+ ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
+ if (!ar)
+ return -ENOMEM;
+
+ ar->map = map;
+
+ ar->rcdev.owner = THIS_MODULE;
+ ar->rcdev.nr_resets = 64;
+ ar->rcdev.ops = &aspeed_g6_reset_ops;
+ ar->rcdev.of_node = dev->of_node;
+
+ ret = devm_reset_controller_register(dev, &ar->rcdev);
+ if (ret) {
+ dev_err(dev, "could not register reset controller\n");
+ return ret;
+ }
+
+ /* UART clock div13 setting */
+ regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
+ if (val & UART_DIV13_EN)
+ rate = 24000000 / 13;
+ else
+ rate = 24000000;
+ hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
+
+ /* UART6~13 clock div13 setting */
+ regmap_read(map, 0x80, &val);
+ if (val & BIT(31))
+ rate = 24000000 / 13;
+ else
+ rate = 24000000;
+ hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
+
+ /* EMMC ext clock divider */
+ hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0,
+ ast2600_div_table,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
+
+ /* SD/SDIO clock divider and gate */
+ hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
+ 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
+ ast2600_div_table,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
+
+ /* MAC1/2 AHB bus clock divider */
+ hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
+ ast2600_mac_div_table,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
+
+ /* MAC3/4 AHB bus clock divider */
+ hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
+ scu_g6_base + 0x310, 24, 3, 0,
+ ast2600_mac_div_table,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
+
+ /* LPC Host (LHCLK) clock divider */
+ hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
+ ast2600_div_table,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
+
+ /* gfx d1clk : use dp clk */
+ regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
+ /* SoC Display clock selection */
+ hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
+ ARRAY_SIZE(d1clk_parent_names), 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
+
+ //d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1
+ regmap_write(map, 0x308, 0x12000); //3x3 = 9
+
+ /* P-Bus (BCLK) clock divider */
+ hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
+ ast2600_div_table,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
+
+ /* Video Capture clock selection */
+ hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
+ ARRAY_SIZE(vclk_parent_names), 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
+
+ /* Video Engine clock divider */
+ hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
+ ast2600_eclk_div_table,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
+ const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
+ u32 gate_flags;
+
+ /* Special case: the USB port 1 clock (bit 14) is always
+ * working the opposite way from the other ones.
+ */
+ gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
+ hw = aspeed_g6_clk_hw_register_gate(dev,
+ gd->name,
+ gd->parent_name,
+ gd->flags,
+ map,
+ gd->clock_idx,
+ gd->reset_idx,
+ gate_flags,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[i] = hw;
+ }
+
+ return 0;
+};
+
+static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
+ { .compatible = "aspeed,ast2600-scu" },
+ { }
+};
+
+static struct platform_driver aspeed_g6_clk_driver = {
+ .probe = aspeed_g6_clk_probe,
+ .driver = {
+ .name = "ast2600-clk",
+ .of_match_table = aspeed_g6_clk_dt_ids,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver(aspeed_g6_clk_driver);
+
+static u32 ast2600_a0_axi_ahb_div_table[] = {
+ 2, 2, 3, 5,
+};
+
+static u32 ast2600_a1_axi_ahb_div_table[] = {
+ 4, 6, 2, 4,
+};
+
+static void __init aspeed_g6_cc(struct regmap *map)
+{
+ struct clk_hw *hw;
+ u32 val, div, chip_id, axi_div, ahb_div;
+
+ clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
+
+ /*
+ * High-speed PLL clock derived from the crystal. This the CPU clock,
+ * and we assume that it is enabled
+ */
+ regmap_read(map, ASPEED_HPLL_PARAM, &val);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
+
+ regmap_read(map, ASPEED_MPLL_PARAM, &val);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
+
+ regmap_read(map, ASPEED_DPLL_PARAM, &val);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
+
+ regmap_read(map, ASPEED_EPLL_PARAM, &val);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
+
+ regmap_read(map, ASPEED_APLL_PARAM, &val);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
+
+ /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
+ regmap_read(map, ASPEED_G6_STRAP1, &val);
+ if (val & BIT(16))
+ axi_div = 1;
+ else
+ axi_div = 2;
+
+ regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
+ if (chip_id & BIT(16))
+ ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];
+ else
+ ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
+
+ hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
+
+ regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
+ val = (val >> 23) & 0x7;
+ div = 4 * (val + 1);
+ hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
+
+ regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
+ val = (val >> 9) & 0x7;
+ div = 2 * (val + 1);
+ hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
+
+ /* USB 2.0 port1 phy 40MHz clock */
+ hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
+};
+
+static void __init aspeed_g6_cc_init(struct device_node *np)
+{
+ struct regmap *map;
+ int ret;
+ int i;
+
+ scu_g6_base = of_iomap(np, 0);
+ if (!scu_g6_base)
+ return;
+
+ aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
+ ASPEED_G6_NUM_CLKS), GFP_KERNEL);
+ if (!aspeed_g6_clk_data)
+ return;
+
+ /*
+ * This way all clocks fetched before the platform device probes,
+ * except those we assign here for early use, will be deferred.
+ */
+ for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
+ aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
+
+ /*
+ * We check that the regmap works on this very first access,
+ * but as this is an MMIO-backed regmap, subsequent regmap
+ * access is not going to fail and we skip error checks from
+ * this point.
+ */
+ map = syscon_node_to_regmap(np);
+ if (IS_ERR(map)) {
+ pr_err("no syscon regmap\n");
+ return;
+ }
+
+ aspeed_g6_cc(map);
+ aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
+ ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
+ if (ret)
+ pr_err("failed to add DT provider: %d\n", ret);
+};
+CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
new file mode 100644
index 000000000000..66567bd48d5b
--- /dev/null
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+#ifndef DT_BINDINGS_AST2600_CLOCK_H
+#define DT_BINDINGS_AST2600_CLOCK_H
+
+#define ASPEED_CLK_GATE_ECLK 0
+#define ASPEED_CLK_GATE_GCLK 1
+
+#define ASPEED_CLK_GATE_MCLK 2
+
+#define ASPEED_CLK_GATE_VCLK 3
+#define ASPEED_CLK_GATE_BCLK 4
+#define ASPEED_CLK_GATE_DCLK 5
+
+#define ASPEED_CLK_GATE_LCLK 6
+#define ASPEED_CLK_GATE_LHCCLK 7
+
+#define ASPEED_CLK_GATE_D1CLK 8
+#define ASPEED_CLK_GATE_YCLK 9
+
+#define ASPEED_CLK_GATE_REF0CLK 10
+#define ASPEED_CLK_GATE_REF1CLK 11
+
+#define ASPEED_CLK_GATE_ESPICLK 12
+
+#define ASPEED_CLK_GATE_USBUHCICLK 13
+#define ASPEED_CLK_GATE_USBPORT1CLK 14
+#define ASPEED_CLK_GATE_USBPORT2CLK 15
+
+#define ASPEED_CLK_GATE_RSACLK 16
+#define ASPEED_CLK_GATE_RVASCLK 17
+
+#define ASPEED_CLK_GATE_MAC1CLK 18
+#define ASPEED_CLK_GATE_MAC2CLK 19
+#define ASPEED_CLK_GATE_MAC3CLK 20
+#define ASPEED_CLK_GATE_MAC4CLK 21
+
+#define ASPEED_CLK_GATE_UART1CLK 22
+#define ASPEED_CLK_GATE_UART2CLK 23
+#define ASPEED_CLK_GATE_UART3CLK 24
+#define ASPEED_CLK_GATE_UART4CLK 25
+#define ASPEED_CLK_GATE_UART5CLK 26
+#define ASPEED_CLK_GATE_UART6CLK 27
+#define ASPEED_CLK_GATE_UART7CLK 28
+#define ASPEED_CLK_GATE_UART8CLK 29
+#define ASPEED_CLK_GATE_UART9CLK 30
+#define ASPEED_CLK_GATE_UART10CLK 31
+#define ASPEED_CLK_GATE_UART11CLK 32
+#define ASPEED_CLK_GATE_UART12CLK 33
+#define ASPEED_CLK_GATE_UART13CLK 34
+
+#define ASPEED_CLK_GATE_SDCLK 35
+#define ASPEED_CLK_GATE_SDEXTCLK 36
+#define ASPEED_CLK_GATE_EMMCCLK 37
+#define ASPEED_CLK_GATE_EMMCEXTCLK 38
+
+#define ASPEED_CLK_GATE_I3C0CLK 39
+#define ASPEED_CLK_GATE_I3C1CLK 40
+#define ASPEED_CLK_GATE_I3C2CLK 41
+#define ASPEED_CLK_GATE_I3C3CLK 42
+#define ASPEED_CLK_GATE_I3C4CLK 43
+#define ASPEED_CLK_GATE_I3C5CLK 44
+#define ASPEED_CLK_GATE_I3C6CLK 45
+#define ASPEED_CLK_GATE_I3C7CLK 46
+
+#define ASPEED_CLK_GATE_FSICLK 47
+
+#define ASPEED_CLK_HPLL 48
+#define ASPEED_CLK_MPLL 49
+#define ASPEED_CLK_DPLL 50
+#define ASPEED_CLK_EPLL 51
+#define ASPEED_CLK_APLL 52
+#define ASPEED_CLK_AHB 53
+#define ASPEED_CLK_APB1 54
+#define ASPEED_CLK_APB2 55
+#define ASPEED_CLK_BCLK 56
+#define ASPEED_CLK_D1CLK 57
+#define ASPEED_CLK_VCLK 58
+#define ASPEED_CLK_LHCLK 59
+#define ASPEED_CLK_UART 60
+#define ASPEED_CLK_UARTX 61
+#define ASPEED_CLK_SDIO 62
+#define ASPEED_CLK_EMMC 63
+#define ASPEED_CLK_ECLK 64
+#define ASPEED_CLK_ECLK_MUX 65
+#define ASPEED_CLK_MAC12 66
+#define ASPEED_CLK_MAC34 67
+#define ASPEED_CLK_USBPHY_40M 68
+
+/* Only list resets here that are not part of a gate */
+#define ASPEED_RESET_SD 56
+#define ASPEED_RESET_ADC 55
+#define ASPEED_RESET_JTAG_MASTER2 54
+#define ASPEED_RESET_I3C_DMA 39
+#define ASPEED_RESET_PWM 37
+#define ASPEED_RESET_PECI 36
+#define ASPEED_RESET_MII 35
+#define ASPEED_RESET_I2C 34
+#define ASPEED_RESET_H2X 31
+#define ASPEED_RESET_GP_MCU 30
+#define ASPEED_RESET_DP_MCU 29
+#define ASPEED_RESET_DP 28
+#define ASPEED_RESET_RC_XDMA 27
+#define ASPEED_RESET_GRAPHICS 26
+#define ASPEED_RESET_DEV_XDMA 25
+#define ASPEED_RESET_DEV_MCTP 24
+#define ASPEED_RESET_RC_MCTP 23
+#define ASPEED_RESET_JTAG_MASTER 22
+#define ASPEED_RESET_PCIE_DEV_O 21
+#define ASPEED_RESET_PCIE_DEV_OEN 20
+#define ASPEED_RESET_PCIE_RC_O 19
+#define ASPEED_RESET_PCIE_RC_OEN 18
+#define ASPEED_RESET_PCI_DP 5
+#define ASPEED_RESET_AHB 1
+#define ASPEED_RESET_SDRAM 0
+
+#endif
--
2.23.0.rc1
^ permalink raw reply related
* [PATCH 1/2] clk: aspeed: Move structures to header
From: Joel Stanley @ 2019-08-16 15:58 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190816155806.22869-1-joel@jms.id.au>
They will be reused by the ast2600 driver.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/clk/clk-aspeed.c | 63 ++--------------------------------
drivers/clk/clk-aspeed.h | 74 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 76 insertions(+), 61 deletions(-)
create mode 100644 drivers/clk/clk-aspeed.h
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
index 898291501f45..44df54d87ad4 100644
--- a/drivers/clk/clk-aspeed.c
+++ b/drivers/clk/clk-aspeed.c
@@ -14,6 +14,8 @@
#include <dt-bindings/clock/aspeed-clock.h>
+#include "clk-aspeed.h"
+
#define ASPEED_NUM_CLKS 36
#define ASPEED_RESET2_OFFSET 32
@@ -42,48 +44,6 @@ static struct clk_hw_onecell_data *aspeed_clk_data;
static void __iomem *scu_base;
-/**
- * struct aspeed_gate_data - Aspeed gated clocks
- * @clock_idx: bit used to gate this clock in the clock register
- * @reset_idx: bit used to reset this IP in the reset register. -1 if no
- * reset is required when enabling the clock
- * @name: the clock name
- * @parent_name: the name of the parent clock
- * @flags: standard clock framework flags
- */
-struct aspeed_gate_data {
- u8 clock_idx;
- s8 reset_idx;
- const char *name;
- const char *parent_name;
- unsigned long flags;
-};
-
-/**
- * struct aspeed_clk_gate - Aspeed specific clk_gate structure
- * @hw: handle between common and hardware-specific interfaces
- * @reg: register controlling gate
- * @clock_idx: bit used to gate this clock in the clock register
- * @reset_idx: bit used to reset this IP in the reset register. -1 if no
- * reset is required when enabling the clock
- * @flags: hardware-specific flags
- * @lock: register lock
- *
- * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
- * This modified version of clk_gate allows an optional reset bit to be
- * specified.
- */
-struct aspeed_clk_gate {
- struct clk_hw hw;
- struct regmap *map;
- u8 clock_idx;
- s8 reset_idx;
- u8 flags;
- spinlock_t *lock;
-};
-
-#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
-
/* TODO: ask Aspeed about the actual parent data */
static const struct aspeed_gate_data aspeed_gates[] = {
/* clk rst name parent flags */
@@ -208,13 +168,6 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
mult, div);
}
-struct aspeed_clk_soc_data {
- const struct clk_div_table *div_table;
- const struct clk_div_table *eclk_div_table;
- const struct clk_div_table *mac_div_table;
- struct clk_hw *(*calc_pll)(const char *name, u32 val);
-};
-
static const struct aspeed_clk_soc_data ast2500_data = {
.div_table = ast2500_div_table,
.eclk_div_table = ast2500_eclk_div_table,
@@ -315,18 +268,6 @@ static const struct clk_ops aspeed_clk_gate_ops = {
.is_enabled = aspeed_clk_is_enabled,
};
-/**
- * struct aspeed_reset - Aspeed reset controller
- * @map: regmap to access the containing system controller
- * @rcdev: reset controller device
- */
-struct aspeed_reset {
- struct regmap *map;
- struct reset_controller_dev rcdev;
-};
-
-#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
-
static const u8 aspeed_resets[] = {
/* SCU04 resets */
[ASPEED_RESET_XDMA] = 25,
diff --git a/drivers/clk/clk-aspeed.h b/drivers/clk/clk-aspeed.h
new file mode 100644
index 000000000000..92d384367c25
--- /dev/null
+++ b/drivers/clk/clk-aspeed.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Structures used by ASPEED clock drivers
+ *
+ * Copyright 2019 IBM Corp.
+ */
+
+/**
+ * struct aspeed_gate_data - Aspeed gated clocks
+ * @clock_idx: bit used to gate this clock in the clock register
+ * @reset_idx: bit used to reset this IP in the reset register. -1 if no
+ * reset is required when enabling the clock
+ * @name: the clock name
+ * @parent_name: the name of the parent clock
+ * @flags: standard clock framework flags
+ */
+struct aspeed_gate_data {
+ u8 clock_idx;
+ s8 reset_idx;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+};
+
+/**
+ * struct aspeed_clk_gate - Aspeed specific clk_gate structure
+ * @hw: handle between common and hardware-specific interfaces
+ * @reg: register controlling gate
+ * @clock_idx: bit used to gate this clock in the clock register
+ * @reset_idx: bit used to reset this IP in the reset register. -1 if no
+ * reset is required when enabling the clock
+ * @flags: hardware-specific flags
+ * @lock: register lock
+ *
+ * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
+ * This modified version of clk_gate allows an optional reset bit to be
+ * specified.
+ */
+struct aspeed_clk_gate {
+ struct clk_hw hw;
+ struct regmap *map;
+ u8 clock_idx;
+ s8 reset_idx;
+ u8 flags;
+ spinlock_t *lock;
+};
+
+#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
+
+/**
+ * struct aspeed_reset - Aspeed reset controller
+ * @map: regmap to access the containing system controller
+ * @rcdev: reset controller device
+ */
+struct aspeed_reset {
+ struct regmap *map;
+ struct reset_controller_dev rcdev;
+};
+
+#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
+
+/**
+ * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information
+ * @div_table: Common divider lookup table
+ * @eclk_div_table: Divider lookup table for ECLK
+ * @mac_div_table: Divider lookup table for MAC (Ethernet) clocks
+ * @calc_pll: Callback to maculate common PLL settings
+ */
+struct aspeed_clk_soc_data {
+ const struct clk_div_table *div_table;
+ const struct clk_div_table *eclk_div_table;
+ const struct clk_div_table *mac_div_table;
+ struct clk_hw *(*calc_pll)(const char *name, u32 val);
+};
--
2.23.0.rc1
^ permalink raw reply related
* [PATCH 0/2] clk: Add driver for ast2600
From: Joel Stanley @ 2019-08-16 15:58 UTC (permalink / raw)
To: linux-aspeed
Hello clock maintainers,
This adds a new driver for the ast2600 BMC's clocks. It's a separate
from the existing aspeed one as the ast2600 changes enough from the
previous generation to make it hard to support with one driver.
It has been tested on the ast2600 evaluation board.
Joel Stanley (2):
clk: aspeed: Move structures to header
clk: Add support for AST2600 SoC
drivers/clk/Makefile | 1 +
drivers/clk/clk-aspeed.c | 63 +-
drivers/clk/clk-aspeed.h | 76 +++
drivers/clk/clk-ast2600.c | 711 ++++++++++++++++++++++
include/dt-bindings/clock/ast2600-clock.h | 116 ++++
5 files changed, 906 insertions(+), 61 deletions(-)
create mode 100644 drivers/clk/clk-aspeed.h
create mode 100644 drivers/clk/clk-ast2600.c
create mode 100644 include/dt-bindings/clock/ast2600-clock.h
--
2.23.0.rc1
^ permalink raw reply
* [PATCH v5 1/2] dt-bindings: mmc: Document Aspeed SD controller
From: Andrew Jeffery @ 2019-08-15 5:38 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CACPK8Xe6Zp1uOqEffEc0b6oGa7portEAifGPRqb876HmA+oZeg@mail.gmail.com>
On Thu, 15 Aug 2019, at 15:06, Joel Stanley wrote:
> On Wed, 7 Aug 2019 at 00:38, Andrew Jeffery <andrew@aj.id.au> wrote:
> >
> > The ASPEED SD/SDIO/MMC controller exposes two slots implementing the
> > SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit
> > data bus if only a single slot is enabled.
> >
> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
>
> Two minor comments below.
>
> > +++ b/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
> > @@ -0,0 +1,105 @@
> > +# SPDX-License-Identifier: GPL-2.0-or-later
>
> No "Copyright IBM" ?
I'm going rogue.
That reminds me I should chase up where we got to with the binding
licensing.
>
> > +%YAML 1.2
> > +---
>
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/aspeed-clock.h>
> > + sdc at 1e740000 {
> > + compatible = "aspeed,ast2500-sd-controller";
> > + reg = <0x1e740000 0x100>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0x1e740000 0x10000>;
>
> According to the datasheet this could be 0x20000. It does not matter
> though, as there's nothing in it past 0x300.
Good catch.
Andrew
^ permalink raw reply
* [PATCH v5 1/2] dt-bindings: mmc: Document Aspeed SD controller
From: Joel Stanley @ 2019-08-15 5:36 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190807003629.2974-2-andrew@aj.id.au>
On Wed, 7 Aug 2019 at 00:38, Andrew Jeffery <andrew@aj.id.au> wrote:
>
> The ASPEED SD/SDIO/MMC controller exposes two slots implementing the
> SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit
> data bus if only a single slot is enabled.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Two minor comments below.
> +++ b/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: GPL-2.0-or-later
No "Copyright IBM" ?
> +%YAML 1.2
> +---
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/aspeed-clock.h>
> + sdc at 1e740000 {
> + compatible = "aspeed,ast2500-sd-controller";
> + reg = <0x1e740000 0x100>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x1e740000 0x10000>;
According to the datasheet this could be 0x20000. It does not matter
though, as there's nothing in it past 0x300.
Cheers,
Joel
^ permalink raw reply
* [PATCH v5 2/2] mmc: Add support for the ASPEED SD controller
From: Joel Stanley @ 2019-08-15 5:28 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190807003629.2974-3-andrew@aj.id.au>
On Wed, 7 Aug 2019 at 00:38, Andrew Jeffery <andrew@aj.id.au> wrote:
>
> Add a minimal driver for ASPEED's SD controller, which exposes two
> SDHCIs.
>
> The ASPEED design implements a common register set for the SDHCIs, and
> moves some of the standard configuration elements out to this common
> area (e.g. 8-bit mode, and card detect configuration which is not
> currently supported).
>
> The SD controller has a dedicated hardware interrupt that is shared
> between the slots. The common register set exposes information on which
> slot triggered the interrupt; early revisions of the patch introduced an
> irqchip for the register, but reality is it doesn't behave as an
> irqchip, and the result fits awkwardly into the irqchip APIs. Instead
> I've taken the simple approach of using the IRQ as a shared IRQ with
> some minor performance impact for the second slot.
>
> Ryan was the original author of the patch - I've taken his work and
> massaged it to drop the irqchip support and rework the devicetree
> integration. The driver has been smoke tested under qemu against a
> minimal SD controller model and lightly tested on an ast2500-evb.
>
> Signed-off-by: Ryan Chen <ryanchen.aspeed@gmail.com>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
>
> ---
>
> v5:
> * Cleanup sdhci driver on registration failure
>
> v4: No change
>
> v2:
> * Add AST2600 compatible
> * Drop SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN
> * Ensure slot number is valid
> * Fix build with CONFIG_MODULES
> * Fix module license string
> * Non-PCI devices won't die
> * Rename aspeed_sdc_configure_8bit_mode()
> * Rename aspeed_sdhci_pdata
> * Switch to sdhci_enable_clk()
> * Use PTR_ERR() on the right `struct platform_device *`
> ---
> drivers/mmc/host/Kconfig | 12 ++
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/sdhci-of-aspeed.c | 332 +++++++++++++++++++++++++++++
> 3 files changed, 345 insertions(+)
> create mode 100644 drivers/mmc/host/sdhci-of-aspeed.c
>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 14d89a108edd..0f8a230de2f3 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -154,6 +154,18 @@ config MMC_SDHCI_OF_ARASAN
>
> If unsure, say N.
>
> +config MMC_SDHCI_OF_ASPEED
> + tristate "SDHCI OF support for the ASPEED SDHCI controller"
> + depends on MMC_SDHCI_PLTFM
> + depends on OF
> + help
> + This selects the ASPEED Secure Digital Host Controller Interface.
> +
> + If you have a controller with this interface, say Y or M here. You
> + also need to enable an appropriate bus interface.
> +
> + If unsure, say N.
> +
> config MMC_SDHCI_OF_AT91
> tristate "SDHCI OF support for the Atmel SDMMC controller"
> depends on MMC_SDHCI_PLTFM
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index 73578718f119..390ee162fe71 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -84,6 +84,7 @@ obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
> obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o
> obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o
> obj-$(CONFIG_MMC_SDHCI_OF_ARASAN) += sdhci-of-arasan.o
> +obj-$(CONFIG_MMC_SDHCI_OF_ASPEED) += sdhci-of-aspeed.o
> obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o
> obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
> obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
> diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c
> new file mode 100644
> index 000000000000..8bb095ca2fa9
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-of-aspeed.c
> @@ -0,0 +1,332 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/* Copyright (C) 2019 ASPEED Technology Inc. */
> +/* Copyright (C) 2019 IBM Corp. */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/mmc/host.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/spinlock.h>
> +
> +#include "sdhci-pltfm.h"
> +
> +#define ASPEED_SDC_INFO 0x00
> +#define ASPEED_SDC_S1MMC8 BIT(25)
> +#define ASPEED_SDC_S0MMC8 BIT(24)
> +
> +struct aspeed_sdc {
> + struct clk *clk;
> + struct resource *res;
> +
> + spinlock_t lock;
> + void __iomem *regs;
> +};
> +
> +struct aspeed_sdhci {
> + struct aspeed_sdc *parent;
> + u32 width_mask;
> +};
> +
> +static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc,
> + struct aspeed_sdhci *sdhci,
> + bool bus8)
> +{
> + u32 info;
> +
> + /* Set/clear 8 bit mode */
> + spin_lock(&sdc->lock);
> + info = readl(sdc->regs + ASPEED_SDC_INFO);
> + if (bus8)
> + info |= sdhci->width_mask;
> + else
> + info &= ~sdhci->width_mask;
> + writel(info, sdc->regs + ASPEED_SDC_INFO);
> + spin_unlock(&sdc->lock);
> +}
> +
> +static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
> +{
> + int div;
> + u16 clk;
> +
> + if (clock == host->clock)
> + return;
> +
> + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
> +
> + if (clock == 0)
> + goto out;
> +
> + for (div = 1; div < 256; div *= 2) {
> + if ((host->max_clk / div) <= clock)
> + break;
> + }
> + div >>= 1;
> +
> + clk = div << SDHCI_DIVIDER_SHIFT;
> +
> + sdhci_enable_clk(host, clk);
> +
> +out:
> + host->clock = clock;
> +}
> +
> +static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width)
> +{
> + struct sdhci_pltfm_host *pltfm_priv;
> + struct aspeed_sdhci *aspeed_sdhci;
> + struct aspeed_sdc *aspeed_sdc;
> + u8 ctrl;
> +
> + pltfm_priv = sdhci_priv(host);
> + aspeed_sdhci = sdhci_pltfm_priv(pltfm_priv);
> + aspeed_sdc = aspeed_sdhci->parent;
> +
> + /* Set/clear 8-bit mode */
> + aspeed_sdc_configure_8bit_mode(aspeed_sdc, aspeed_sdhci,
> + width == MMC_BUS_WIDTH_8);
> +
> + /* Set/clear 1 or 4 bit mode */
> + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
> + if (width == MMC_BUS_WIDTH_4)
> + ctrl |= SDHCI_CTRL_4BITBUS;
> + else
> + ctrl &= ~SDHCI_CTRL_4BITBUS;
> + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
> +}
> +
> +static const struct sdhci_ops aspeed_sdhci_ops = {
> + .set_clock = aspeed_sdhci_set_clock,
> + .get_max_clock = sdhci_pltfm_clk_get_max_clock,
> + .set_bus_width = aspeed_sdhci_set_bus_width,
> + .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
> + .reset = sdhci_reset,
> + .set_uhs_signaling = sdhci_set_uhs_signaling,
> +};
> +
> +static const struct sdhci_pltfm_data aspeed_sdhci_pdata = {
> + .ops = &aspeed_sdhci_ops,
> + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> +};
> +
> +static inline int aspeed_sdhci_calculate_slot(struct aspeed_sdhci *dev,
> + struct resource *res)
> +{
> + resource_size_t delta;
> +
> + if (!res || resource_type(res) != IORESOURCE_MEM)
> + return -EINVAL;
> +
> + if (res->start < dev->parent->res->start)
> + return -EINVAL;
> +
> + delta = res->start - dev->parent->res->start;
> + if (delta & (0x100 - 1))
> + return -EINVAL;
> +
> + return (delta / 0x100) - 1;
> +}
> +
> +static int aspeed_sdhci_probe(struct platform_device *pdev)
> +{
> + struct sdhci_pltfm_host *pltfm_host;
> + struct aspeed_sdhci *dev;
> + struct sdhci_host *host;
> + struct resource *res;
> + int slot;
> + int ret;
> +
> + host = sdhci_pltfm_init(pdev, &aspeed_sdhci_pdata, sizeof(*dev));
> + if (IS_ERR(host))
> + return PTR_ERR(host);
> +
> + pltfm_host = sdhci_priv(host);
> + dev = sdhci_pltfm_priv(pltfm_host);
> + dev->parent = dev_get_drvdata(pdev->dev.parent);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + slot = aspeed_sdhci_calculate_slot(dev, res);
> +
> + if (slot < 0)
> + return slot;
> + else if (slot >= 2)
> + return -EINVAL;
> +
> + dev_info(&pdev->dev, "Configuring for slot %d\n", slot);
> + dev->width_mask = !slot ? ASPEED_SDC_S0MMC8 : ASPEED_SDC_S1MMC8;
> +
> + sdhci_get_of_property(pdev);
> +
> + pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(pltfm_host->clk))
> + return PTR_ERR(pltfm_host->clk);
> +
> + ret = clk_prepare_enable(pltfm_host->clk);
> + if (ret) {
> + dev_err(&pdev->dev, "Unable to enable SDIO clock\n");
> + goto err_pltfm_free;
> + }
> +
> + ret = mmc_of_parse(host->mmc);
> + if (ret)
> + goto err_sdhci_add;
> +
> + ret = sdhci_add_host(host);
> + if (ret)
> + goto err_sdhci_add;
> +
> + return 0;
> +
> +err_sdhci_add:
> + clk_disable_unprepare(pltfm_host->clk);
> +err_pltfm_free:
> + sdhci_pltfm_free(pdev);
> + return ret;
> +}
> +
> +static int aspeed_sdhci_remove(struct platform_device *pdev)
> +{
> + struct sdhci_pltfm_host *pltfm_host;
> + struct sdhci_host *host;
> + int dead = 0;
> +
> + host = platform_get_drvdata(pdev);
> + pltfm_host = sdhci_priv(host);
> +
> + sdhci_remove_host(host, dead);
> +
> + clk_disable_unprepare(pltfm_host->clk);
> +
> + sdhci_pltfm_free(pdev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id aspeed_sdhci_of_match[] = {
> + { .compatible = "aspeed,ast2400-sdhci", },
> + { .compatible = "aspeed,ast2500-sdhci", },
> + { .compatible = "aspeed,ast2600-sdhci", },
> + { }
> +};
> +
> +static struct platform_driver aspeed_sdhci_driver = {
> + .driver = {
> + .name = "sdhci-aspeed",
> + .of_match_table = aspeed_sdhci_of_match,
> + },
> + .probe = aspeed_sdhci_probe,
> + .remove = aspeed_sdhci_remove,
> +};
> +
> +static int aspeed_sdc_probe(struct platform_device *pdev)
> +
> +{
> + struct device_node *parent, *child;
> + struct aspeed_sdc *sdc;
> + int ret;
> +
> + sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);
> + if (!sdc)
> + return -ENOMEM;
> +
> + spin_lock_init(&sdc->lock);
> +
> + sdc->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(sdc->clk))
> + return PTR_ERR(sdc->clk);
> +
> + ret = clk_prepare_enable(sdc->clk);
> + if (ret) {
> + dev_err(&pdev->dev, "Unable to enable SDCLK\n");
> + return ret;
> + }
> +
> + sdc->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + sdc->regs = devm_ioremap_resource(&pdev->dev, sdc->res);
> + if (IS_ERR(sdc->regs)) {
> + ret = PTR_ERR(sdc->regs);
> + goto err_clk;
> + }
> +
> + dev_set_drvdata(&pdev->dev, sdc);
> +
> + parent = pdev->dev.of_node;
> + for_each_available_child_of_node(parent, child) {
> + struct platform_device *cpdev;
> +
> + cpdev = of_platform_device_create(child, NULL, &pdev->dev);
> + if (IS_ERR(cpdev)) {
> + of_node_put(child);
> + ret = PTR_ERR(cpdev);
> + goto err_clk;
> + }
> + }
> +
> + return 0;
> +
> +err_clk:
> + clk_disable_unprepare(sdc->clk);
> + return ret;
> +}
> +
> +static int aspeed_sdc_remove(struct platform_device *pdev)
> +{
> + struct aspeed_sdc *sdc = dev_get_drvdata(&pdev->dev);
> +
> + clk_disable_unprepare(sdc->clk);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id aspeed_sdc_of_match[] = {
> + { .compatible = "aspeed,ast2400-sd-controller", },
> + { .compatible = "aspeed,ast2500-sd-controller", },
> + { .compatible = "aspeed,ast2600-sd-controller", },
> + { }
> +};
> +
> +MODULE_DEVICE_TABLE(of, aspeed_sdc_of_match);
> +
> +static struct platform_driver aspeed_sdc_driver = {
> + .driver = {
> + .name = "sd-controller-aspeed",
> + .pm = &sdhci_pltfm_pmops,
> + .of_match_table = aspeed_sdc_of_match,
> + },
> + .probe = aspeed_sdc_probe,
> + .remove = aspeed_sdc_remove,
> +};
> +
> +static int __init aspeed_sdc_init(void)
> +{
> + int rc;
> +
> + rc = platform_driver_register(&aspeed_sdhci_driver);
> + if (rc < 0)
> + return rc;
> +
> + rc = platform_driver_register(&aspeed_sdc_driver);
> + if (rc < 0)
> + platform_driver_unregister(&aspeed_sdhci_driver);
> +
> + return rc;
> +}
> +module_init(aspeed_sdc_init);
> +
> +static void __exit aspeed_sdc_exit(void)
> +{
> + platform_driver_unregister(&aspeed_sdc_driver);
> + platform_driver_unregister(&aspeed_sdhci_driver);
> +}
> +module_exit(aspeed_sdc_exit);
> +
> +MODULE_DESCRIPTION("Driver for the ASPEED SD/SDIO/SDHCI Controllers");
> +MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>");
> +MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>");
> +MODULE_LICENSE("GPL");
> --
> 2.20.1
>
^ permalink raw reply
* [PATCH] drm/aspeed: gfc_crtc: Make structure aspeed_gfx_funcs constant
From: Daniel Vetter @ 2019-08-14 17:27 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190813063355.25549-1-nishkadg.linux@gmail.com>
On Tue, Aug 13, 2019 at 12:03:55PM +0530, Nishka Dasgupta wrote:
> The static structure aspeed_gfx_funcs, of type
> drm_simple_display_pipe_funcs, is used only as an argument to
> drm_simple_display_pipe_init(), which does not modify it. Hence make it
> constant to protect it from unintended modification.
> Issue found with Coccinelle.
>
> Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Applied, thanks for your patch.
> ---
> drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> index 15db9e426ec4..2184b8be6fd4 100644
> --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> @@ -215,7 +215,7 @@ static void aspeed_gfx_disable_vblank(struct drm_simple_display_pipe *pipe)
> writel(reg | CRT_CTRL_VERTICAL_INTR_STS, priv->base + CRT_CTRL1);
> }
>
> -static struct drm_simple_display_pipe_funcs aspeed_gfx_funcs = {
> +static const struct drm_simple_display_pipe_funcs aspeed_gfx_funcs = {
> .enable = aspeed_gfx_pipe_enable,
> .disable = aspeed_gfx_pipe_disable,
> .update = aspeed_gfx_pipe_update,
> --
> 2.19.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply
* [PATCH 3/3] dt-bindings: aspeed: Remove mention of deprecated compatibles
From: Lee Jones @ 2019-08-14 10:54 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <CACRpkdapA_-yp4ihY3S+CHMmDMKU2b0u=sj2UhJ-cvv39Dji_g@mail.gmail.com>
On Wed, 14 Aug 2019, Linus Walleij wrote:
> On Mon, Aug 12, 2019 at 12:15 PM Lee Jones <lee.jones@linaro.org> wrote:
> > On Mon, 05 Aug 2019, Linus Walleij wrote:
> >
> > > On Wed, Jul 24, 2019 at 10:13 AM Andrew Jeffery <andrew@aj.id.au> wrote:
> > >
> > > > Guide readers away from using the aspeed,g[45].* compatible patterns.
> > > >
> > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > >
> > > Patch applied to the pinctrl tree.
> >
> > With my Ack?
>
> Sorry no. :( Was I too trigger-happy?
>
> Usually I take Rob's ACK as authoritative for anything under
> Documentation/devicetree but if you have concerns about the
> patch from an MFD point of view I will revert it pending further
> discussion.
No need. I would have Acked it.
--
Lee Jones [???]
Linaro Services Technical Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 3/3] dt-bindings: aspeed: Remove mention of deprecated compatibles
From: Linus Walleij @ 2019-08-14 8:41 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190812101504.GF26727@dell>
On Mon, Aug 12, 2019 at 12:15 PM Lee Jones <lee.jones@linaro.org> wrote:
> On Mon, 05 Aug 2019, Linus Walleij wrote:
>
> > On Wed, Jul 24, 2019 at 10:13 AM Andrew Jeffery <andrew@aj.id.au> wrote:
> >
> > > Guide readers away from using the aspeed,g[45].* compatible patterns.
> > >
> > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> >
> > Patch applied to the pinctrl tree.
>
> With my Ack?
Sorry no. :( Was I too trigger-happy?
Usually I take Rob's ACK as authoritative for anything under
Documentation/devicetree but if you have concerns about the
patch from an MFD point of view I will revert it pending further
discussion.
Yours,
Linus Walleij
^ permalink raw reply
* [v7 2/2] gpio: aspeed: Add SGPIO driver
From: Linus Walleij @ 2019-08-14 8:09 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1564603297-1391-3-git-send-email-hongweiz@ami.com>
Hi Hongwei,
thanks for your patch!
I have now merged the bindings so you only need to respin
this patch.
On Wed, Jul 31, 2019 at 10:02 PM Hongwei Zhang <hongweiz@ami.com> wrote:
> Add SGPIO driver support for Aspeed AST2500 SoC.
>
> Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
I guess I need to go with this, there are some minor things
I still want to be fixed:
> +static void __aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
I don't like __underscore_functions because their semantic
is ambiguous.
Rename this something like aspeed_sgpio_commit() or
whatever best fits the actual use.
> +static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
> + struct platform_device *pdev)
> +{
(...)
> + rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_sgpio_irqchip,
> + 0, handle_bad_irq, IRQ_TYPE_NONE);
(...)
> + gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_sgpio_irqchip,
> + gpio->irq, aspeed_sgpio_irq_handler);
We do not set up chained irqchips like this anymore, sorry.
I am currently rewriting all existing chained drivers to pass
an initialized irqchip when registering the whole gpio chip.
See drivers/gpio/TODO.
Here are examples:
https://lore.kernel.org/linux-gpio/20190811080539.15647-1-linus.walleij at linaro.org/
https://lore.kernel.org/linux-gpio/20190812132554.18313-1-linus.walleij at linaro.org/
> + /* set all SGPIO pins as input (1). */
> + memset(gpio->dir_in, 0xff, sizeof(gpio->dir_in));
Do the irqchip set-up here, before adding the gpio_chip.
> + rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
> + if (rc < 0)
> + return rc;
> +
> + return aspeed_sgpio_setup_irqs(gpio, pdev);
Yours,
Linus Walleij
^ permalink raw reply
* [v7 1/2] dt-bindings: gpio: aspeed: Add SGPIO support
From: Linus Walleij @ 2019-08-14 7:59 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1564603297-1391-2-git-send-email-hongweiz@ami.com>
On Wed, Jul 31, 2019 at 10:01 PM Hongwei Zhang <hongweiz@ami.com> wrote:
> Add bindings to support SGPIO on AST2400 or AST2500.
>
> Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
OK timeout for further DT binding review. I adjusted a bunch
of things like whitespace and referencing other files when
applying.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v5 1/2] dt-bindings: mmc: Document Aspeed SD controller
From: Rob Herring @ 2019-08-13 22:14 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190807003629.2974-2-andrew@aj.id.au>
On Tue, Aug 6, 2019 at 6:38 PM Andrew Jeffery <andrew@aj.id.au> wrote:
>
> The ASPEED SD/SDIO/MMC controller exposes two slots implementing the
> SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit
> data bus if only a single slot is enabled.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
>
> ---
> v4:
> * Make use of mmc-controller.yaml
> * Document sdhci,auto-cmd12
>
> v2:
> * Fix compatible enums
> * Add AST2600 compatibles
> * Describe #address-cells / #size-cells
> ---
> .../devicetree/bindings/mmc/aspeed,sdhci.yaml | 105 ++++++++++++++++++
> 1 file changed, 105 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox