* [PATCH v2 2/4] vesnin: add secondary SPI flash chip
From: Ivan Mikhaylov @ 2019-08-26 10:46 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190826104636.19324-1-i.mikhaylov@yadro.com>
Adds secondary SPI flash chip into dts for vesnin.
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
index 2ee26c86a32e..db4cc3df61ce 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
@@ -81,6 +81,14 @@
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
+
+ flash at 1 {
+ status = "okay";
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ label = "alt";
+ };
};
&spi {
--
2.20.1
^ permalink raw reply related
* [PATCH v2 1/4] vesnin: add wdt2 section with alt-boot option
From: Ivan Mikhaylov @ 2019-08-26 10:46 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190826104636.19324-1-i.mikhaylov@yadro.com>
Adds wdt2 section with 'alt-boot' option into dts for vesnin.
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
index 0b9e29c3212e..2ee26c86a32e 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
@@ -222,3 +222,7 @@
&vuart {
status = "okay";
};
+
+&wdt2 {
+ aspeed,alt-boot;
+};
--
2.20.1
^ permalink raw reply related
* [PATCH v2 0/4] add dual-boot support
From: Ivan Mikhaylov @ 2019-08-26 10:46 UTC (permalink / raw)
To: linux-aspeed
ASPEED SoCs support dual-boot feature for SPI Flash.
When strapped appropriately, the SoC starts wdt2 (/dev/watchdog1)
and if within a minute it is not disabled, it goes off and reboots
the SoC from an alternate SPI Flash chip by changing CS0 controls
to actually drive CS1 line.
When booted from alternate chip, in order to access the main chip
at CS0, the user must reset the appropriate bit in the watchdog
hardware. There is no interface that would allow to do that from
an embedded firmware startup script.
This commit implements support for that feature:
* Enable 'alt-boot' option for wdt2
* Enable secondary SPI flash chip
* Make it possible to get access to the primary SPI flash chip at CS0
after booting from the alternate chip at CS1. A sysfs interface is added
to provide an easy way for embedded firmware startup scripts to clear
the chip select bit to gain access to the primary flash chip in order
to allow for recovery of its contents.
Ivan Mikhaylov (4):
vesnin: add wdt2 section with alt-boot option
vesnin: add secondary SPI flash chip
watchdog/aspeed: add support for dual boot
dt-bindings/watchdog: Add access_cs0 option for alt-boot
.../bindings/watchdog/aspeed-wdt.txt | 7 +++
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 12 ++++
drivers/watchdog/aspeed_wdt.c | 62 ++++++++++++++++++-
3 files changed, 80 insertions(+), 1 deletion(-)
--
2.20.1
^ permalink raw reply
* Re: [PATCH] media: aspeed: fix an incorrect return code on buffer allocation failure
From: Andrew Jeffery @ 2019-08-26 2:50 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <588f6cbd-b6ca-4f43-8034-80956ee56bb8@www.fastmail.com>
On Mon, 26 Aug 2019, at 11:02, Andrew Jeffery wrote:
>
>
> On Sat, 24 Aug 2019, at 07:00, Jae Hyun Yoo wrote:
> > It returns '0' even when a failure happens on jpeg buffer allocation
> > so this commit fixes the issue.
> >
> > Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Keep my Reviewed-by, but can you please do a v2 that adds a Fixes: tag
and also Cc stable with the patch?
Cheers,
Andrew
^ permalink raw reply
* [PATCH] dt-bindings: mmc: aspeed: Update example ranges property
From: Andrew Jeffery @ 2019-08-26 2:16 UTC (permalink / raw)
To: linux-aspeed
The example node in the binding uses the AST2500 compatible string for
the SD controller with a 64kiB ranges property, but the SD controller is
allocated 128kiB of MMIO space according to the AST2500 datasheet. Fix
the example to correctly reflect the hardware in the AST2500, however it
should be noted that the MMIO region is reduced to 64kiB in the AST2600
where a second SD controller block has been introduced into the address
space.
Also add the IBM copyright header that I left out of the initial patch.
Suggested-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
Hi Ulf, this is the follow-up fix as discussed here:
http://patchwork.ozlabs.org/patch/1143090/
Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml b/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
index 570f8c72662b..200de9396036 100644
--- a/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright 2019 IBM Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
@@ -84,7 +85,7 @@ examples:
reg = <0x1e740000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x1e740000 0x10000>;
+ ranges = <0 0x1e740000 0x20000>;
clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
sdhci0: sdhci at 100 {
--
2.20.1
^ permalink raw reply related
* Re: [PATCH] media: aspeed: fix an incorrect return code on buffer allocation failure
From: Andrew Jeffery @ 2019-08-26 1:32 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190823212957.26043-1-jae.hyun.yoo@linux.intel.com>
On Sat, 24 Aug 2019, at 07:00, Jae Hyun Yoo wrote:
> It returns '0' even when a failure happens on jpeg buffer allocation
> so this commit fixes the issue.
>
> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> drivers/media/platform/aspeed-video.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/media/platform/aspeed-video.c
> b/drivers/media/platform/aspeed-video.c
> index f899ac3b4a61..94f97d96dabc 100644
> --- a/drivers/media/platform/aspeed-video.c
> +++ b/drivers/media/platform/aspeed-video.c
> @@ -1624,6 +1624,7 @@ static int aspeed_video_init(struct aspeed_video
> *video)
> if (!aspeed_video_alloc_buf(video, &video->jpeg,
> VE_JPEG_HEADER_SIZE)) {
> dev_err(dev, "Failed to allocate DMA for JPEG header\n");
> + rc = -ENOMEM;
> goto err_release_reserved_mem;
> }
>
> --
> 2.7.4
>
>
^ permalink raw reply
* [PATCH v2 2/2] clk: Add support for AST2600 SoC
From: Joel Stanley @ 2019-08-25 14:18 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190825141848.17346-1-joel@jms.id.au>
The ast2600 is a new BMC SoC from ASPEED. It contains many more clocks
than the previous iterations, so support is broken out into it's own
driver.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v2:
- Make headers standalone
- Rename lock so it doesn't alias with clk-aspeed's lock
- Document critical clocks, remove undocumented ones
- Fix style issues with braces
- Fix comment style
- Remove unnecessary braces in header licence statement
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-ast2600.c | 704 ++++++++++++++++++++++
include/dt-bindings/clock/ast2600-clock.h | 113 ++++
3 files changed, 818 insertions(+)
create mode 100644 drivers/clk/clk-ast2600.c
create mode 100644 include/dt-bindings/clock/ast2600-clock.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0cad76021297..0138fb14e6f8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
+obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
new file mode 100644
index 000000000000..5f065ab46cef
--- /dev/null
+++ b/drivers/clk/clk-ast2600.c
@@ -0,0 +1,704 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright IBM Corp
+// Copyright ASPEED Technology
+
+#define pr_fmt(fmt) "clk-ast2600: " fmt
+
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/ast2600-clock.h>
+
+#include "clk-aspeed.h"
+
+#define ASPEED_G6_NUM_CLKS 67
+
+#define ASPEED_G6_SILICON_REV 0x004
+
+#define ASPEED_G6_RESET_CTRL 0x040
+#define ASPEED_G6_RESET_CTRL2 0x050
+
+#define ASPEED_G6_CLK_STOP_CTRL 0x080
+#define ASPEED_G6_CLK_STOP_CTRL2 0x090
+
+#define ASPEED_G6_MISC_CTRL 0x0C0
+#define UART_DIV13_EN BIT(12)
+
+#define ASPEED_G6_CLK_SELECTION1 0x300
+#define ASPEED_G6_CLK_SELECTION2 0x304
+#define ASPEED_G6_CLK_SELECTION4 0x310
+
+#define ASPEED_HPLL_PARAM 0x200
+#define ASPEED_APLL_PARAM 0x210
+#define ASPEED_MPLL_PARAM 0x220
+#define ASPEED_EPLL_PARAM 0x240
+#define ASPEED_DPLL_PARAM 0x260
+
+#define ASPEED_G6_STRAP1 0x500
+
+/* Globally visible clocks */
+static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
+
+/* Keeps track of all clocks */
+static struct clk_hw_onecell_data *aspeed_g6_clk_data;
+
+static void __iomem *scu_g6_base;
+
+/*
+ * Clocks marked with CLK_IS_CRITICAL:
+ *
+ * ref0 and ref1 are essential for the SoC to operate
+ * mpll is required if SDRAM is used
+ */
+static const struct aspeed_gate_data aspeed_g6_gates[] = {
+ /* clk rst name parent flags */
+ [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
+ [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
+ [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
+ /* vclk parent - dclk/d1clk/hclk/mclk */
+ [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
+ [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
+ /* From dpll */
+ [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
+ [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL },
+ [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
+ /* Reserved 8 */
+ [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
+ /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
+ [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */
+ /* Reserved 11/12 */
+ [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
+ [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
+ [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
+ /* Reserved 16/19 */
+ [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */
+ [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */
+ /* Reserved 22/23 */
+ [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */
+ [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */
+ /* Reserved 26 */
+ [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */
+ /* Reserved 28/29/30 */
+ [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */
+ [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
+ [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL },
+ /* Reserved 35 */
+ [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
+ [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
+ /* Reserved 38 RSA: no longer used */
+ /* Reserved 39 */
+ [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */
+ [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */
+ [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */
+ [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */
+ [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */
+ [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */
+ [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */
+ [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */
+ [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
+ [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
+ [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
+ [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
+ [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */
+ [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */
+ [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */
+ [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */
+ [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */
+ [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */
+ [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */
+ [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */
+ [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */
+ [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */
+ [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */
+};
+
+static const char * const eclk_parent_names[] = { "mpll", "hpll", "dpll" };
+
+static const struct clk_div_table ast2600_eclk_div_table[] = {
+ { 0x0, 2 },
+ { 0x1, 2 },
+ { 0x2, 3 },
+ { 0x3, 4 },
+ { 0x4, 5 },
+ { 0x5, 6 },
+ { 0x6, 7 },
+ { 0x7, 8 },
+ { 0 }
+};
+
+static const struct clk_div_table ast2600_mac_div_table[] = {
+ { 0x0, 4 },
+ { 0x1, 4 },
+ { 0x2, 6 },
+ { 0x3, 8 },
+ { 0x4, 10 },
+ { 0x5, 12 },
+ { 0x6, 14 },
+ { 0x7, 16 },
+ { 0 }
+};
+
+static const struct clk_div_table ast2600_div_table[] = {
+ { 0x0, 4 },
+ { 0x1, 8 },
+ { 0x2, 12 },
+ { 0x3, 16 },
+ { 0x4, 20 },
+ { 0x5, 24 },
+ { 0x6, 28 },
+ { 0x7, 32 },
+ { 0 }
+};
+
+/* For hpll/dpll/epll/mpll */
+static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
+{
+ unsigned int mult, div;
+
+ if (val & BIT(24)) {
+ /* Pass through mode */
+ mult = div = 1;
+ } else {
+ /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
+ u32 m = val & 0x1fff;
+ u32 n = (val >> 13) & 0x3f;
+ u32 p = (val >> 19) & 0xf;
+ mult = (m + 1) / (n + 1);
+ div = (p + 1);
+ }
+ return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
+ mult, div);
+};
+
+static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
+{
+ unsigned int mult, div;
+
+ if (val & BIT(20)) {
+ /* Pass through mode */
+ mult = div = 1;
+ } else {
+ /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
+ u32 m = (val >> 5) & 0x3f;
+ u32 od = (val >> 4) & 0x1;
+ u32 n = val & 0xf;
+
+ mult = (2 - od) * (m + 2);
+ div = n + 1;
+ }
+ return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
+ mult, div);
+};
+
+static u32 get_bit(u8 idx)
+{
+ return BIT(idx % 32);
+}
+
+static u32 get_reset_reg(struct aspeed_clk_gate *gate)
+{
+ if (gate->reset_idx < 32)
+ return ASPEED_G6_RESET_CTRL;
+
+ return ASPEED_G6_RESET_CTRL2;
+}
+
+static u32 get_clock_reg(struct aspeed_clk_gate *gate)
+{
+ if (gate->clock_idx < 32)
+ return ASPEED_G6_CLK_STOP_CTRL;
+
+ return ASPEED_G6_CLK_STOP_CTRL2;
+}
+
+static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
+{
+ struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
+ u32 clk = get_bit(gate->clock_idx);
+ u32 rst = get_bit(gate->reset_idx);
+ u32 reg;
+ u32 enval;
+
+ /*
+ * If the IP is in reset, treat the clock as not enabled,
+ * this happens with some clocks such as the USB one when
+ * coming from cold reset. Without this, aspeed_clk_enable()
+ * will fail to lift the reset.
+ */
+ if (gate->reset_idx >= 0) {
+ regmap_read(gate->map, get_reset_reg(gate), ®);
+
+ if (reg & rst)
+ return 0;
+ }
+
+ regmap_read(gate->map, get_clock_reg(gate), ®);
+
+ enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
+
+ return ((reg & clk) == enval) ? 1 : 0;
+}
+
+static int aspeed_g6_clk_enable(struct clk_hw *hw)
+{
+ struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
+ unsigned long flags;
+ u32 clk = get_bit(gate->clock_idx);
+ u32 rst = get_bit(gate->reset_idx);
+
+ spin_lock_irqsave(gate->lock, flags);
+
+ if (aspeed_g6_clk_is_enabled(hw)) {
+ spin_unlock_irqrestore(gate->lock, flags);
+ return 0;
+ }
+
+ if (gate->reset_idx >= 0) {
+ /* Put IP in reset */
+ regmap_write(gate->map, get_reset_reg(gate), rst);
+ /* Delay 100us */
+ udelay(100);
+ }
+
+ /* Enable clock */
+ if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
+ regmap_write(gate->map, get_clock_reg(gate), clk);
+ } else {
+ /* Use set to clear register */
+ regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
+ }
+
+ if (gate->reset_idx >= 0) {
+ /* A delay of 10ms is specified by the ASPEED docs */
+ mdelay(10);
+ /* Take IP out of reset */
+ regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
+ }
+
+ spin_unlock_irqrestore(gate->lock, flags);
+
+ return 0;
+}
+
+static void aspeed_g6_clk_disable(struct clk_hw *hw)
+{
+ struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
+ unsigned long flags;
+ u32 clk = get_bit(gate->clock_idx);
+
+ spin_lock_irqsave(gate->lock, flags);
+
+ if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
+ regmap_write(gate->map, get_clock_reg(gate), clk);
+ } else {
+ /* Use set to clear register */
+ regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
+ }
+
+ spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static const struct clk_ops aspeed_g6_clk_gate_ops = {
+ .enable = aspeed_g6_clk_enable,
+ .disable = aspeed_g6_clk_disable,
+ .is_enabled = aspeed_g6_clk_is_enabled,
+};
+
+static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct aspeed_reset *ar = to_aspeed_reset(rcdev);
+ u32 rst = get_bit(id);
+ u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
+
+ /* Use set to clear register */
+ return regmap_write(ar->map, reg + 0x04, rst);
+}
+
+static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct aspeed_reset *ar = to_aspeed_reset(rcdev);
+ u32 rst = get_bit(id);
+ u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
+
+ return regmap_write(ar->map, reg, rst);
+}
+
+static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct aspeed_reset *ar = to_aspeed_reset(rcdev);
+ int ret;
+ u32 val;
+ u32 rst = get_bit(id);
+ u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
+
+ ret = regmap_read(ar->map, reg, &val);
+ if (ret)
+ return ret;
+
+ return !!(val & rst);
+}
+
+static const struct reset_control_ops aspeed_g6_reset_ops = {
+ .assert = aspeed_g6_reset_assert,
+ .deassert = aspeed_g6_reset_deassert,
+ .status = aspeed_g6_reset_status,
+};
+
+static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
+ const char *name, const char *parent_name, unsigned long flags,
+ struct regmap *map, u8 clock_idx, u8 reset_idx,
+ u8 clk_gate_flags, spinlock_t *lock)
+{
+ struct aspeed_clk_gate *gate;
+ struct clk_init_data init;
+ struct clk_hw *hw;
+ int ret;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &aspeed_g6_clk_gate_ops;
+ init.flags = flags;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+
+ gate->map = map;
+ gate->clock_idx = clock_idx;
+ gate->reset_idx = reset_idx;
+ gate->flags = clk_gate_flags;
+ gate->lock = lock;
+ gate->hw.init = &init;
+
+ hw = &gate->hw;
+ ret = clk_hw_register(dev, hw);
+ if (ret) {
+ kfree(gate);
+ hw = ERR_PTR(ret);
+ }
+
+ return hw;
+}
+
+static const char * const vclk_parent_names[] = {
+ "dpll",
+ "d1pll",
+ "hclk",
+ "mclk",
+};
+
+static const char * const d1clk_parent_names[] = {
+ "dpll",
+ "epll",
+ "usb-phy-40m",
+ "gpioc6_clkin",
+ "dp_phy_pll",
+};
+
+static int aspeed_g6_clk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct aspeed_reset *ar;
+ struct regmap *map;
+ struct clk_hw *hw;
+ u32 val, rate;
+ int i, ret;
+
+ map = syscon_node_to_regmap(dev->of_node);
+ if (IS_ERR(map)) {
+ dev_err(dev, "no syscon regmap\n");
+ return PTR_ERR(map);
+ }
+
+ ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
+ if (!ar)
+ return -ENOMEM;
+
+ ar->map = map;
+
+ ar->rcdev.owner = THIS_MODULE;
+ ar->rcdev.nr_resets = 64;
+ ar->rcdev.ops = &aspeed_g6_reset_ops;
+ ar->rcdev.of_node = dev->of_node;
+
+ ret = devm_reset_controller_register(dev, &ar->rcdev);
+ if (ret) {
+ dev_err(dev, "could not register reset controller\n");
+ return ret;
+ }
+
+ /* UART clock div13 setting */
+ regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
+ if (val & UART_DIV13_EN)
+ rate = 24000000 / 13;
+ else
+ rate = 24000000;
+ hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
+
+ /* UART6~13 clock div13 setting */
+ regmap_read(map, 0x80, &val);
+ if (val & BIT(31))
+ rate = 24000000 / 13;
+ else
+ rate = 24000000;
+ hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
+
+ /* EMMC ext clock divider */
+ hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0,
+ ast2600_div_table,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
+
+ /* SD/SDIO clock divider and gate */
+ hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
+ 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
+ ast2600_div_table,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
+
+ /* MAC1/2 AHB bus clock divider */
+ hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
+ ast2600_mac_div_table,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
+
+ /* MAC3/4 AHB bus clock divider */
+ hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
+ scu_g6_base + 0x310, 24, 3, 0,
+ ast2600_mac_div_table,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
+
+ /* LPC Host (LHCLK) clock divider */
+ hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
+ ast2600_div_table,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
+
+ /* gfx d1clk : use dp clk */
+ regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
+ /* SoC Display clock selection */
+ hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
+ ARRAY_SIZE(d1clk_parent_names), 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
+
+ /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */
+ regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
+
+ /* P-Bus (BCLK) clock divider */
+ hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
+ ast2600_div_table,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
+
+ /* Video Capture clock selection */
+ hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
+ ARRAY_SIZE(vclk_parent_names), 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
+
+ /* Video Engine clock divider */
+ hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
+ scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
+ ast2600_eclk_div_table,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
+ const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
+ u32 gate_flags;
+
+ /*
+ * Special case: the USB port 1 clock (bit 14) is always
+ * working the opposite way from the other ones.
+ */
+ gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
+ hw = aspeed_g6_clk_hw_register_gate(dev,
+ gd->name,
+ gd->parent_name,
+ gd->flags,
+ map,
+ gd->clock_idx,
+ gd->reset_idx,
+ gate_flags,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[i] = hw;
+ }
+
+ return 0;
+};
+
+static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
+ { .compatible = "aspeed,ast2600-scu" },
+ { }
+};
+
+static struct platform_driver aspeed_g6_clk_driver = {
+ .probe = aspeed_g6_clk_probe,
+ .driver = {
+ .name = "ast2600-clk",
+ .of_match_table = aspeed_g6_clk_dt_ids,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver(aspeed_g6_clk_driver);
+
+static u32 ast2600_a0_axi_ahb_div_table[] = {
+ 2, 2, 3, 5,
+};
+
+static u32 ast2600_a1_axi_ahb_div_table[] = {
+ 4, 6, 2, 4,
+};
+
+static void __init aspeed_g6_cc(struct regmap *map)
+{
+ struct clk_hw *hw;
+ u32 val, div, chip_id, axi_div, ahb_div;
+
+ clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
+
+ /*
+ * High-speed PLL clock derived from the crystal. This the CPU clock,
+ * and we assume that it is enabled
+ */
+ regmap_read(map, ASPEED_HPLL_PARAM, &val);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
+
+ regmap_read(map, ASPEED_MPLL_PARAM, &val);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
+
+ regmap_read(map, ASPEED_DPLL_PARAM, &val);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
+
+ regmap_read(map, ASPEED_EPLL_PARAM, &val);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
+
+ regmap_read(map, ASPEED_APLL_PARAM, &val);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
+
+ /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
+ regmap_read(map, ASPEED_G6_STRAP1, &val);
+ if (val & BIT(16))
+ axi_div = 1;
+ else
+ axi_div = 2;
+
+ regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
+ if (chip_id & BIT(16))
+ ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];
+ else
+ ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
+
+ hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
+
+ regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
+ val = (val >> 23) & 0x7;
+ div = 4 * (val + 1);
+ hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
+
+ regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
+ val = (val >> 9) & 0x7;
+ div = 2 * (val + 1);
+ hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
+
+ /* USB 2.0 port1 phy 40MHz clock */
+ hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
+};
+
+static void __init aspeed_g6_cc_init(struct device_node *np)
+{
+ struct regmap *map;
+ int ret;
+ int i;
+
+ scu_g6_base = of_iomap(np, 0);
+ if (!scu_g6_base)
+ return;
+
+ aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
+ ASPEED_G6_NUM_CLKS), GFP_KERNEL);
+ if (!aspeed_g6_clk_data)
+ return;
+
+ /*
+ * This way all clocks fetched before the platform device probes,
+ * except those we assign here for early use, will be deferred.
+ */
+ for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
+ aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
+
+ /*
+ * We check that the regmap works on this very first access,
+ * but as this is an MMIO-backed regmap, subsequent regmap
+ * access is not going to fail and we skip error checks from
+ * this point.
+ */
+ map = syscon_node_to_regmap(np);
+ if (IS_ERR(map)) {
+ pr_err("no syscon regmap\n");
+ return;
+ }
+
+ aspeed_g6_cc(map);
+ aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
+ ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
+ if (ret)
+ pr_err("failed to add DT provider: %d\n", ret);
+};
+CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
new file mode 100644
index 000000000000..38074a5f7296
--- /dev/null
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
+#ifndef DT_BINDINGS_AST2600_CLOCK_H
+#define DT_BINDINGS_AST2600_CLOCK_H
+
+#define ASPEED_CLK_GATE_ECLK 0
+#define ASPEED_CLK_GATE_GCLK 1
+
+#define ASPEED_CLK_GATE_MCLK 2
+
+#define ASPEED_CLK_GATE_VCLK 3
+#define ASPEED_CLK_GATE_BCLK 4
+#define ASPEED_CLK_GATE_DCLK 5
+
+#define ASPEED_CLK_GATE_LCLK 6
+#define ASPEED_CLK_GATE_LHCCLK 7
+
+#define ASPEED_CLK_GATE_D1CLK 8
+#define ASPEED_CLK_GATE_YCLK 9
+
+#define ASPEED_CLK_GATE_REF0CLK 10
+#define ASPEED_CLK_GATE_REF1CLK 11
+
+#define ASPEED_CLK_GATE_ESPICLK 12
+
+#define ASPEED_CLK_GATE_USBUHCICLK 13
+#define ASPEED_CLK_GATE_USBPORT1CLK 14
+#define ASPEED_CLK_GATE_USBPORT2CLK 15
+
+#define ASPEED_CLK_GATE_RSACLK 16
+#define ASPEED_CLK_GATE_RVASCLK 17
+
+#define ASPEED_CLK_GATE_MAC1CLK 18
+#define ASPEED_CLK_GATE_MAC2CLK 19
+#define ASPEED_CLK_GATE_MAC3CLK 20
+#define ASPEED_CLK_GATE_MAC4CLK 21
+
+#define ASPEED_CLK_GATE_UART1CLK 22
+#define ASPEED_CLK_GATE_UART2CLK 23
+#define ASPEED_CLK_GATE_UART3CLK 24
+#define ASPEED_CLK_GATE_UART4CLK 25
+#define ASPEED_CLK_GATE_UART5CLK 26
+#define ASPEED_CLK_GATE_UART6CLK 27
+#define ASPEED_CLK_GATE_UART7CLK 28
+#define ASPEED_CLK_GATE_UART8CLK 29
+#define ASPEED_CLK_GATE_UART9CLK 30
+#define ASPEED_CLK_GATE_UART10CLK 31
+#define ASPEED_CLK_GATE_UART11CLK 32
+#define ASPEED_CLK_GATE_UART12CLK 33
+#define ASPEED_CLK_GATE_UART13CLK 34
+
+#define ASPEED_CLK_GATE_SDCLK 35
+#define ASPEED_CLK_GATE_EMMCCLK 36
+
+#define ASPEED_CLK_GATE_I3C0CLK 37
+#define ASPEED_CLK_GATE_I3C1CLK 38
+#define ASPEED_CLK_GATE_I3C2CLK 39
+#define ASPEED_CLK_GATE_I3C3CLK 40
+#define ASPEED_CLK_GATE_I3C4CLK 41
+#define ASPEED_CLK_GATE_I3C5CLK 42
+#define ASPEED_CLK_GATE_I3C6CLK 43
+#define ASPEED_CLK_GATE_I3C7CLK 44
+
+#define ASPEED_CLK_GATE_FSICLK 45
+
+#define ASPEED_CLK_HPLL 46
+#define ASPEED_CLK_MPLL 47
+#define ASPEED_CLK_DPLL 48
+#define ASPEED_CLK_EPLL 49
+#define ASPEED_CLK_APLL 50
+#define ASPEED_CLK_AHB 51
+#define ASPEED_CLK_APB1 52
+#define ASPEED_CLK_APB2 53
+#define ASPEED_CLK_BCLK 54
+#define ASPEED_CLK_D1CLK 55
+#define ASPEED_CLK_VCLK 56
+#define ASPEED_CLK_LHCLK 57
+#define ASPEED_CLK_UART 58
+#define ASPEED_CLK_UARTX 59
+#define ASPEED_CLK_SDIO 60
+#define ASPEED_CLK_EMMC 61
+#define ASPEED_CLK_ECLK 62
+#define ASPEED_CLK_ECLK_MUX 63
+#define ASPEED_CLK_MAC12 64
+#define ASPEED_CLK_MAC34 65
+#define ASPEED_CLK_USBPHY_40M 66
+
+/* Only list resets here that are not part of a gate */
+#define ASPEED_RESET_ADC 55
+#define ASPEED_RESET_JTAG_MASTER2 54
+#define ASPEED_RESET_I3C_DMA 39
+#define ASPEED_RESET_PWM 37
+#define ASPEED_RESET_PECI 36
+#define ASPEED_RESET_MII 35
+#define ASPEED_RESET_I2C 34
+#define ASPEED_RESET_H2X 31
+#define ASPEED_RESET_GP_MCU 30
+#define ASPEED_RESET_DP_MCU 29
+#define ASPEED_RESET_DP 28
+#define ASPEED_RESET_RC_XDMA 27
+#define ASPEED_RESET_GRAPHICS 26
+#define ASPEED_RESET_DEV_XDMA 25
+#define ASPEED_RESET_DEV_MCTP 24
+#define ASPEED_RESET_RC_MCTP 23
+#define ASPEED_RESET_JTAG_MASTER 22
+#define ASPEED_RESET_PCIE_DEV_O 21
+#define ASPEED_RESET_PCIE_DEV_OEN 20
+#define ASPEED_RESET_PCIE_RC_O 19
+#define ASPEED_RESET_PCIE_RC_OEN 18
+#define ASPEED_RESET_PCI_DP 5
+#define ASPEED_RESET_AHB 1
+#define ASPEED_RESET_SDRAM 0
+
+#endif
--
2.23.0.rc1
^ permalink raw reply related
* [PATCH v2 1/2] clk: aspeed: Move structures to header
From: Joel Stanley @ 2019-08-25 14:18 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190825141848.17346-1-joel@jms.id.au>
They will be reused by the ast2600 driver.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v2:
include required headers for structures used by clk-aspeed.h
drivers/clk/clk-aspeed.c | 67 ++------------------------------
drivers/clk/clk-aspeed.h | 82 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 85 insertions(+), 64 deletions(-)
create mode 100644 drivers/clk/clk-aspeed.h
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
index 898291501f45..abf06fb6453e 100644
--- a/drivers/clk/clk-aspeed.c
+++ b/drivers/clk/clk-aspeed.c
@@ -1,19 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+
+// Copyright IBM Corp
#define pr_fmt(fmt) "clk-aspeed: " fmt
-#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
-#include <linux/reset-controller.h>
#include <linux/slab.h>
-#include <linux/spinlock.h>
#include <dt-bindings/clock/aspeed-clock.h>
+#include "clk-aspeed.h"
+
#define ASPEED_NUM_CLKS 36
#define ASPEED_RESET2_OFFSET 32
@@ -42,48 +42,6 @@ static struct clk_hw_onecell_data *aspeed_clk_data;
static void __iomem *scu_base;
-/**
- * struct aspeed_gate_data - Aspeed gated clocks
- * @clock_idx: bit used to gate this clock in the clock register
- * @reset_idx: bit used to reset this IP in the reset register. -1 if no
- * reset is required when enabling the clock
- * @name: the clock name
- * @parent_name: the name of the parent clock
- * @flags: standard clock framework flags
- */
-struct aspeed_gate_data {
- u8 clock_idx;
- s8 reset_idx;
- const char *name;
- const char *parent_name;
- unsigned long flags;
-};
-
-/**
- * struct aspeed_clk_gate - Aspeed specific clk_gate structure
- * @hw: handle between common and hardware-specific interfaces
- * @reg: register controlling gate
- * @clock_idx: bit used to gate this clock in the clock register
- * @reset_idx: bit used to reset this IP in the reset register. -1 if no
- * reset is required when enabling the clock
- * @flags: hardware-specific flags
- * @lock: register lock
- *
- * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
- * This modified version of clk_gate allows an optional reset bit to be
- * specified.
- */
-struct aspeed_clk_gate {
- struct clk_hw hw;
- struct regmap *map;
- u8 clock_idx;
- s8 reset_idx;
- u8 flags;
- spinlock_t *lock;
-};
-
-#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
-
/* TODO: ask Aspeed about the actual parent data */
static const struct aspeed_gate_data aspeed_gates[] = {
/* clk rst name parent flags */
@@ -208,13 +166,6 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
mult, div);
}
-struct aspeed_clk_soc_data {
- const struct clk_div_table *div_table;
- const struct clk_div_table *eclk_div_table;
- const struct clk_div_table *mac_div_table;
- struct clk_hw *(*calc_pll)(const char *name, u32 val);
-};
-
static const struct aspeed_clk_soc_data ast2500_data = {
.div_table = ast2500_div_table,
.eclk_div_table = ast2500_eclk_div_table,
@@ -315,18 +266,6 @@ static const struct clk_ops aspeed_clk_gate_ops = {
.is_enabled = aspeed_clk_is_enabled,
};
-/**
- * struct aspeed_reset - Aspeed reset controller
- * @map: regmap to access the containing system controller
- * @rcdev: reset controller device
- */
-struct aspeed_reset {
- struct regmap *map;
- struct reset_controller_dev rcdev;
-};
-
-#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
-
static const u8 aspeed_resets[] = {
/* SCU04 resets */
[ASPEED_RESET_XDMA] = 25,
diff --git a/drivers/clk/clk-aspeed.h b/drivers/clk/clk-aspeed.h
new file mode 100644
index 000000000000..5296b15b1c88
--- /dev/null
+++ b/drivers/clk/clk-aspeed.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Structures used by ASPEED clock drivers
+ *
+ * Copyright 2019 IBM Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/reset-controller.h>
+#include <linux/spinlock.h>
+
+struct clk_div_table;
+struct regmap;
+
+/**
+ * struct aspeed_gate_data - Aspeed gated clocks
+ * @clock_idx: bit used to gate this clock in the clock register
+ * @reset_idx: bit used to reset this IP in the reset register. -1 if no
+ * reset is required when enabling the clock
+ * @name: the clock name
+ * @parent_name: the name of the parent clock
+ * @flags: standard clock framework flags
+ */
+struct aspeed_gate_data {
+ u8 clock_idx;
+ s8 reset_idx;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+};
+
+/**
+ * struct aspeed_clk_gate - Aspeed specific clk_gate structure
+ * @hw: handle between common and hardware-specific interfaces
+ * @reg: register controlling gate
+ * @clock_idx: bit used to gate this clock in the clock register
+ * @reset_idx: bit used to reset this IP in the reset register. -1 if no
+ * reset is required when enabling the clock
+ * @flags: hardware-specific flags
+ * @lock: register lock
+ *
+ * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
+ * This modified version of clk_gate allows an optional reset bit to be
+ * specified.
+ */
+struct aspeed_clk_gate {
+ struct clk_hw hw;
+ struct regmap *map;
+ u8 clock_idx;
+ s8 reset_idx;
+ u8 flags;
+ spinlock_t *lock;
+};
+
+#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
+
+/**
+ * struct aspeed_reset - Aspeed reset controller
+ * @map: regmap to access the containing system controller
+ * @rcdev: reset controller device
+ */
+struct aspeed_reset {
+ struct regmap *map;
+ struct reset_controller_dev rcdev;
+};
+
+#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
+
+/**
+ * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information
+ * @div_table: Common divider lookup table
+ * @eclk_div_table: Divider lookup table for ECLK
+ * @mac_div_table: Divider lookup table for MAC (Ethernet) clocks
+ * @calc_pll: Callback to maculate common PLL settings
+ */
+struct aspeed_clk_soc_data {
+ const struct clk_div_table *div_table;
+ const struct clk_div_table *eclk_div_table;
+ const struct clk_div_table *mac_div_table;
+ struct clk_hw *(*calc_pll)(const char *name, u32 val);
+};
--
2.23.0.rc1
^ permalink raw reply related
* [PATCH v2 0/2] clk: Add driver for ast2600
From: Joel Stanley @ 2019-08-25 14:18 UTC (permalink / raw)
To: linux-aspeed
Hello clock maintainers,
v2 of the clock driver addresses most review comments from Stephen, and
contains a few fixes found while testing on hardware.
Stephen, I did not get a chance to move to the new parent registration scheme.
If you would be comfortable with taking these patches for 5.4 I can work
on to moving to the new parent scheme next merge window, for both the
ast2600 and the existing driver.
Joel Stanley (2):
clk: aspeed: Move structures to header
clk: Add support for AST2600 SoC
drivers/clk/Makefile | 1 +
drivers/clk/clk-aspeed.c | 67 +-
drivers/clk/clk-aspeed.h | 82 +++
drivers/clk/clk-ast2600.c | 704 ++++++++++++++++++++++
include/dt-bindings/clock/ast2600-clock.h | 113 ++++
5 files changed, 903 insertions(+), 64 deletions(-)
create mode 100644 drivers/clk/clk-aspeed.h
create mode 100644 drivers/clk/clk-ast2600.c
create mode 100644 include/dt-bindings/clock/ast2600-clock.h
--
2.23.0.rc1
^ permalink raw reply
* [GIT PULL] ARM: aspeed: defconfig changes for 5.4
From: Joel Stanley @ 2019-08-25 14:10 UTC (permalink / raw)
To: linux-aspeed
Hello ARM Maintainers,
Some bits and pieces for the defconfigs. The multi_v7 one applies to
linux-next with a bit of fuzz, but let us know if you run in to any
issues. I'll be away for this week, but Andrew will be on hand to help
out.
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git \
tags/aspeed-5.4-defconfig
for you to fetch changes up to 4cdabee7d6d2e439fea726a101e448c4ca6837f4:
ARM: configs: aspeed_g5: Enable AST2600 (2019-08-25 23:22:54 +0930)
----------------------------------------------------------------
ASPEED defconfig updates for 5.4
- Enable the new AST2600 in multi_v7 and the aspeed_g5 configs.
- Regenerate defconfigs to drop old options
- Clean up network options
----------------------------------------------------------------
Joel Stanley (3):
ARM: configs: aspeed: Refresh defconfigs
ARM: configs: multi_v7: Add ASPEED G6
ARM: configs: aspeed_g5: Enable AST2600
William A. Kennington III (1):
ARM: configs: aspeed: Enable commonly used network functionality
arch/arm/configs/aspeed_g4_defconfig | 50 +++++++++++---------------
arch/arm/configs/aspeed_g5_defconfig | 68 ++++++++++++++++++++----------------
arch/arm/configs/multi_v7_defconfig | 19 ++++++++++
3 files changed, 78 insertions(+), 59 deletions(-)
^ permalink raw reply
* [GIT PULL] ARM: aspeed: devicetree changes for 5.4
From: Joel Stanley @ 2019-08-25 14:10 UTC (permalink / raw)
To: linux-aspeed
Hello ARM Maintainers,
Here are the APSEED device tree changes. No ast2600 support here
unfortunately as the clock driver wasn't quite ready in time.
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git \
tags/aspeed-5.4-devicetree
for you to fetch changes up to 49b0f3be0b86292eed6f6aedadf4252131d9c111:
ARM: dts: aspeed: swift: Add eMMC device (2019-08-22 15:34:20 +0930)
----------------------------------------------------------------
ASPEED device tree updates for 5.4
New machines:
- Facebook Wedge100, Wedge40 and Minipack
- Lenovo Hr855xg2
- Wistron Mihawk
There's a few other updates, notably some changes to to use the newly
added SDHCI driver.
----------------------------------------------------------------
Andrew Jeffery (2):
ARM: dts: aspeed: Describe SD controllers
ARM: dts: aspeed: Enable first MMC slot on AST2500 EVB
Andrew Peng (1):
ARM: dts: aspeed: Add Lenovo Hr855xg2 BMC
Ben Pai (1):
ARM: dts: aspeed: Add Mihawk BMC platform
Hongwei Zhang (1):
ARM: dts: aspeed: Add SGPM pinmux
Joel Stanley (1):
ARM: dts: aspeed: swift: Add eMMC device
John Wang (1):
ARM: dts: aspeed: fp5280g2: Fix power supply address
Matt Spinler (1):
ARM: dts: aspeed: swift: Fix FSI GPIOs
Tao Ren (3):
ARM: dts: aspeed: Add Facebook Minipack BMC
ARM: dts: aspeed: Add Facebook Wedge40 BMC
ARM: dts: aspeed: Add Facebook Wedge100 BMC
Vijay Khemka (3):
ARM: dts: aspeed: tiogapass: Add VR devices
ARM: dts: aspeed: tiogapass: Move battery sensor
ARM: dts: aspeed: tiogapass: Add Riser card
arch/arm/boot/dts/Makefile | 5 +
arch/arm/boot/dts/aspeed-ast2500-evb.dts | 11 +
arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts | 429 ++++++++++
.../arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 272 +++++-
arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts | 149 ++++
arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts | 141 ++++
arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts | 4 +-
arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts | 663 +++++++++++++++
arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts | 918 +++++++++++++++++++++
arch/arm/boot/dts/aspeed-bmc-opp-swift.dts | 15 +-
arch/arm/boot/dts/aspeed-g4.dtsi | 28 +
arch/arm/boot/dts/aspeed-g5.dtsi | 33 +
12 files changed, 2659 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts
create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts
create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
create mode 100644 arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts
create mode 100755 arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts
^ permalink raw reply
* [GIT PULL] ARM: aspeed: arch changes for 5.4
From: Joel Stanley @ 2019-08-25 14:09 UTC (permalink / raw)
To: linux-aspeed
Hello ARM Maintainers,
Here's my first mach-aspeed pull request. We finally had to add some
code here to support SMP on the shiny new ASPEED AST2600.
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git \
tags/aspeed-5.4-arch
for you to fetch changes up to 87dfe49691a3aefd66ebe76a4a0cc9e872d2587b:
ARM: aspeed: Enable SMP boot (2019-08-25 23:26:52 +0930)
----------------------------------------------------------------
ASPEED architecture updates for 5.4
This adds support for the new ASPEED AST2600 BMC SoC.
----------------------------------------------------------------
Joel Stanley (4):
dt-bindings: arm: cpus: Add ASPEED SMP
ARM: aspeed: Select timer in each SoC
ARM: aspeed: Add ASPEED AST2600 architecture
ARM: aspeed: Enable SMP boot
Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
arch/arm/Makefile | 1 +
arch/arm/mach-aspeed/Kconfig | 17 ++++++-
arch/arm/mach-aspeed/Makefile | 5 ++
arch/arm/mach-aspeed/platsmp.c | 61 +++++++++++++++++++++++++
5 files changed, 83 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-aspeed/Makefile
create mode 100644 arch/arm/mach-aspeed/platsmp.c
^ permalink raw reply
* [PATCH] media: aspeed: fix an incorrect return code on buffer allocation failure
From: Jae Hyun Yoo @ 2019-08-23 21:29 UTC (permalink / raw)
To: linux-aspeed
It returns '0' even when a failure happens on jpeg buffer allocation
so this commit fixes the issue.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
---
drivers/media/platform/aspeed-video.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c
index f899ac3b4a61..94f97d96dabc 100644
--- a/drivers/media/platform/aspeed-video.c
+++ b/drivers/media/platform/aspeed-video.c
@@ -1624,6 +1624,7 @@ static int aspeed_video_init(struct aspeed_video *video)
if (!aspeed_video_alloc_buf(video, &video->jpeg,
VE_JPEG_HEADER_SIZE)) {
dev_err(dev, "Failed to allocate DMA for JPEG header\n");
+ rc = -ENOMEM;
goto err_release_reserved_mem;
}
--
2.7.4
^ permalink raw reply related
* [PATCH v1 3/3] watchdog/aspeed: add support for dual boot
From: Ivan Mikhaylov @ 2019-08-23 14:58 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190823141930.GA11610@roeck-us.net>
On Fri, 2019-08-23 at 07:19 -0700, Guenter Roeck wrote:
> >
> > +/* access_cs0 shows if cs0 is accessible, hence the reverted bit */
> > +static ssize_t access_cs0_show(struct device *dev,
> > + struct device_attribute *attr, char *buf)
> > +{
> > + struct aspeed_wdt *wdt = dev_get_drvdata(dev);
> > +
>
> Unnecessary empty line.
>
Ok, will cut.
> > +static ssize_t access_cs0_store(struct device *dev,
> > + struct device_attribute *attr,
> > + const char *buf, size_t size)
> > +{
> > + struct aspeed_wdt *wdt = dev_get_drvdata(dev);
> > + unsigned long val = 0;
>
> Unnecessary initialization.
So, you're saying 'unsigned long val;' is enough? Will do then.
>
> So the attribute would only exist if the boot was from the secondary
> flash, and it would exist even if it wasn't needed (ie on ast2500 /
> ast2600)?
Yes, only at secondary flash it will be available.
Also, found out that is for 2600 aspeed completely changed the process of
switch. For 2500 it just swaps chipselects back to make it accordingly as at
first side, on idea it may be helpful.
May be some approach like this will suffice?
if ((of_device_is_compatible(np, "aspeed,ast2400-wdt") or
(of_device_is_compatible(np, "aspeed,ast2500-wdt"))
wdt->wdd.groups = bswitch_groups;
> Well, if that is what you want, who am I to argue, but
> you'll have to document it accordingly. When you do so, please also
> document what happens on ast2500 / ast2600 when the attribute exists
> and is written.
>
Ok, I'll put it in Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
for next patch set.
^ permalink raw reply
* [PATCH v1 3/3] watchdog/aspeed: add support for dual boot
From: Guenter Roeck @ 2019-08-23 14:19 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <fafd757238e204b2566f216f1d6a4bef4b4906c5.camel@yadro.com>
On Fri, Aug 23, 2019 at 12:35:28PM +0300, Ivan Mikhaylov wrote:
> Set WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION into WDT_CLEAR_TIMEOUT_STATUS
> to clear out boot code source and re-enable access to the primary SPI flash
> chip while booted via wdt2 from the alternate chip.
>
> AST2400 datasheet says:
> "In the 2nd flash booting mode, all the address mapping to CS0# would be
> re-directed to CS1#. And CS0# is not accessable under this mode. To access
> CS0#, firmware should clear the 2nd boot mode register in the WDT2 status
> register WDT30.bit[1]."
>
> Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
> ---
> drivers/watchdog/aspeed_wdt.c | 44 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 43 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
> index cc71861e033a..62bf95cb741f 100644
> --- a/drivers/watchdog/aspeed_wdt.c
> +++ b/drivers/watchdog/aspeed_wdt.c
> @@ -53,6 +53,8 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
> #define WDT_CTRL_ENABLE BIT(0)
> #define WDT_TIMEOUT_STATUS 0x10
> #define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
> +#define WDT_CLEAR_TIMEOUT_STATUS 0x14
> +#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
>
> /*
> * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
> @@ -165,6 +167,42 @@ static int aspeed_wdt_restart(struct watchdog_device *wdd,
> return 0;
> }
>
> +/* access_cs0 shows if cs0 is accessible, hence the reverted bit */
> +static ssize_t access_cs0_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct aspeed_wdt *wdt = dev_get_drvdata(dev);
> +
Unnecessary empty line.
> + uint32_t status = readl(wdt->base + WDT_TIMEOUT_STATUS);
> +
> + return sprintf(buf, "%u\n",
> + !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
> +}
> +
> +static ssize_t access_cs0_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t size)
> +{
> + struct aspeed_wdt *wdt = dev_get_drvdata(dev);
> + unsigned long val = 0;
Unnecessary initialization.
> +
> + if (kstrtoul(buf, 10, &val))
> + return -EINVAL;
> +
> + if (val)
> + writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
> + wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
> +
> + return size;
> +}
> +static DEVICE_ATTR_RW(access_cs0);
> +
> +static struct attribute *bswitch_attrs[] = {
> + &dev_attr_access_cs0.attr,
The attribute needs to be documented.
> + NULL
> +};
> +ATTRIBUTE_GROUPS(bswitch);
> +
> static const struct watchdog_ops aspeed_wdt_ops = {
> .start = aspeed_wdt_start,
> .stop = aspeed_wdt_stop,
> @@ -306,8 +344,12 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
> }
>
> status = readl(wdt->base + WDT_TIMEOUT_STATUS);
> - if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY)
> + if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
> wdt->wdd.bootstatus = WDIOF_CARDRESET;
> + wdt->wdd.groups = bswitch_groups;
> + }
So the attribute would only exist if the boot was from the secondary
flash, and it would exist even if it wasn't needed (ie on ast2500 /
ast2600) ? Well, if that is what you want, who am I to argue, but
you'll have to document it accordingly. When you do so, please also
document what happens on ast2500 / ast2600 when the attribute exists
and is written.
> +
> + dev_set_drvdata(dev, wdt);
>
> return devm_watchdog_register_device(dev, &wdt->wdd);
> }
> --
> 2.20.1
>
>
^ permalink raw reply
* [v8 1/1] gpio: aspeed: Add SGPIO driver
From: Linus Walleij @ 2019-08-23 9:41 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <1566335128-31498-2-git-send-email-hongweiz@ami.com>
On Tue, Aug 20, 2019 at 11:05 PM Hongwei Zhang <hongweiz@ami.com> wrote:
> Add SGPIO driver support for Aspeed AST2500 SoC.
>
> Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
This v8 patch applied for v5.4, thanks!
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v1 3/3] watchdog/aspeed: add support for dual boot
From: Ivan Mikhaylov @ 2019-08-23 9:35 UTC (permalink / raw)
To: linux-aspeed
Set WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION into WDT_CLEAR_TIMEOUT_STATUS
to clear out boot code source and re-enable access to the primary SPI flash
chip while booted via wdt2 from the alternate chip.
AST2400 datasheet says:
"In the 2nd flash booting mode, all the address mapping to CS0# would be
re-directed to CS1#. And CS0# is not accessable under this mode. To access
CS0#, firmware should clear the 2nd boot mode register in the WDT2 status
register WDT30.bit[1]."
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
drivers/watchdog/aspeed_wdt.c | 44 ++++++++++++++++++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
index cc71861e033a..62bf95cb741f 100644
--- a/drivers/watchdog/aspeed_wdt.c
+++ b/drivers/watchdog/aspeed_wdt.c
@@ -53,6 +53,8 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
#define WDT_CTRL_ENABLE BIT(0)
#define WDT_TIMEOUT_STATUS 0x10
#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
+#define WDT_CLEAR_TIMEOUT_STATUS 0x14
+#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
/*
* WDT_RESET_WIDTH controls the characteristics of the external pulse (if
@@ -165,6 +167,42 @@ static int aspeed_wdt_restart(struct watchdog_device *wdd,
return 0;
}
+/* access_cs0 shows if cs0 is accessible, hence the reverted bit */
+static ssize_t access_cs0_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct aspeed_wdt *wdt = dev_get_drvdata(dev);
+
+ uint32_t status = readl(wdt->base + WDT_TIMEOUT_STATUS);
+
+ return sprintf(buf, "%u\n",
+ !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
+}
+
+static ssize_t access_cs0_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ struct aspeed_wdt *wdt = dev_get_drvdata(dev);
+ unsigned long val = 0;
+
+ if (kstrtoul(buf, 10, &val))
+ return -EINVAL;
+
+ if (val)
+ writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
+ wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
+
+ return size;
+}
+static DEVICE_ATTR_RW(access_cs0);
+
+static struct attribute *bswitch_attrs[] = {
+ &dev_attr_access_cs0.attr,
+ NULL
+};
+ATTRIBUTE_GROUPS(bswitch);
+
static const struct watchdog_ops aspeed_wdt_ops = {
.start = aspeed_wdt_start,
.stop = aspeed_wdt_stop,
@@ -306,8 +344,12 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
}
status = readl(wdt->base + WDT_TIMEOUT_STATUS);
- if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY)
+ if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
wdt->wdd.bootstatus = WDIOF_CARDRESET;
+ wdt->wdd.groups = bswitch_groups;
+ }
+
+ dev_set_drvdata(dev, wdt);
return devm_watchdog_register_device(dev, &wdt->wdd);
}
--
2.20.1
^ permalink raw reply related
* [PATCH v1 2/3] vesnin: add secondary SPI flash chip
From: Ivan Mikhaylov @ 2019-08-23 9:33 UTC (permalink / raw)
To: linux-aspeed
Adds secondary SPI flash chip into dts for vesnin.
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
index 2ee26c86a32e..db4cc3df61ce 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
@@ -81,6 +81,14 @@
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
+
+ flash at 1 {
+ status = "okay";
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ label = "alt";
+ };
};
&spi {
--
2.20.1
^ permalink raw reply related
* [PATCH v1 1/3] vesnin: add wdt2 section with alt-boot option
From: Ivan Mikhaylov @ 2019-08-23 9:32 UTC (permalink / raw)
To: linux-aspeed
Adds wdt2 section with 'alt-boot' option into dts for vesnin.
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
index 0b9e29c3212e..2ee26c86a32e 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
@@ -222,3 +222,7 @@
&vuart {
status = "okay";
};
+
+&wdt2 {
+ aspeed,alt-boot;
+};
--
2.20.1
^ permalink raw reply related
* [PATCH v1 0/3] add dual-boot support
From: Ivan Mikhaylov @ 2019-08-23 9:31 UTC (permalink / raw)
To: linux-aspeed
ASPEED SoCs support dual-boot feature for SPI Flash.
When strapped appropriately, the SoC starts wdt2 (/dev/watchdog1)
and if within a minute it is not disabled, it goes off and reboots
the SoC from an alternate SPI Flash chip by changing CS0 controls
to actually drive CS1 line.
When booted from alternate chip, in order to access the main chip
at CS0, the user must reset the appropriate bit in the watchdog
hardware. There is no interface that would allow to do that from
an embedded firmware startup script.
This commit implements support for that feature:
* Enable 'alt-boot' option for wdt2
* Enable secondary SPI flash chip
* Make it possible to get access to the primary SPI flash chip at CS0
after booting from the alternate chip at CS1. A sysfs interface is added
to provide an easy way for embedded firmware startup scripts to clear
the chip select bit to gain access to the primary flash chip in order
to allow for recovery of its contents.
Ivan Mikhaylov (3):
vesnin: add wdt2 section with alt-boot option
vesnin: add secondary SPI flash chip
watchdog/aspeed: add support for dual boot
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 12 +++++++++
drivers/watchdog/aspeed_wdt.c | 30 +++++++++++++++++++++
2 files changed, 42 insertions(+)
--
2.20.1
^ permalink raw reply
* [PATCH 3/7] media: aspeed-video: address a protential usage of an unit var
From: Mauro Carvalho Chehab @ 2019-08-22 19:39 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <4a411ba155eb062b6575aba0824123c840806c0b.1566502743.git.mchehab+samsung@kernel.org>
While this might not occur in practice, if the device is doing
the right thing, it would be teoretically be possible to have
both hsync_counter and vsync_counter negatives.
If this ever happen, ctrl will be undefined, but the driver
will still call:
aspeed_video_update(video, VE_CTRL, 0, ctrl);
Change the code to prevent this to happen.
This was warned by cppcheck:
[drivers/media/platform/aspeed-video.c:653]: (error) Uninitialized variable: ctrl
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
---
drivers/media/platform/aspeed-video.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c
index f899ac3b4a61..4ef37cfc8446 100644
--- a/drivers/media/platform/aspeed-video.c
+++ b/drivers/media/platform/aspeed-video.c
@@ -630,7 +630,7 @@ static void aspeed_video_check_and_set_polarity(struct aspeed_video *video)
}
if (hsync_counter < 0 || vsync_counter < 0) {
- u32 ctrl;
+ u32 ctrl = 0;
if (hsync_counter < 0) {
ctrl = VE_CTRL_HSYNC_POL;
@@ -650,7 +650,8 @@ static void aspeed_video_check_and_set_polarity(struct aspeed_video *video)
V4L2_DV_VSYNC_POS_POL;
}
- aspeed_video_update(video, VE_CTRL, 0, ctrl);
+ if (ctrl)
+ aspeed_video_update(video, VE_CTRL, 0, ctrl);
}
}
--
2.21.0
^ permalink raw reply related
* [PATCH 3/3] watchdog/aspeed: add support for dual boot
From: Alexander Amelkin @ 2019-08-22 16:45 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190822160127.GA6992@roeck-us.net>
22.08.2019 19:01, Guenter Roeck wrote:
> On Thu, Aug 22, 2019 at 05:36:21PM +0300, Alexander Amelkin wrote:
>> 21.08.2019 21:10, Guenter Roeck wrote:
>>> On Wed, Aug 21, 2019 at 08:42:24PM +0300, Alexander Amelkin wrote:
>>>> 21.08.2019 19:32, Guenter Roeck wrote:
>>>>> On Wed, Aug 21, 2019 at 06:57:43PM +0300, Ivan Mikhaylov wrote:
>>>>>> Set WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION into WDT_CLEAR_TIMEOUT_STATUS
>>>>>> to clear out boot code source and re-enable access to the primary SPI flash
>>>>>> chip while booted via wdt2 from the alternate chip.
>>>>>>
>>>>>> AST2400 datasheet says:
>>>>>> "In the 2nd flash booting mode, all the address mapping to CS0# would be
>>>>>> re-directed to CS1#. And CS0# is not accessable under this mode. To access
>>>>>> CS0#, firmware should clear the 2nd boot mode register in the WDT2 status
>>>>>> register WDT30.bit[1]."
>>>>> Is there reason to not do this automatically when loading the module
>>>>> in alt-boot mode ? What means does userspace have to determine if CS0
>>>>> or CS1 is active at any given time ? If there is reason to ever have CS1
>>>>> active instead of CS0, what means would userspace have to enable it ?
>>>> Yes, there is. The driver is loaded long before the filesystems are mounted.
>>>> The filesystems, in the event of alternate/recovery boot, need to be mounted
>>>> from the same chip that the kernel was booted. For one reason because the main
>>>> chip at CS0 is most probably corrupt. If you clear that bit when driver is
>>>> loaded, your software will not know that and will try to mount the wrong
>>>> filesystems. The whole idea of ASPEED's switching chipselects is to have
>>>> identical firmware in both chips, without the need to process the alternate
>>>> boot state in any way except for indicating a successful boot and restoring
>>>> access to CS0 when needed.
>>>>
>>>> The userspace can read bootstatus sysfs node to determine if an alternate
>>>> boot has occured.
>>>>
>>>> With ASPEED, CS1 is activated automatically by wdt2 when system fails to boot
>>>> from the primary flash chip (at CS0) and disable the watchdog to indicate a
>>>> successful boot. When that happens, both CS0 and CS1 controls? get routed in
>>>> hardware to CS1 line, making the primary flash chip inaccessible. Depending
>>>> on the architecture of the user-space software, it may choose to re-enable
>>>> access to the primary chip via CS0 at different times. There must be a way to do so.
>>>>
>>> So by activating cs0, userspace would essentially pull its own root file system
>>> from underneath itself ?
>> Exactly. That's why for alternate boot the firmware would usually copy
>> all filesystems to memory and mount from there. Some embedded systems
>> do that always, regardless of which chip they boot from.
>>
> That is different, though, to what you said earlier. Linux would then start
> with a clean file system, and not need access to the file system in cs1 at all.
> Clearing the flag when starting the driver would then be ok.
I don't see how that is different. Copying to memory may be done by startup
scripts that run after the driver is loaded, so they need to read the data from
the chip they are booted from. That is how it is done in OpenBMC, for instance.
Other flavors of firmware may choose a different approach.
Having the control available via sysfs gives more flexibility.
>> However, to be able to recover the main flash chip, the system needs CS0
>> to function as such (not as CS1). That's why this control is needed.
>>
> If what you said is correct, not really. It should be fine and create more
> predictive behavior if the probe function selects cs0 automatically.
Well, this is not a function for home users. This is for servers. You won't
even find an ASPEED BMC chip in a home PC. Aspeed's dual-boot is quite
an advanced feature and people willing to use it are expected to be able
to predict the behavior. To me, as an embedded systems developer,
automatic selection of cs0 by probe is a limitation. I prefer flexibility.
With best regards,
Alexander Amelkin,
BIOS/BMC Team Lead, YADRO
https://yadro.com
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^ permalink raw reply
* [PATCH 3/3] watchdog/aspeed: add support for dual boot
From: Guenter Roeck @ 2019-08-22 16:01 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <5cb20f52-884a-b921-c904-ebf244092318@yadro.com>
On Thu, Aug 22, 2019 at 05:36:21PM +0300, Alexander Amelkin wrote:
> 21.08.2019 21:10, Guenter Roeck wrote:
> > On Wed, Aug 21, 2019 at 08:42:24PM +0300, Alexander Amelkin wrote:
> >> 21.08.2019 19:32, Guenter Roeck wrote:
> >>> On Wed, Aug 21, 2019 at 06:57:43PM +0300, Ivan Mikhaylov wrote:
> >>>> Set WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION into WDT_CLEAR_TIMEOUT_STATUS
> >>>> to clear out boot code source and re-enable access to the primary SPI flash
> >>>> chip while booted via wdt2 from the alternate chip.
> >>>>
> >>>> AST2400 datasheet says:
> >>>> "In the 2nd flash booting mode, all the address mapping to CS0# would be
> >>>> re-directed to CS1#. And CS0# is not accessable under this mode. To access
> >>>> CS0#, firmware should clear the 2nd boot mode register in the WDT2 status
> >>>> register WDT30.bit[1]."
> >>> Is there reason to not do this automatically when loading the module
> >>> in alt-boot mode ? What means does userspace have to determine if CS0
> >>> or CS1 is active at any given time ? If there is reason to ever have CS1
> >>> active instead of CS0, what means would userspace have to enable it ?
> >> Yes, there is. The driver is loaded long before the filesystems are mounted.
> >> The filesystems, in the event of alternate/recovery boot, need to be mounted
> >> from the same chip that the kernel was booted. For one reason because the main
> >> chip at CS0 is most probably corrupt. If you clear that bit when driver is
> >> loaded, your software will not know that and will try to mount the wrong
> >> filesystems. The whole idea of ASPEED's switching chipselects is to have
> >> identical firmware in both chips, without the need to process the alternate
> >> boot state in any way except for indicating a successful boot and restoring
> >> access to CS0 when needed.
> >>
> >> The userspace can read bootstatus sysfs node to determine if an alternate
> >> boot has occured.
> >>
> >> With ASPEED, CS1 is activated automatically by wdt2 when system fails to boot
> >> from the primary flash chip (at CS0) and disable the watchdog to indicate a
> >> successful boot. When that happens, both CS0 and CS1 controls? get routed in
> >> hardware to CS1 line, making the primary flash chip inaccessible. Depending
> >> on the architecture of the user-space software, it may choose to re-enable
> >> access to the primary chip via CS0 at different times. There must be a way to do so.
> >>
> > So by activating cs0, userspace would essentially pull its own root file system
> > from underneath itself ?
>
> Exactly. That's why for alternate boot the firmware would usually copy
> all filesystems to memory and mount from there. Some embedded systems
> do that always, regardless of which chip they boot from.
>
That is different, though, to what you said earlier. Linux would then start
with a clean file system, and not need access to the file system in cs1 at all.
Clearing the flag when starting the driver would then be ok.
> However, to be able to recover the main flash chip, the system needs CS0
> to function as such (not as CS1). That's why this control is needed.
>
If what you said is correct, not really. It should be fine and create more
predictive behavior if the probe function selects cs0 automatically.
Guenter
> As Ivan mentioned, for AST2500 and the upcoming AST2600 the behavior
> is slightly different. They don't just connect both CS controls to CS1 but instead
> swap them so the primary chip becomes secondary from the software point
> of view. The means to restore the normal wiring may still be needed.
>
> >
> >> This code most probably adds nothing at the assembly level.
> >>
> > That seems quite unlikely. Please demonstrate.
>
> Yes, you were right. It adds 7 instructions. We'll drop the check.
> It's just my DO-178 background, I add 'robustness' checks everywhere.
>
> >>>> + writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
> >>>> + wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
> >>>> + wdt->wdd.bootstatus |= WDIOF_EXTERN1;
> >>> The variable reflects the _boot status_. It should not change after booting.
> >> Is there any documentation that dictates that? All I could find is
> >>
> >> "bootstatus: status of the device after booting". That doesn't look to me like it absolutely can not change to reflect the updated status (that is, to reflect that the originally set up alternate CS routing has been reset to normal).
> >>
> > You choose to interpret "after booting" in a kind of novel way,
> > which I find a bit disturbing. I am not really sure how else to
> > describe "boot status" in a way that does not permit such
> > reinterpratation of the term.
>
> How about "Reflects reasons that caused a reboot, remains constant until the next boot" ?
>
> > On top of that, how specifically would "WDIOF_EXTERN1" reflect
> > what you claim it does ? Not only you are hijacking bootstatus9
> > (which is supposed to describe the reason for a reboot), you
> > are also hijacking WDIOF_EXTERN1. That seems highly arbitrary
> > to me, and is not really how an API/ABI should be used.
>
> We used WDIOF_EXTERN1 because:
>
> 1. We thought that bootstatus _can_ change
>
> 2. We thought that adding extra bits wouldn't be appreciated
>
> Now as you clarified that assumption 1 was wrong we are going to implement status as I proposed earlier:
>
> >
> >> I think we could make 'access_cs0' readable instead, so it could report the
> >> current state of the boot code selection bit. Reverted, I suppose. That
> >> way 'access_cs0' would report 1 after 1 has been written to it (it wouldn't
> >> be possible to write a zero).
>
> With best regards,
> Alexander Amelkin,
> BIOS/BMC Team Lead, YADRO
> https://yadro.com
>
>
^ permalink raw reply
* [PATCH 3/3] watchdog/aspeed: add support for dual boot
From: Alexander Amelkin @ 2019-08-22 14:36 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190821181008.GB15127@roeck-us.net>
21.08.2019 21:10, Guenter Roeck wrote:
> On Wed, Aug 21, 2019 at 08:42:24PM +0300, Alexander Amelkin wrote:
>> 21.08.2019 19:32, Guenter Roeck wrote:
>>> On Wed, Aug 21, 2019 at 06:57:43PM +0300, Ivan Mikhaylov wrote:
>>>> Set WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION into WDT_CLEAR_TIMEOUT_STATUS
>>>> to clear out boot code source and re-enable access to the primary SPI flash
>>>> chip while booted via wdt2 from the alternate chip.
>>>>
>>>> AST2400 datasheet says:
>>>> "In the 2nd flash booting mode, all the address mapping to CS0# would be
>>>> re-directed to CS1#. And CS0# is not accessable under this mode. To access
>>>> CS0#, firmware should clear the 2nd boot mode register in the WDT2 status
>>>> register WDT30.bit[1]."
>>> Is there reason to not do this automatically when loading the module
>>> in alt-boot mode ? What means does userspace have to determine if CS0
>>> or CS1 is active at any given time ? If there is reason to ever have CS1
>>> active instead of CS0, what means would userspace have to enable it ?
>> Yes, there is. The driver is loaded long before the filesystems are mounted.
>> The filesystems, in the event of alternate/recovery boot, need to be mounted
>> from the same chip that the kernel was booted. For one reason because the main
>> chip at CS0 is most probably corrupt. If you clear that bit when driver is
>> loaded, your software will not know that and will try to mount the wrong
>> filesystems. The whole idea of ASPEED's switching chipselects is to have
>> identical firmware in both chips, without the need to process the alternate
>> boot state in any way except for indicating a successful boot and restoring
>> access to CS0 when needed.
>>
>> The userspace can read bootstatus sysfs node to determine if an alternate
>> boot has occured.
>>
>> With ASPEED, CS1 is activated automatically by wdt2 when system fails to boot
>> from the primary flash chip (at CS0) and disable the watchdog to indicate a
>> successful boot. When that happens, both CS0 and CS1 controls? get routed in
>> hardware to CS1 line, making the primary flash chip inaccessible. Depending
>> on the architecture of the user-space software, it may choose to re-enable
>> access to the primary chip via CS0 at different times. There must be a way to do so.
>>
> So by activating cs0, userspace would essentially pull its own root file system
> from underneath itself ?
Exactly. That's why for alternate boot the firmware would usually copy
all filesystems to memory and mount from there. Some embedded systems
do that always, regardless of which chip they boot from.
However, to be able to recover the main flash chip, the system needs CS0
to function as such (not as CS1). That's why this control is needed.
As Ivan mentioned, for AST2500 and the upcoming AST2600 the behavior
is slightly different. They don't just connect both CS controls to CS1 but instead
swap them so the primary chip becomes secondary from the software point
of view. The means to restore the normal wiring may still be needed.
>
>> This code most probably adds nothing at the assembly level.
>>
> That seems quite unlikely. Please demonstrate.
Yes, you were right. It adds 7 instructions. We'll drop the check.
It's just my DO-178 background, I add 'robustness' checks everywhere.
>>>> + writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
>>>> + wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
>>>> + wdt->wdd.bootstatus |= WDIOF_EXTERN1;
>>> The variable reflects the _boot status_. It should not change after booting.
>> Is there any documentation that dictates that? All I could find is
>>
>> "bootstatus: status of the device after booting". That doesn't look to me like it absolutely can not change to reflect the updated status (that is, to reflect that the originally set up alternate CS routing has been reset to normal).
>>
> You choose to interpret "after booting" in a kind of novel way,
> which I find a bit disturbing. I am not really sure how else to
> describe "boot status" in a way that does not permit such
> reinterpratation of the term.
How about "Reflects reasons that caused a reboot, remains constant until the next boot" ?
> On top of that, how specifically would "WDIOF_EXTERN1" reflect
> what you claim it does ? Not only you are hijacking bootstatus9
> (which is supposed to describe the reason for a reboot), you
> are also hijacking WDIOF_EXTERN1. That seems highly arbitrary
> to me, and is not really how an API/ABI should be used.
We used WDIOF_EXTERN1 because:
1. We thought that bootstatus _can_ change
2. We thought that adding extra bits wouldn't be appreciated
Now as you clarified that assumption 1 was wrong we are going to implement status as I proposed earlier:
>
>> I think we could make 'access_cs0' readable instead, so it could report the
>> current state of the boot code selection bit. Reverted, I suppose. That
>> way 'access_cs0' would report 1 after 1 has been written to it (it wouldn't
>> be possible to write a zero).
With best regards,
Alexander Amelkin,
BIOS/BMC Team Lead, YADRO
https://yadro.com
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^ permalink raw reply
* [PATCH 3/3] watchdog/aspeed: add support for dual boot
From: Ivan Mikhaylov @ 2019-08-22 14:24 UTC (permalink / raw)
To: linux-aspeed
In-Reply-To: <20190822135528.GB8144@roeck-us.net>
On Thu, 2019-08-22 at 06:55 -0700, Guenter Roeck wrote:
> On Thu, Aug 22, 2019 at 12:15:20PM +0300, Ivan Mikhaylov wrote:
> > On Wed, 2019-08-21 at 09:32 -0700, Guenter Roeck wrote:
> > > > + writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
> > > > + wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
> > > > + wdt->wdd.bootstatus |= WDIOF_EXTERN1;
> > >
> > > The variable reflects the _boot status_. It should not change after
> > > booting.
> >
> > Okay, then perhaps may we set 'status' handler for watchdog device and
> > check
> > 'status' file? Right now 'bootstatus' and 'status' are same because there is
> > no
> > handler for 'status'.
> >
>
> You would still have to redefine one of the status bits to mean something
> driver specific. You would also still have two different flags to read
> and control cs0 - to read the status, you would read an ioctl (or the
> status sysfs attribute), to write it you would write into access_cs0.
>
> I guess I must be missing something. What is the problem with using
> access_cs0 for both ?
>
> Guenter
>
There is no problem, I'll do that way, thanks!
^ permalink raw reply
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