From: Christoph Hellwig <hch@lst.de>
To: Ming Lei <ming.lei@redhat.com>
Cc: Christoph Hellwig <hch@lst.de>,
linux-block@vger.kernel.org, Keith Busch <kbusch@kernel.org>,
Jens Axboe <axboe@kernel.dk>,
Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: [Regression] b1a000d3b8ec ("block: relax direct io memory alignment")
Date: Wed, 16 Oct 2024 14:31:53 +0200 [thread overview]
Message-ID: <20241016123153.GA18219@lst.de> (raw)
In-Reply-To: <Zw958YtMExrNhUxy@fedora>
On Wed, Oct 16, 2024 at 04:31:45PM +0800, Ming Lei wrote:
> On Wed, Oct 16, 2024 at 10:04:19AM +0200, Christoph Hellwig wrote:
> > On Wed, Oct 16, 2024 at 12:40:13AM +0800, Ming Lei wrote:
> > > Hello Guys,
> > >
> > > Turns out host controller's DMA alignment is often too relax, so two DMA
> > > buffers may cross same cache line easily, and trigger the warning of
> > > "cacheline tracking EEXIST, overlapping mappings aren't supported".
> > >
> > > The attached test code can trigger the warning immediately with CONFIG_DMA_API_DEBUG
> > > enabled when reading from one scsi disk which queue DMA alignment is 3.
> > >
> >
> > We should not allow smaller than cache line alignment on architectures
> > that are not cache coherent indeed.
>
> Yes, something like the following change:
We only really need this if the architecture support cache incoherent
DMA. Maybe even as a runtime setting.
next prev parent reply other threads:[~2024-10-16 12:31 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-15 16:40 [Regression] b1a000d3b8ec ("block: relax direct io memory alignment") Ming Lei
2024-10-16 8:04 ` Christoph Hellwig
2024-10-16 8:31 ` Ming Lei
2024-10-16 12:31 ` Christoph Hellwig [this message]
2024-10-22 1:21 ` Ming Lei
2024-10-22 7:25 ` Christoph Hellwig
2024-10-22 2:15 ` Jens Axboe
2024-10-22 10:24 ` Catalin Marinas
2024-10-23 0:50 ` Ming Lei
2024-10-23 6:12 ` Christoph Hellwig
2024-10-23 8:14 ` Ming Lei
2024-10-23 12:23 ` Christoph Hellwig
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