Re: [PATCH 1/1] nvme-pci: set virt boundary according to capability

[Max Gurtovoy <mgurtovoy@nvidia.com>]

On 09/12/2025 8:40, Christoph Hellwig wrote:
> On Tue, Dec 09, 2025 at 12:26:20AM +0200, Max Gurtovoy wrote:
>> Some controllers advertise DWORD alignment for SGLs, so configure the
>> virtual boundary correctly for those devices.
>>
>> Signed-off-by: Max Gurtovoy <mgurtovoy@nvidia.com>
>> ---
>>   drivers/nvme/host/pci.c | 4 +++-
>>   1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
>> index e5ca8301bb8b..eacc89cd25eb 100644
>> --- a/drivers/nvme/host/pci.c
>> +++ b/drivers/nvme/host/pci.c
>> @@ -3326,7 +3326,9 @@ static unsigned long nvme_pci_get_virt_boundary(struct nvme_ctrl *ctrl,
>>   {
>>   	if (!nvme_ctrl_sgl_supported(ctrl) || is_admin)
>>   		return NVME_CTRL_PAGE_SIZE - 1;
>> -	return 0;
>> +	else if (ctrl->sgls & NVME_CTRL_SGLS_BYTE_ALIGNED)
>> +		return 0;
>> +	return 3;
> I don't think this is correct.  NVME_CTRL_SGLS_BYTE_ALIGNED requires
> each SGL to be aligned, but is not a virt boundary.  The dma_alignment
> value in the queue_limits already takes care of that.

I see. The virt boundary handles the gaps.

Should we modify:

dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);

and

lim->dma_alignment = 3;

to ease the restriction for capable devices with 
NVME_CTRL_SGLS_BYTE_ALIGNED support ?

>