RE: Reg: New MFD Driver for my PCIe Device

Kumaravel.Thiagarajan
2021-11-19T09:16:41Z

Dear Greg KH,

I went through the documentation of aux bus and felt that it would be the correct way to go as you said.
I will migrate from MFD to aux bus.

I have one more architectural question as below.
I have written the driver such that it enumerates the OTP memory and EEPROM memory as two separate block devices or disks each of size 8KB and this enables me to use the linux dd command with "direct" option to dump the configuration binary onto OTP or EEPROM devices.
Also, this enables me to use the application like hexedit to view the OTP or EEPROM devices in raw binary format.
These devices are not based on mtd (memory technology device) architecture as we don't have any erase functionality here.
Can you please let me know a suitable location in kernel source tree for my block or disk device driver?

Thank You.

Regards,
Kumaravel Thiagarajan

-----Original Message-----
From: Greg KH <gregkh@linuxfoundation.org>
Sent: Tuesday, November 16, 2021 7:50 PM
To: Kumaravel Thiagarajan - I21417 <Kumaravel.Thiagarajan@microchip.com>
Cc: lee.jones@linaro.org; Pragash Mangalapandian - I21326 <Pragash.Mangalapandian@microchip.com>; Sundararaman Hariharaputran - I21286 <Sundararaman.H@microchip.com>; axboe@kernel.dk; linux-block@vger.kernel.org; miquel.raynal@bootlin.com; richard@nod.at; vigneshr@ti.com; linux-mtd@lists.infradead.org; Lakshmi Praveen Kopparthi - I17972 <LakshmiPraveen.Kopparthi@microchip.com>
Subject: Re: Reg: New MFD Driver for my PCIe Device

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On Tue, Nov 16, 2021 at 11:34:24AM +0000, Kumaravel.Thiagarajan@microchip.com wrote:
> Dear Greg K-H & Lee Jones,
>
> Thanks for your inputs and I need more of your help to understand things better.
>
> I took this MFD route not just based on the recommendation from Linus Walleij but also based on the kernel documentation @ /Documentation/driver-api/driver-model/platform.rst which states as below.
>
> "Rarely, a platform_device will be connected through a segment of some other kind of bus; but its registers will still be directly addressable."
>
> I visualized these two (GPIO controller & OTP/EEPROM controller) devices as platform devices present on the same PCI function and these two devices are not detectable unless the base PCI function driver enumerates them and anyway their registers are directly addressable.
> Hence, I thought that the platform driver architecture is inclusive of devices like this.

Sorry, but no. Again, platform devices are ONLY for actual platform devices, not "things on a device that happens to be on another bus device". Like PCI devices.

That is what the auxiliary bus code was written for, please read Documentation/driver-api/auxiliary_bus.rst for how to use it.

> Please let me know your comments.
>
> Also please let me know if I can talk to any of you over a webex call to get clarifications on my further doubts.

Email works best, video chats for every patch review does not scale at all :)

thanks,

greg k-h