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Sat, 01 Aug 2026 08:31:09 -0700 (PDT) X-Received: by 2002:a17:90b:17c5:b0:385:39ac:fe4b with SMTP id 98e67ed59e1d1-38fb263d5admr6158843a91.17.1785598268995; Sat, 01 Aug 2026 08:31:08 -0700 (PDT) Received: from [192.168.1.7] ([122.177.240.1]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13fab4e44bcsm20902752c88.12.2026.08.01.08.31.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 01 Aug 2026 08:31:08 -0700 (PDT) Message-ID: <4523441f-498a-4bbd-80f3-97a7a9206c00@oss.qualcomm.com> Date: Sat, 1 Aug 2026 21:01:00 +0530 Precedence: bulk X-Mailing-List: linux-bluetooth@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/6] dt-bindings: bluetooth: qca: add QCC2072 To: Krzysztof Kozlowski Cc: Bartosz Golaszewski , Marcel Holtmann , Luiz Augusto von Dentz , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Balakrishna Godavarthi , Rocky Liao , Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-bluetooth@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, quic_mohamull@quicinc.com, quic_hbandi@quicinc.com, quic_anubhavg@quicinc.com References: <20260727-rb3-industrial-bt-uart-v2-0-2d100f30e202@oss.qualcomm.com> <20260727-rb3-industrial-bt-uart-v2-1-2d100f30e202@oss.qualcomm.com> <20260731-first-righteous-bear-dd72ed@quoll> <712f8a14-d2a1-4a90-82f9-05cd694f2658@oss.qualcomm.com> <6d6465bb-47ac-464c-af4e-0ca72325705f@oss.qualcomm.com> <8a388310-d3cc-4d02-abb6-0eb98c24cfce@kernel.org> Content-Language: en-US From: Rahul Samana In-Reply-To: <8a388310-d3cc-4d02-abb6-0eb98c24cfce@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAxMDEyNCBTYWx0ZWRfX5uS+9/6/TxmC H+LhU+Blz4uKDe9/YiPWf38xte7ZYXb02lze+pEYOyr8lm3MLn8WVzj7kFUBzFUrf5IUHrtLGyQ Y70DMwTCWcZ9B08IfNe4kh/C1HSSKfpNkmuzWKaRXYZQ1NEQiTwHeAOccdjBX6PHwtIreHeO62K oxrpiEVQQDjVZFjQ9rWc46ty08pHOw1SRD/MyeNWBNM8/ZXc3oZozSYsKMx3YHD5fL0WUJqmy7B jMr+An/PX59t5CSjYJD6VI5yFt6cKbMcg6Pel34gaJq3TtJV9T8GE5bCRRZHTzRQHw4KkKjTGIl 3KkGvW2vv2PD6NGp6GRGIakPuRMtpuoRjoOFdHG9WPaqdjbvQ4dOTshi9cjGokzCUrbdrgs6a7q ZSqEpIdhS0x7i7INKArxppzFxl785N1YM/K/J1fYAR1YYq/pzadG5e+WhL7KZ3DkLxXlfu4vWoS LbGrSEIkf+XFsO62P2g== X-Proofpoint-GUID: fq3laPJZVG3TJgj6cfSBhK4GWE09s5Eg X-Authority-Analysis: v=2.4 cv=T9C8ifKQ c=1 sm=1 tr=0 ts=6a6e1143 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=2skDqgroqaW2kJZUe6+7Kg==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=QZOgD_54N6fV3tg6C9wA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODAxMDEyNCBTYWx0ZWRfX7u/qYk8CM30K 4bOgpPywOuYo2W44UkxkftBEvNLmLpm0qk7dct5v2ouoZZyaick3UcziyTKL/RrHqqPukULSgWV VinyCVSGjy0B2YXyYzYhpp8MrWFjDhE= X-Proofpoint-ORIG-GUID: fq3laPJZVG3TJgj6cfSBhK4GWE09s5Eg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-01_01,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 adultscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608010124 On 01-08-2026 20:18, Krzysztof Kozlowski wrote: > On 31/07/2026 17:51, Rahul Samana wrote: >> >> >> On 31-07-2026 20:34, Krzysztof Kozlowski wrote: >>> On 31/07/2026 16:45, Rahul Samana wrote: >>>> >>>> >>>> On 31-07-2026 15:16, Krzysztof Kozlowski wrote: >>>>> On Mon, Jul 27, 2026 at 09:15:01PM +0530, Rahul Samana wrote: >>>>>> QCC2072 can be used on M.2 E-key cards where the card power resources are >>>>>> described by the pcie-m2-e-connector node. In that setup, the M.2 power >>>>>> sequencing provider creates the Bluetooth serdev child after matching the >>>>>> QCC2072 PCI function. >>>>>> >>>>>> Integrated non-M.2 designs need board-specific power resources. Document >>>>>> only the compatible for now and leave those properties to be added with >>>>>> matching driver support. >>>>>> >>>>>> Document the qcom,qcc2072-bt compatible used for QCC2072 Bluetooth >>>>>> controllers connected over UART. >>>>>> >>>>>> Signed-off-by: Rahul Samana >>>>> >>>>> NAK, exactly same comments as before. >>>>> >>>>> Nothing got improved, although what is weird - original SoB is gone, so >>>>> this is legally dubious work. >>>>> >>>>> Best regards, >>>>> Krzysztof >>>>> >>>> >>>> Hi Krzysztof, >>>> >>>> Thanks for the review. >>>> >>>> For the binding contents, I tried to capture the current scope in the binding >>>> description itself. This series supports QCC2072 only as an M.2 E-key card, >>>> where the card power resources are described by the pcie-m2-e-connector node >>>> and the M.2 pwrseq provider creates the Bluetooth serdev child. >>>> >>>> The binding also says: >>>> >>>> Integrated non-M.2 designs require board-specific power resources. Those >>>> properties, together with a static devicetree example, should be added when >>>> integrated non-M.2 support is added. >>> >>> Bindings must be complete and your driver support is irrelevant here. >>> >>> If you claim this is a PCI device thus you do not need any resources, >>> then the binding is not needed either. PCI devices are enumerable. And >>> to prove it: look at your DTS. Do you see qcom,qcc2072-bt being used? No. >>> >>>> >>>> We do not currently have an integrated non-M.2 QCC2072 design, so I do not >>>> have board-specific regulator supplies to document for that topology. >>>> >>>> Could you please suggest how you would prefer this binding to be handled for >>>> the current M.2-only use case? >>> >>> Drop the binding, you do not need it. >>> >>> Anyway the problem is that more comments were ignored. >>> >> >> Hi Krzysztof, >> >> Just to clarify the reason for adding this binding in v2: >> v1 did not add a binding because this series only targets the M.2 use case. >> >> I added the minimal binding in v2 because checkpatch reported >> qcom,qcc2072-bt as an undocumented compatible, and I interpreted the request >> to fix the checkpatch warnings as requiring this compatible to be documented. >> I also had the earlier feedback in mind, where the indirect >> qcom,qcc2072-bt compatible was pushed back because it was undocumented: >> >> https://lore.kernel.org/all/20260703-eliza_evk-v1-3-7624440bd76d@oss.qualcomm.com/ >> >> Based on your clarification here, I will drop the binding patch in v3 and >> keep qcom,qcc2072-bt only as the pwrseq-created child compatible for this >> M.2 case. > > My previous statement is also valid, please read entire threads. > > You cannot have undocumented qcom,qcc2072-bt. > > I ask you to drop both, because they are not needed. But feel free to > prove me wrong, see my first paragraph in the previous reply. > > The PCIe M.2 power sequencing driver, pwrseq-pcie-m2.c, uses pwrseq_m2_pci_ids to translate the enumerated PCI function into the Bluetooth compatible used for the generated serdev child. For example, WCN7850 maps PCI ID 17cb:1107 to qcom,wcn7850-bt, then hci_qca matches that compatible to select qca_soc_data_wcn7850. For QCC2072, pwrseq-pcie-m2.c matches PCI ID 17cb:1112 and creates the generated Bluetooth serdev child with compatible "qcom,qcc2072-bt". The hci_qca driver then matches "qcom,qcc2072-bt" and uses qca_soc_data_qcc2072 as the controller-specific data. That match data is needed by hci_qca to select the QCC2072 soc_type, firmware/NVM naming, calibration handling, and capabilities. Without some identity being passed from the PCI match to the generated serdev child, hci_qca cannot distinguish QCC2072 from the other Qualcomm UART Bluetooth controllers on this path. Please correct me if I misunderstood the concern or if you are asking for this identity to be passed from pwrseq-pcie-m2.c to hci_qca through a different mechanism. I can drop the binding patch, but unless there is a preferred alternative mechanism, I think we still need the pwrseq-pcie-m2 QCC2072 PCI ID support from patch 3 so the power sequencing driver can pass the QCC2072 identity into hci_qca through the generated serdev child: https://lore.kernel.org/all/20260727-rb3-industrial-bt-uart-v2-3-2d100f30e202@oss.qualcomm.com/ Thanks, Rahul >> >>> And why this is sent so many times? >>> >>> https://lore.kernel.org/all/20260218114955.3970974-2-vivek.sahu@oss.qualcomm.com/ >>> >>> https://lore.kernel.org/all/20260529175342.3363935-1-yepuri.siddu@oss.qualcomm.com/ >>> >>> and now by you. >>> >>> How many times this will be sent in separate patchsets and asking for >>> separate review ignoring previous review? >>> >> >> Regarding the repeated submissions, the reason for carrying this forward from >> the earlier QCC2072 work is documented in the cover letter. This series was >> intended to continue that work for the RB3 Gen 2 Industrial M.2 use case, not >> to ignore the earlier reviews. > > If you continue the work, you do not ignore previous comments, so I do > not see how this is any sort of continuation. Looks like duplicating > work without looking at previous discussions at all. > > Best regards, > Krzysztof