Re: [PATCH 3/3] arm64: dts: qcom: rb3gen2: add Industrial BT UART overlay

[Rahul Samana <rahul.samana@oss.qualcomm.com>]

On 24-07-2026 00:40, Dmitry Baryshkov wrote:
> On Thu, Jul 23, 2026 at 06:01:09PM +0530, Rahul Samana wrote:
>> Add an overlay for the RB3 Gen 2 Industrial mezzanine variant that routes
>> QCC2072 Bluetooth over UART4 and models the M.2 E-key connector graph
>> endpoints for PCIe and UART.
>>
>> The default Industrial mezzanine overlay describes the common mezzanine
>> hardware. Build this variant by applying the common Industrial mezzanine
>> overlay first, followed by the BT UART overlay, because the reworked board
>> keeps the common mezzanine description and only changes the Bluetooth
>> transport routing.
>>
>> The overlay also disables the on-board WCN6750 PMU and UART7 path so the
>> M.2 QCC2072 Bluetooth controller can be used instead.
>>
>> Signed-off-by: Rahul Samana <rahul.samana@oss.qualcomm.com>
>> ---
>>  arch/arm64/boot/dts/qcom/Makefile                  |   2 +
>>  ...s6490-rb3gen2-industrial-mezzanine-bt-uart.dtso | 133 +++++++++++++++++++++
>>  2 files changed, 135 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 6f33c4e2f09c..45786d3db14a 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -179,8 +179,10 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2.dtb
>>  
>>  qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo
>>  qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo
>> +qcs6490-rb3gen2-industrial-mezzanine-bt-uart-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo qcs6490-rb3gen2-industrial-mezzanine-bt-uart.dtbo
>>  
>>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2-industrial-mezzanine.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2-industrial-mezzanine-bt-uart.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2-vision-mezzanine.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-thundercomm-minipc-g1iot.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-thundercomm-rubikpi3.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine-bt-uart.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine-bt-uart.dtso
>> new file mode 100644
>> index 000000000000..06560df0a719
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine-bt-uart.dtso
>> @@ -0,0 +1,133 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +/plugin/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +&{/} {
>> +	vreg_wcn_3p3: regulator-wcn-3p3 {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "VREG_WCN_3P3";
>> +		regulator-min-microvolt = <3300000>;
>> +		regulator-max-microvolt = <3300000>;
>> +
>> +		regulator-boot-on;
>> +	};
>> +
>> +	m2_e_connector: m2-e-connector {
> 
> Kill unused labels. Everywhere.
> 
>> +		compatible = "pcie-m2-e-connector";
>> +		vpcie3v3-supply = <&vreg_wcn_3p3>;
>> +
>> +		m2_e_ports: ports {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +
>> +			port@0 {
>> +				reg = <0>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +
>> +				m2_e_pcie_ep: endpoint@0 {
>> +					reg = <0>;
>> +					remote-endpoint = <&pcie0_m2_e_ep>;
>> +				};
>> +			};
>> +
>> +			port@3 {
>> +				reg = <3>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +
>> +				m2_e_uart_ep: endpoint@0 {
>> +					reg = <0>;
>> +					remote-endpoint = <&uart4_m2_e_ep>;
>> +				};
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&qup_uart4_cts {
>> +	bias-bus-hold;
>> +};
>> +
>> +&qup_uart4_rts {
>> +	drive-strength = <2>;
>> +	bias-disable;
>> +};
>> +
>> +&qup_uart4_rx {
>> +	bias-pull-up;
>> +};
>> +
>> +&qup_uart4_tx {
>> +	drive-strength = <2>;
>> +	bias-disable;
>> +};
>> +
>> +&tlmm {
>> +	qup_uart4_sleep_cts: qup-uart4-sleep-cts-state {
>> +		pins = "gpio16";
>> +		function = "gpio";
>> +		bias-bus-hold;
>> +	};
>> +
>> +	qup_uart4_sleep_rts: qup-uart4-sleep-rts-state {
>> +		pins = "gpio17";
>> +		function = "gpio";
>> +		bias-pull-down;
>> +	};
>> +
>> +	qup_uart4_sleep_tx: qup-uart4-sleep-tx-state {
>> +		pins = "gpio18";
>> +		function = "gpio";
>> +		bias-pull-up;
>> +	};
>> +
>> +	qup_uart4_sleep_rx: qup-uart4-sleep-rx-state {
>> +		pins = "gpio19";
>> +		function = "gpio";
>> +		bias-pull-up;
>> +	};
>> +};
>> +
>> +&pcie0_port {
>> +	pcie@0,0 {
>> +		pcie@2,0 {
>> +			port {
> 
> The house that Jack built. Don't use multiple nested nodes to patch it.
> The node might go away and nobody will notice it. Add a label to the
> exact location and patch only it.
> 
>> +				pcie0_m2_e_ep: endpoint {
>> +					remote-endpoint = <&m2_e_pcie_ep>;
>> +				};
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&uart4 {
>> +	status = "okay";
>> +	/delete-property/ interrupts;
>> +	interrupts-extended = <&intc GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>,
>> +			      <&tlmm 19 IRQ_TYPE_EDGE_FALLING>;
>> +	pinctrl-names = "default", "sleep";
>> +	pinctrl-1 = <&qup_uart4_sleep_cts>, <&qup_uart4_sleep_rts>,
>> +		    <&qup_uart4_sleep_tx>, <&qup_uart4_sleep_rx>;
>> +
>> +	port {
>> +		uart4_m2_e_ep: endpoint {
>> +			remote-endpoint = <&m2_e_uart_ep>;
>> +		};
>> +	};
>> +};
>> +
>> +&uart7 {
>> +	status = "disabled";
>> +};
>> +
>> +&{/wcn6750-pmu} {
> 
> label
> 
>> +	status = "disabled";
>> +};
>>
>> -- 
>> 2.34.1
>>
> 

Hi Dmitry,

Ack, I will clean this up in v2.

I will remove the unused connector/ports labels and add labels to the
existing nodes that the overlay needs to patch, including the WCN6750 PMU
node and the relevant PCI child node below pcie0_port.

I will then update the BT UART overlay to reference those labels directly
instead of reconstructing the full nested path or using the /wcn6750-pmu
path reference.

Thanks,
Rahul