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Thu, 22 Oct 2026 02:34:32 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c468a55c001sm84619866b.31.2026.10.22.02.34.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Oct 2026 02:34:31 -0700 (PDT) Message-ID: Date: Thu, 22 Oct 2026 11:34:29 +0200 X-Mailing-List: linux-bluetooth@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector To: Loic Poulain Cc: Manivannan Sadhasivam , Wei Deng , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-bluetooth@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_chezhou@quicinc.com, cheng.jiang@oss.qualcomm.com, shuai.zhang@oss.qualcomm.com, jinwang.li@oss.qualcomm.com, xiuzhuo.shang@oss.qualcomm.com, mengshi.wu@oss.qualcomm.com References: <0303224f-4c2c-46ec-9866-5ea1fd0fb4a3@oss.qualcomm.com> <20260825092715.5794-1-wei.deng@oss.qualcomm.com> <83b67ab2-ab68-427a-94aa-881454f457ba@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIyMDAzNyBTYWx0ZWRfX9zQzRmsx9nB8 3Kk20tVAhBtoGUmRMge9YrWqLsuM3ZTmd0U8o7Ax50bKJAiVj0Uod2bfiLHas4Y7xoeAhadwpUi biqJ17YTlMEKEhHaPtXGDbqBijYZSLw= X-Authority-Analysis: v=2.4 cv=ReAFmFtv c=1 sm=1 tr=0 ts=6ad9d8a9 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=9AbZo8Gtoo8lc68VITMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-GUID: rKfKmubmqVBxyKZQyd8f3aQU_vTQHMbr X-Proofpoint-ORIG-GUID: rKfKmubmqVBxyKZQyd8f3aQU_vTQHMbr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIyMDAzNyBTYWx0ZWRfX/Im1t2KdBzG4 0s/b3pgsBNfDHRM/97H6WHl8D+9dwFvvQI1pfQ0nFK7Jy6h+sB2nIm/uAZDQXlzeqBoz6Plh/7T 3Y/eF+1DEZtoQ0VBPT7Pm8ucJ892Djk1wqk2zjshwQr/gx3X13z9K3mCZlQJ1NwbzBwpFgyAVco GMVG6vwIcuOe4EzwWkWgBiYQj/9LxiAT1qdvPDvUwnnCHZxSXOfeQy825z5+F5TamWbT+SEfNvs GfnSzdTs4qLZ7OA8rsD++VBZjZaakCQdXo+7wxaJOtd6sCIve/EF4Z8KGpGvdymEWOj223jg0Y3 orCmgMDPBx3Jnl1c/rkPQ/7AJWmGJ57y1lCCI1GM4rkpr5yomUN6+2mVyS/xn09iLynLLNI3YkR BLDvWfYj5veR7XLpwzDgX0MVbnk/NeeiIYVWbgWRg/HTY9/pPtUIx5TI2vh9KsqDQHn3ZeLSScC 4ZgYu+5A+tDOCTmTGkA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-22_03,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 clxscore=1011 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610220037 On 10/13/26 10:13 AM, Loic Poulain wrote: > Hi Folks, > > On Mon, Sep 21, 2026 at 2:38 PM Konrad Dybcio > wrote: [...] >>>> We are adding M.2 Key E connector support for monaco-evk [2]. Konrad >>>> suggested moving the port/endpoint anchor nodes to the SoC DTSI >>>> (monaco.dtsi) for clean DTS layering, so that board files only need to >>>> fill in remote-endpoint for boards that actually have an M.2 connector. >>>> >>> >>> This means, the dummy port/endpoint node will always be present even when the >>> M.2 connector is not used. I don't see a compelling reason to do so. >> >> I don't really see a compelling reason to defer re-defining them to each >> device DT either.. > > Adding an empty port/endpoint at the SoC level is problematic for > uart, port is not always expected, this depends if the uart is exposed > through a connector or to an onboard device. So we may end with an > unconnected endpoint but still have a bluetooth subnode, which can be > a bit confusing... Also why adding a port/endpoint only for a specific > uart in the dts, and not for the others? This is a board/SoC level > choice to use a specific uart for M2 or not. >From my perspective it's removing boilerplate. Currently all USB and PCIe hosts already define their ports and endpoints in the SoC DTSI and if they're unconnected, then simply nothing happens. Both 'ports' and 'endpoints' are an abstract property that signify 'X can be related to Y' and I don't see how that's a problem here given UART is very much expected to be connected "somewhere" (with the "somewhere" perhaps being external/a pin header) Konrad