Error in Makefile for multiple files

Error in Makefile for multiple files

[Sagar Shinde]

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Hi all,

I have a module with 3 C files: smarthook.c restore.c backup.c

My Makefile code is:
-----------------------------------------------------
INCLUDEDIR = /usr/src/kernels/linux-2.6.12.1/include

CFLAGS = -D__KERNEL__ -DMODULE
CFLAGS += -I$(INCLUDEDIR)

TARGET = smarthook
OBJS = $(TARGET).o
SRC = smarthook.c backup.c restore.c

all: .depend $(TARGET).o

$(TARGET).o: $(SRC:.c=.o)
	$(LD) -r $^ -o $@

depend .depend dep:
	$(CC) $(CFLAGS) -M *.c > $@
-----------------------------------------------------

now though I am giving proper dependencies
 why am I not able to access global variables defined in one file
(smarthook.c)
 from other files, inspite of these variables being declared extern in other
files.

any suggestions?

Thanks in Advance.

Thanks n Regards,
Sagar Shinde









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Re: Error in Makefile for multiple files

[Steve Graegert]

On 8/29/05, Sagar Shinde <sagar.shinde@patni.com> wrote:
> 
> Hi all,
> 
> I have a module with 3 C files: smarthook.c restore.c backup.c
> 
> My Makefile code is:
> -----------------------------------------------------
> INCLUDEDIR = /usr/src/kernels/linux-2.6.12.1/include
> 
> CFLAGS = -D__KERNEL__ -DMODULE
> CFLAGS += -I$(INCLUDEDIR)
> 
> TARGET = smarthook
> OBJS = $(TARGET).o
> SRC = smarthook.c backup.c restore.c
> 
> all: .depend $(TARGET).o
> 
> $(TARGET).o: $(SRC:.c=.o)
>        $(LD) -r $^ -o $@
> 
> depend .depend dep:
>        $(CC) $(CFLAGS) -M *.c > $@
> -----------------------------------------------------
> 
> now though I am giving proper dependencies
>  why am I not able to access global variables defined in one file
> (smarthook.c)
>  from other files, inspite of these variables being declared extern in other
> files.

Although I am not a make guru I can't see something unusual in this
fairly simple makefile.  Does the module compile and link properly
without using a makefile, i.e. compiling and linking manually?  Is the
contents of .depend exactly what you expected after calling make?

Please, let us know if you have results you want to share.
 
Regards

	\Steve

--

Steve Graegert <graegerts@gmail.com>
Software Consultancy {C/C++ && Java && .NET}
Mobile: +49 (176)  21248869
Office: +49 (9131) 7126409

Re: Error in Makefile for multiple files

[K Anandan]

Sagar Shinde

On Tue, 2005-08-30 at 04:01, Steve Graegert wrote:
> On 8/29/05, Sagar Shinde <sagar.shinde@patni.com> wrote:
> > 
> > Hi all,
> > 
> > I have a module with 3 C files: smarthook.c restore.c backup.c
> > 
> > My Makefile code is:
> > -----------------------------------------------------
> > INCLUDEDIR = /usr/src/kernels/linux-2.6.12.1/include
> > 
> > CFLAGS = -D__KERNEL__ -DMODULE
> > CFLAGS += -I$(INCLUDEDIR)
> > 
> > TARGET = smarthook
> > OBJS = $(TARGET).o
> > SRC = smarthook.c backup.c restore.c
> > 
> > all: .depend $(TARGET).o
Here you change 
all: .depend $(TARGET)

> > 
> > $(TARGET).o: $(SRC:.c=.o)
Here you change 
$(TARGET) : $(SRC:.c=.o)

> >        $(LD) -r $^ -o $@
> > 
> > depend .depend dep:
> >        $(CC) $(CFLAGS) -M *.c > $@
> > -----------------------------------------------------
> > 
> > now though I am giving proper dependencies
> >  why am I not able to access global variables defined in one file
> > (smarthook.c)
> >  from other files, inspite of these variables being declared extern in other
> > files.
> 
> Although I am not a make guru I can't see something unusual in this
> fairly simple makefile.  Does the module compile and link properly
> without using a makefile, i.e. compiling and linking manually?  Is the
> contents of .depend exactly what you expected after calling make?
> 
> Please, let us know if you have results you want to share.
>  
> Regards
> 
> 	\Steve
> 
> --
> 
> Steve Graegert <graegerts@gmail.com>
> Software Consultancy {C/C++ && Java && .NET}
> Mobile: +49 (176)  21248869
> Office: +49 (9131) 7126409
> -
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-- 

Your program will work fine

Ananth