Error in Makefile for multiple files

["Sagar Shinde" <sagar.shinde@patni.com>]

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Hi all,

I have a module with 3 C files: smarthook.c restore.c backup.c

My Makefile code is:
-----------------------------------------------------
INCLUDEDIR = /usr/src/kernels/linux-2.6.12.1/include

CFLAGS = -D__KERNEL__ -DMODULE
CFLAGS += -I$(INCLUDEDIR)

TARGET = smarthook
OBJS = $(TARGET).o
SRC = smarthook.c backup.c restore.c

all: .depend $(TARGET).o

$(TARGET).o: $(SRC:.c=.o)
	$(LD) -r $^ -o $@

depend .depend dep:
	$(CC) $(CFLAGS) -M *.c > $@
-----------------------------------------------------

now though I am giving proper dependencies
 why am I not able to access global variables defined in one file
(smarthook.c)
 from other files, inspite of these variables being declared extern in other
files.

any suggestions?

Thanks in Advance.

Thanks n Regards,
Sagar Shinde









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