[PATCH 1/3] can: flexcan: Add ls1021a flexcan device entry

[PATCH 1/3] can: flexcan: Add ls1021a flexcan device entry

[Bhupesh Sharma]

This patch adds ls1021a flexcan device entry to the flexcan driver code.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 drivers/net/can/flexcan.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 80c46ad..437d6bd 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -267,10 +267,15 @@ static struct flexcan_devtype_data fsl_imx28_devtype_data;
 static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 	.features = FLEXCAN_HAS_V10_FEATURES,
 };
+
 static struct flexcan_devtype_data fsl_vf610_devtype_data = {
 	.features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES,
 };
 
+static struct flexcan_devtype_data fsl_ls1021a_devtype_data = {
+	.features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES,
+};
+
 static const struct can_bittiming_const flexcan_bittiming_const = {
 	.name = DRV_NAME,
 	.tseg1_min = 4,
@@ -1140,6 +1145,8 @@ static void unregister_flexcandev(struct net_device *dev)
 static const struct of_device_id flexcan_of_match[] = {
 	{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
 	{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
+	{ .compatible = "fsl,ls1021a-flexcan",
+	  .data = &fsl_ls1021a_devtype_data, },
 	{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
 	{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
 	{ /* sentinel */ },
-- 
1.7.9.5

[PATCH 2/3] net: can: Remodel FlexCAN register read/write APIs for BE instances

[Bhupesh Sharma]

From: Sakar Arora <Sakar.Arora@freescale.com>

The FlexCAN IP on certain SoCs like (Freescale's LS1021A) is modelled
in a big-endian fashion, i.e. the registers and the message buffers are
organized in a BE way.

More details about the LS1021A SoC can be seen here:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=LS1021A&nodeId=018rH325E4017B#

This patch ensures that the register read/write APIs are remodelled to
address such cases, while ensuring that existing platforms (where the
FlexCAN IP was modelled in LE way) do not break.

Tested on LS1021A-QDS board.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
---
 drivers/net/can/flexcan.c |  208 ++++++++++++++++++++++++++-------------------
 1 file changed, 119 insertions(+), 89 deletions(-)

diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 437d6bd..3d91549 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -258,6 +258,10 @@ struct flexcan_priv {
 	struct flexcan_platform_data *pdata;
 	const struct flexcan_devtype_data *devtype_data;
 	struct regulator *reg_xceiver;
+
+	/* Read and Write APIs */
+	u32 (*read)(void __iomem *addr);
+	void (*write)(u32 val, void __iomem *addr);
 };
 
 static struct flexcan_devtype_data fsl_p1010_devtype_data = {
@@ -289,32 +293,38 @@ static const struct can_bittiming_const flexcan_bittiming_const = {
 };
 
 /*
- * Abstract off the read/write for arm versus ppc. This
- * assumes that PPC uses big-endian registers and everything
- * else uses little-endian registers, independent of CPU
- * endianess.
+ * FlexCAN module is essentially modelled as a little-endian IP in most
+ * SoCs, i.e the registers as well as the message buffer areas are
+ * implemented in a little-endian fashion.
+ *
+ * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
+ * module in a big-endian fashion (i.e the registers as well as the
+ * message buffer areas are implemented in a big-endian way).
+ *
+ * In addition, the FlexCAN module can be found on SoCs having ARM or
+ * PPC cores. So, we need to abstract off the register read/write
+ * functions, ensuring that these cater to all the combinations of module
+ * endianness and underlying CPU endianness.
  */
-#if defined(CONFIG_PPC)
-static inline u32 flexcan_read(void __iomem *addr)
+static inline u32 flexcan_read_le(void __iomem *addr)
 {
-	return in_be32(addr);
+	return ioread32(addr);
 }
 
-static inline void flexcan_write(u32 val, void __iomem *addr)
+static inline void flexcan_write_le(u32 val, void __iomem *addr)
 {
-	out_be32(addr, val);
+	iowrite32(val, addr);
 }
-#else
-static inline u32 flexcan_read(void __iomem *addr)
+
+static inline u32 flexcan_read_be(void __iomem *addr)
 {
-	return readl(addr);
+	return ioread32be(addr);
 }
 
-static inline void flexcan_write(u32 val, void __iomem *addr)
+static inline void flexcan_write_be(u32 val, void __iomem *addr)
 {
-	writel(val, addr);
+	iowrite32be(val, addr);
 }
-#endif
 
 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 {
@@ -345,14 +355,14 @@ static int flexcan_chip_enable(struct flexcan_priv *priv)
 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 	u32 reg;
 
-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
 	reg &= ~FLEXCAN_MCR_MDIS;
-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
 
-	while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 		udelay(10);
 
-	if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
+	if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 		return -ETIMEDOUT;
 
 	return 0;
@@ -364,14 +374,14 @@ static int flexcan_chip_disable(struct flexcan_priv *priv)
 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 	u32 reg;
 
-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
 	reg |= FLEXCAN_MCR_MDIS;
-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
 
-	while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 		udelay(10);
 
-	if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 		return -ETIMEDOUT;
 
 	return 0;
@@ -383,14 +393,14 @@ static int flexcan_chip_freeze(struct flexcan_priv *priv)
 	unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
 	u32 reg;
 
-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
 	reg |= FLEXCAN_MCR_HALT;
-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
 
-	while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 		udelay(100);
 
-	if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 		return -ETIMEDOUT;
 
 	return 0;
@@ -402,14 +412,14 @@ static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 	u32 reg;
 
-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
 	reg &= ~FLEXCAN_MCR_HALT;
-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
 
-	while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 		udelay(10);
 
-	if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
+	if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 		return -ETIMEDOUT;
 
 	return 0;
@@ -420,23 +430,22 @@ static int flexcan_chip_softreset(struct flexcan_priv *priv)
 	struct flexcan_regs __iomem *regs = priv->base;
 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 
-	flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
-	while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
+	priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
+	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 		udelay(10);
 
-	if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
+	if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 		return -ETIMEDOUT;
 
 	return 0;
 }
 
-
 static int __flexcan_get_berr_counter(const struct net_device *dev,
 				      struct can_berr_counter *bec)
 {
 	const struct flexcan_priv *priv = netdev_priv(dev);
 	struct flexcan_regs __iomem *regs = priv->base;
-	u32 reg = flexcan_read(&regs->ecr);
+	u32 reg = priv->read(&regs->ecr);
 
 	bec->txerr = (reg >> 0) & 0xff;
 	bec->rxerr = (reg >> 8) & 0xff;
@@ -492,24 +501,24 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
 	if (cf->can_dlc > 0) {
 		u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
-		flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
+		priv->write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
 	}
 	if (cf->can_dlc > 3) {
 		u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
-		flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
+		priv->write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
 	}
 
 	can_put_echo_skb(skb, dev, 0);
 
-	flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
-	flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
+	priv->write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
+	priv->write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
 
 	/* Errata ERR005829 step8:
 	 * Write twice INACTIVE(0x8) code to first MB.
 	 */
-	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 		      &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
-	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 		      &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
 
 	return NETDEV_TX_OK;
@@ -635,8 +644,8 @@ static void flexcan_read_fifo(const struct net_device *dev,
 	struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
 	u32 reg_ctrl, reg_id;
 
-	reg_ctrl = flexcan_read(&mb->can_ctrl);
-	reg_id = flexcan_read(&mb->can_id);
+	reg_ctrl = priv->read(&mb->can_ctrl);
+	reg_id = priv->read(&mb->can_id);
 	if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 		cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 	else
@@ -646,12 +655,12 @@ static void flexcan_read_fifo(const struct net_device *dev,
 		cf->can_id |= CAN_RTR_FLAG;
 	cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 
-	*(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
-	*(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
+	*(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
+	*(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
 
 	/* mark as read */
-	flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
-	flexcan_read(&regs->timer);
+	priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
+	priv->read(&regs->timer);
 }
 
 static int flexcan_read_frame(struct net_device *dev)
@@ -689,17 +698,17 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
 	 * The error bits are cleared on read,
 	 * use saved value from irq handler.
 	 */
-	reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
+	reg_esr = priv->read(&regs->esr) | priv->reg_esr;
 
 	/* handle state changes */
 	work_done += flexcan_poll_state(dev, reg_esr);
 
 	/* handle RX-FIFO */
-	reg_iflag1 = flexcan_read(&regs->iflag1);
+	reg_iflag1 = priv->read(&regs->iflag1);
 	while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
 	       work_done < quota) {
 		work_done += flexcan_read_frame(dev);
-		reg_iflag1 = flexcan_read(&regs->iflag1);
+		reg_iflag1 = priv->read(&regs->iflag1);
 	}
 
 	/* report bus errors */
@@ -709,8 +718,8 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
 	if (work_done < quota) {
 		napi_complete(napi);
 		/* enable IRQs */
-		flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
-		flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
+		priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+		priv->write(priv->reg_ctrl_default, &regs->ctrl);
 	}
 
 	return work_done;
@@ -724,11 +733,11 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
 	struct flexcan_regs __iomem *regs = priv->base;
 	u32 reg_iflag1, reg_esr;
 
-	reg_iflag1 = flexcan_read(&regs->iflag1);
-	reg_esr = flexcan_read(&regs->esr);
+	reg_iflag1 = priv->read(&regs->iflag1);
+	reg_esr = priv->read(&regs->esr);
 	/* ACK all bus error and state change IRQ sources */
 	if (reg_esr & FLEXCAN_ESR_ALL_INT)
-		flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
+		priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 
 	/*
 	 * schedule NAPI in case of:
@@ -744,16 +753,16 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
 		 * save them for later use.
 		 */
 		priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
-		flexcan_write(FLEXCAN_IFLAG_DEFAULT &
+		priv->write(FLEXCAN_IFLAG_DEFAULT &
 			~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
-		flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+		priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
 		       &regs->ctrl);
 		napi_schedule(&priv->napi);
 	}
 
 	/* FIFO overflow */
 	if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
-		flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
+		priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
 		dev->stats.rx_over_errors++;
 		dev->stats.rx_errors++;
 	}
@@ -764,9 +773,9 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
 		stats->tx_packets++;
 		can_led_event(dev, CAN_LED_EVENT_TX);
 		/* after sending a RTR frame mailbox is in RX mode */
-		flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 			      &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
-		flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
+		priv->write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
 		netif_wake_queue(dev);
 	}
 
@@ -780,7 +789,7 @@ static void flexcan_set_bittiming(struct net_device *dev)
 	struct flexcan_regs __iomem *regs = priv->base;
 	u32 reg;
 
-	reg = flexcan_read(&regs->ctrl);
+	reg = priv->read(&regs->ctrl);
 	reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
 		 FLEXCAN_CTRL_RJW(0x3) |
 		 FLEXCAN_CTRL_PSEG1(0x7) |
@@ -804,11 +813,11 @@ static void flexcan_set_bittiming(struct net_device *dev)
 		reg |= FLEXCAN_CTRL_SMP;
 
 	netdev_info(dev, "writing ctrl=0x%08x\n", reg);
-	flexcan_write(reg, &regs->ctrl);
+	priv->write(reg, &regs->ctrl);
 
 	/* print chip status */
 	netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
-		   flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
+		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
 }
 
 /*
@@ -848,14 +857,14 @@ static int flexcan_chip_start(struct net_device *dev)
 	 * disable local echo
 	 *
 	 */
-	reg_mcr = flexcan_read(&regs->mcr);
+	reg_mcr = priv->read(&regs->mcr);
 	reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
 	reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
 		FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
 		FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
 		FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
 	netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
-	flexcan_write(reg_mcr, &regs->mcr);
+	priv->write(reg_mcr, &regs->mcr);
 
 	/*
 	 * CTRL
@@ -869,7 +878,7 @@ static int flexcan_chip_start(struct net_device *dev)
 	 * enable bus off interrupt
 	 * (== FLEXCAN_CTRL_ERR_STATE)
 	 */
-	reg_ctrl = flexcan_read(&regs->ctrl);
+	reg_ctrl = priv->read(&regs->ctrl);
 	reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
 	reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
 		FLEXCAN_CTRL_ERR_STATE;
@@ -887,29 +896,29 @@ static int flexcan_chip_start(struct net_device *dev)
 	/* save for later use */
 	priv->reg_ctrl_default = reg_ctrl;
 	netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
-	flexcan_write(reg_ctrl, &regs->ctrl);
+	priv->write(reg_ctrl, &regs->ctrl);
 
 	/* clear and invalidate all mailboxes first */
 	for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) {
-		flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
+		priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
 			      &regs->cantxfg[i].can_ctrl);
 	}
 
 	/* Errata ERR005829: mark first TX mailbox as INACTIVE */
-	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 		      &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
 
 	/* mark TX mailbox as INACTIVE */
-	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 		      &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
 
 	/* acceptance mask/acceptance code (accept everything) */
-	flexcan_write(0x0, &regs->rxgmask);
-	flexcan_write(0x0, &regs->rx14mask);
-	flexcan_write(0x0, &regs->rx15mask);
+	priv->write(0x0, &regs->rxgmask);
+	priv->write(0x0, &regs->rx14mask);
+	priv->write(0x0, &regs->rx15mask);
 
 	if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
-		flexcan_write(0x0, &regs->rxfgmask);
+		priv->write(0x0, &regs->rxfgmask);
 
 	/*
 	 * On Vybrid, disable memory error detection interrupts
@@ -924,16 +933,16 @@ static int flexcan_chip_start(struct net_device *dev)
 		 * and Correction of Memory Errors" to write to
 		 * MECR register
 		 */
-		reg_crl2 = flexcan_read(&regs->crl2);
+		reg_crl2 = priv->read(&regs->crl2);
 		reg_crl2 |= FLEXCAN_CRL2_ECRWRE;
-		flexcan_write(reg_crl2, &regs->crl2);
+		priv->write(reg_crl2, &regs->crl2);
 
-		reg_mecr = flexcan_read(&regs->mecr);
+		reg_mecr = priv->read(&regs->mecr);
 		reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
-		flexcan_write(reg_mecr, &regs->mecr);
+		priv->write(reg_mecr, &regs->mecr);
 		reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
 				FLEXCAN_MECR_FANCEI_MSK);
-		flexcan_write(reg_mecr, &regs->mecr);
+		priv->write(reg_mecr, &regs->mecr);
 	}
 
 	err = flexcan_transceiver_enable(priv);
@@ -948,11 +957,11 @@ static int flexcan_chip_start(struct net_device *dev)
 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
 
 	/* enable FIFO interrupts */
-	flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+	priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
 
 	/* print chip status */
 	netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
-		   flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
+		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
 
 	return 0;
 
@@ -979,8 +988,8 @@ static void flexcan_chip_stop(struct net_device *dev)
 	flexcan_chip_disable(priv);
 
 	/* Disable all interrupts */
-	flexcan_write(0, &regs->imask1);
-	flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+	priv->write(0, &regs->imask1);
+	priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
 		      &regs->ctrl);
 
 	flexcan_transceiver_disable(priv);
@@ -1098,26 +1107,26 @@ static int register_flexcandev(struct net_device *dev)
 	err = flexcan_chip_disable(priv);
 	if (err)
 		goto out_disable_per;
-	reg = flexcan_read(&regs->ctrl);
+	reg = priv->read(&regs->ctrl);
 	reg |= FLEXCAN_CTRL_CLK_SRC;
-	flexcan_write(reg, &regs->ctrl);
+	priv->write(reg, &regs->ctrl);
 
 	err = flexcan_chip_enable(priv);
 	if (err)
 		goto out_chip_disable;
 
 	/* set freeze, halt and activate FIFO, restrict register access */
-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
 	reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
 		FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
 
 	/*
 	 * Currently we only support newer versions of this core
 	 * featuring a RX FIFO. Older cores found on some Coldfire
 	 * derivates are not yet supported.
 	 */
-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
 	if (!(reg & FLEXCAN_MCR_FEN)) {
 		netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
 		err = -ENODEV;
@@ -1170,6 +1179,8 @@ static int flexcan_probe(struct platform_device *pdev)
 	void __iomem *base;
 	int err, irq;
 	u32 clock_freq = 0;
+	/* Default case for most ARM based FSL SoC having BE FlexCAN IP */
+	bool core_is_little = true, module_is_little = false;
 
 	if (pdev->dev.of_node)
 		of_property_read_u32(pdev->dev.of_node,
@@ -1218,6 +1229,25 @@ static int flexcan_probe(struct platform_device *pdev)
 	dev->flags |= IFF_ECHO;
 
 	priv = netdev_priv(dev);
+
+	if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+		core_is_little = false;
+
+	if (of_property_read_bool(dev->dev.of_node, "little-endian"))
+		module_is_little = true;
+
+	if ((core_is_little && module_is_little) ||
+	    (!core_is_little && !module_is_little)) {
+		priv->read = flexcan_read_le;
+		priv->write = flexcan_write_le;
+	}
+
+	if ((!core_is_little && module_is_little) ||
+	    (core_is_little && !module_is_little)) {
+		priv->read = flexcan_read_be;
+		priv->write = flexcan_write_be;
+	}
+
 	priv->can.clock.freq = clock_freq;
 	priv->can.bittiming_const = &flexcan_bittiming_const;
 	priv->can.do_set_mode = flexcan_set_mode;
-- 
1.7.9.5

[PATCH 3/3] can: flexcan: Add support for non RX-FIFO mode and ERRATA ERR005829

[Bhupesh Sharma]

This patch adds support for non RX-FIFO (legacy) mode and ERRATA
ERR005829 handling in flexcan driver.

Both these features are now selectable via Kconfig entries and hence can
be turned-on/off as per a SoC feature set availability.

ERRATA ERR005829 (A-008965) description:
---------------------------------------
FlexCAN RxFIFO feature is not supported

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
---
 drivers/net/can/flexcan.c |  252 ++++++++++++++++++++++++++++++++++++---------
 1 file changed, 203 insertions(+), 49 deletions(-)

diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 3d91549..4bb7fc6 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -59,6 +59,7 @@
 #define FLEXCAN_MCR_WAK_SRC		BIT(19)
 #define FLEXCAN_MCR_DOZE		BIT(18)
 #define FLEXCAN_MCR_SRX_DIS		BIT(17)
+#define FLEXCAN_MCR_SRX_EN		~(BIT(17))
 #define FLEXCAN_MCR_BCC			BIT(16)
 #define FLEXCAN_MCR_LPRIO_EN		BIT(13)
 #define FLEXCAN_MCR_AEN			BIT(12)
@@ -146,16 +147,26 @@
 	 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
 
 /* FLEXCAN interrupt flag register (IFLAG) bits */
+#ifdef CONFIG_CAN_FLEXCAN_ERRATA_ERR005829
 /* Errata ERR005829 step7: Reserve first valid MB */
 #define FLEXCAN_TX_BUF_RESERVED		8
 #define FLEXCAN_TX_BUF_ID		9
+#else
+#define FLEXCAN_TX_BUF_ID		8
+#endif
 #define FLEXCAN_IFLAG_BUF(x)		BIT(x)
 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW	BIT(7)
 #define FLEXCAN_IFLAG_RX_FIFO_WARN	BIT(6)
 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE	BIT(5)
+#ifdef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
 #define FLEXCAN_IFLAG_DEFAULT \
 	(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
 	 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
+#else
+#define FLEXCAN_IFLAG_DEFAULT \
+	(FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
+#define FLEXCAN_IFLAG_RXMASK	((1 << FLEXCAN_TX_BUF_ID) - 1)
+#endif
 
 /* FLEXCAN message buffers */
 #define FLEXCAN_MB_CNT_CODE(x)		(((x) & 0xf) << 24)
@@ -198,6 +209,7 @@
 #define FLEXCAN_HAS_V10_FEATURES	BIT(1) /* For core version >= 10 */
 #define FLEXCAN_HAS_BROKEN_ERR_STATE	BIT(2) /* [TR]WRN_INT not connected */
 #define FLEXCAN_HAS_MECR_FEATURES	BIT(3) /* Memory error detection */
+#define FLEXCAN_USES_RX_MB		BIT(4) /* Use msg-buf to rx frames */
 
 /* Structure of the message buffer */
 struct flexcan_mb {
@@ -277,7 +289,11 @@ static struct flexcan_devtype_data fsl_vf610_devtype_data = {
 };
 
 static struct flexcan_devtype_data fsl_ls1021a_devtype_data = {
-	.features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES,
+	.features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES
+#ifdef CONFIG_CAN_FLEXCAN_ERRATA_ERR008965
+	| FLEXCAN_USES_RX_MB
+#endif
+	,
 };
 
 static const struct can_bittiming_const flexcan_bittiming_const = {
@@ -414,6 +430,7 @@ static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 
 	reg = priv->read(&regs->mcr);
 	reg &= ~FLEXCAN_MCR_HALT;
+	reg &= ~FLEXCAN_MCR_FRZ;
 	priv->write(reg, &regs->mcr);
 
 	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
@@ -512,7 +529,7 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
 	priv->write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
 	priv->write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
-
+#ifdef CONFIG_CAN_FLEXCAN_ERRATA_ERR005829
 	/* Errata ERR005829 step8:
 	 * Write twice INACTIVE(0x8) code to first MB.
 	 */
@@ -520,6 +537,7 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 		      &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 		      &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
+#endif
 
 	return NETDEV_TX_OK;
 }
@@ -663,7 +681,34 @@ static void flexcan_read_fifo(const struct net_device *dev,
 	priv->read(&regs->timer);
 }
 
-static int flexcan_read_frame(struct net_device *dev)
+static void flexcan_read_mailbox(const struct net_device *dev,
+				 struct can_frame *cf, u32 mailbox)
+{
+	const struct flexcan_priv *priv = netdev_priv(dev);
+	struct flexcan_regs __iomem *regs = priv->base;
+	struct flexcan_mb __iomem *mb = &regs->cantxfg[mailbox];
+	u32 reg_ctrl, reg_id;
+
+	reg_ctrl = priv->read(&mb->can_ctrl);
+	reg_id = priv->read(&mb->can_id);
+	if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
+		cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
+	else
+		cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
+
+	if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
+		cf->can_id |= CAN_RTR_FLAG;
+	cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
+
+	*(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
+	*(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
+
+	/* mark as read */
+	priv->write(BIT(mailbox), &regs->iflag1);
+	priv->read(&regs->timer);
+}
+
+static int flexcan_read_frame_fifo_mode(struct net_device *dev)
 {
 	struct net_device_stats *stats = &dev->stats;
 	struct can_frame *cf;
@@ -676,6 +721,31 @@ static int flexcan_read_frame(struct net_device *dev)
 	}
 
 	flexcan_read_fifo(dev, cf);
+
+	netif_receive_skb(skb);
+
+	stats->rx_packets++;
+	stats->rx_bytes += cf->can_dlc;
+
+	can_led_event(dev, CAN_LED_EVENT_RX);
+
+	return 1;
+}
+
+static int flexcan_read_frame_legacy_mode(struct net_device *dev, u32 mailbox)
+{
+	struct net_device_stats *stats = &dev->stats;
+	struct can_frame *cf;
+	struct sk_buff *skb;
+
+	skb = alloc_can_skb(dev, &cf);
+	if (unlikely(!skb)) {
+		stats->rx_dropped++;
+		return 0;
+	}
+
+	flexcan_read_mailbox(dev, cf, mailbox);
+
 	netif_receive_skb(skb);
 
 	stats->rx_packets++;
@@ -703,12 +773,29 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
 	/* handle state changes */
 	work_done += flexcan_poll_state(dev, reg_esr);
 
-	/* handle RX-FIFO */
-	reg_iflag1 = priv->read(&regs->iflag1);
-	while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
-	       work_done < quota) {
-		work_done += flexcan_read_frame(dev);
+	if (!(priv->devtype_data->features & FLEXCAN_USES_RX_MB)) {
+		/* handle RX-FIFO */
 		reg_iflag1 = priv->read(&regs->iflag1);
+		while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
+		       work_done < quota) {
+			work_done += flexcan_read_frame_fifo_mode(dev);
+			reg_iflag1 = priv->read(&regs->iflag1);
+		}
+	} else {
+		unsigned long iflag1;
+		u32 mailbox;
+
+		/* handle RX-Buffers */
+		reg_iflag1 = priv->read(&regs->iflag1);
+		iflag1 = reg_iflag1 & FLEXCAN_IFLAG_RXMASK;
+		while ((reg_iflag1 & FLEXCAN_IFLAG_RXMASK) &&
+		       work_done < quota) {
+			mailbox = find_first_bit(&iflag1,
+						 (FLEXCAN_TX_BUF_ID - 1));
+			work_done += flexcan_read_frame_legacy_mode(dev,
+								    mailbox);
+			reg_iflag1 = priv->read(&regs->iflag1);
+		}
 	}
 
 	/* report bus errors */
@@ -718,7 +805,12 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
 	if (work_done < quota) {
 		napi_complete(napi);
 		/* enable IRQs */
-		priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+		if (!(priv->devtype_data->features & FLEXCAN_USES_RX_MB))
+			priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+		else
+			priv->write(FLEXCAN_IFLAG_DEFAULT |
+				    FLEXCAN_IFLAG_RXMASK, &regs->imask1);
+
 		priv->write(priv->reg_ctrl_default, &regs->ctrl);
 	}
 
@@ -745,26 +837,43 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
 	 * - state change IRQ
 	 * - bus error IRQ and bus error reporting is activated
 	 */
-	if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
-	    (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
-	    flexcan_has_and_handle_berr(priv, reg_esr)) {
-		/*
-		 * The error bits are cleared on read,
-		 * save them for later use.
-		 */
-		priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
-		priv->write(FLEXCAN_IFLAG_DEFAULT &
-			~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
-		priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
-		       &regs->ctrl);
-		napi_schedule(&priv->napi);
-	}
+	if (!(priv->devtype_data->features & FLEXCAN_USES_RX_MB)) {
+		if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
+		    (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
+		    flexcan_has_and_handle_berr(priv, reg_esr)) {
+			/* The error bits are cleared on read,
+			 * save them for later use.
+			 */
+			priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
+			priv->write(FLEXCAN_IFLAG_DEFAULT &
+				    ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE,
+				    &regs->imask1);
+			priv->write(priv->reg_ctrl_default &
+				    ~FLEXCAN_CTRL_ERR_ALL, &regs->ctrl);
+			napi_schedule(&priv->napi);
+		}
 
-	/* FIFO overflow */
-	if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
-		priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
-		dev->stats.rx_over_errors++;
-		dev->stats.rx_errors++;
+		/* FIFO overflow */
+		if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
+			priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
+				    &regs->iflag1);
+			dev->stats.rx_over_errors++;
+			dev->stats.rx_errors++;
+		}
+	} else {
+		if ((reg_iflag1 & FLEXCAN_IFLAG_RXMASK) ||
+		    (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
+		    flexcan_has_and_handle_berr(priv, reg_esr)) {
+			/* The error bits are cleared on read,
+			 * save them for later use.
+			 */
+			priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
+			priv->write(priv->reg_ctrl_default &
+				    ~FLEXCAN_CTRL_ERR_ALL, &regs->ctrl);
+			priv->write(FLEXCAN_IFLAG_DEFAULT &
+				    ~FLEXCAN_IFLAG_RXMASK, &regs->imask1);
+			napi_schedule(&priv->napi);
+		}
 	}
 
 	/* transmission complete interrupt */
@@ -772,9 +881,12 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
 		stats->tx_bytes += can_get_echo_skb(dev, 0);
 		stats->tx_packets++;
 		can_led_event(dev, CAN_LED_EVENT_TX);
-		/* after sending a RTR frame mailbox is in RX mode */
-		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
-			      &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
+
+		if (priv->devtype_data->features & FLEXCAN_USES_RX_MB)
+			/* after sending a RTR frame mailbox is in RX mode */
+			priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
+				    &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
+
 		priv->write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
 		netif_wake_queue(dev);
 	}
@@ -859,10 +971,19 @@ static int flexcan_chip_start(struct net_device *dev)
 	 */
 	reg_mcr = priv->read(&regs->mcr);
 	reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
-	reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
-		FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
-		FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
-		FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
+	if (!(priv->devtype_data->features & FLEXCAN_USES_RX_MB)) {
+		reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN |
+			   FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
+			   FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IDAM_C |
+			   FLEXCAN_MCR_SRX_DIS |
+			   FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
+	} else {
+		reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
+			   FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
+			   FLEXCAN_MCR_IDAM_A |
+			   FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
+		reg_mcr &= FLEXCAN_MCR_SRX_EN;
+	}
 	netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
 	priv->write(reg_mcr, &regs->mcr);
 
@@ -899,26 +1020,45 @@ static int flexcan_chip_start(struct net_device *dev)
 	priv->write(reg_ctrl, &regs->ctrl);
 
 	/* clear and invalidate all mailboxes first */
-	for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) {
-		priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
-			      &regs->cantxfg[i].can_ctrl);
+	if (priv->devtype_data->features & FLEXCAN_USES_RX_MB) {
+		for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) {
+			priv->write(0, &regs->cantxfg[i].can_ctrl);
+			priv->write(0, &regs->cantxfg[i].can_id);
+			priv->write(0, &regs->cantxfg[i].data[0]);
+			priv->write(0, &regs->cantxfg[i].data[1]);
+
+			/* put MB into rx queue */
+			priv->write(FLEXCAN_MB_CNT_CODE(0x4),
+				    &regs->cantxfg[i].can_ctrl);
+		}
+	} else {
+		for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++)
+			priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
+				    &regs->cantxfg[i].can_ctrl);
 	}
 
+#ifdef CONFIG_CAN_FLEXCAN_ERRATA_ERR005829
 	/* Errata ERR005829: mark first TX mailbox as INACTIVE */
 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 		      &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
+#endif
 
-	/* mark TX mailbox as INACTIVE */
-	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
-		      &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
+	if (!(priv->devtype_data->features & FLEXCAN_USES_RX_MB))
+		/* mark TX mailbox as INACTIVE */
+		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
+			    &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
 
 	/* acceptance mask/acceptance code (accept everything) */
 	priv->write(0x0, &regs->rxgmask);
 	priv->write(0x0, &regs->rx14mask);
 	priv->write(0x0, &regs->rx15mask);
 
-	if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
+	if (!(priv->devtype_data->features & FLEXCAN_USES_RX_MB)) {
+		if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
+			priv->write(0x0, &regs->rxfgmask);
+	} else {
 		priv->write(0x0, &regs->rxfgmask);
+	}
 
 	/*
 	 * On Vybrid, disable memory error detection interrupts
@@ -957,7 +1097,11 @@ static int flexcan_chip_start(struct net_device *dev)
 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
 
 	/* enable FIFO interrupts */
-	priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+	if (!(priv->devtype_data->features & FLEXCAN_USES_RX_MB))
+		priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+	else
+		priv->write(FLEXCAN_IFLAG_DEFAULT | FLEXCAN_IFLAG_RXMASK,
+			    &regs->imask1);
 
 	/* print chip status */
 	netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
@@ -1117,8 +1261,12 @@ static int register_flexcandev(struct net_device *dev)
 
 	/* set freeze, halt and activate FIFO, restrict register access */
 	reg = priv->read(&regs->mcr);
-	reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
-		FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
+	if (!(priv->devtype_data->features & FLEXCAN_USES_RX_MB))
+		reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
+			FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
+	else
+		reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV;
+
 	priv->write(reg, &regs->mcr);
 
 	/*
@@ -1127,10 +1275,16 @@ static int register_flexcandev(struct net_device *dev)
 	 * derivates are not yet supported.
 	 */
 	reg = priv->read(&regs->mcr);
-	if (!(reg & FLEXCAN_MCR_FEN)) {
-		netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
-		err = -ENODEV;
-		goto out_chip_disable;
+
+	if (!(priv->devtype_data->features & FLEXCAN_USES_RX_MB)) {
+		if (!(reg & FLEXCAN_MCR_FEN)) {
+			netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
+			err = -ENODEV;
+			goto out_chip_disable;
+		}
+	} else {
+		if (!(reg & FLEXCAN_MCR_FEN))
+			netdev_info(dev, "Legacy mode (non-RX FIFO) enabled\n");
 	}
 
 	err = register_candev(dev);
-- 
1.7.9.5

Re: [PATCH 3/3] can: flexcan: Add support for non RX-FIFO mode and ERRATA ERR005829

[Marc Kleine-Budde]

[-- Attachment #1: Type: text/plain, Size: 703 bytes --]

On 04/09/2015 05:24 PM, Bhupesh Sharma wrote:
> This patch adds support for non RX-FIFO (legacy) mode and ERRATA
> ERR005829 handling in flexcan driver.

What about
25e924450fcb can: flexcan: implement workaround for errata ERR005829
?
> Both these features are now selectable via Kconfig entries and hence can
> be turned-on/off as per a SoC feature set availability.

Sorry Kconfig is not an option here.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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RE: [PATCH 3/3] can: flexcan: Add support for non RX-FIFO mode and ERRATA ERR005829

[bhupesh.sharma]

> -----Original Message-----
> From: Marc Kleine-Budde [mailto:mkl@pengutronix.de]
> On 04/09/2015 05:24 PM, Bhupesh Sharma wrote:
> > This patch adds support for non RX-FIFO (legacy) mode and ERRATA
> > ERR005829 handling in flexcan driver.
> 
> What about
> 25e924450fcb can: flexcan: implement workaround for errata ERR005829 ?

Oops, looks like a typo. Will fix in V2.

> > Both these features are now selectable via Kconfig entries and hence
> > can be turned-on/off as per a SoC feature set availability.
> 
> Sorry Kconfig is not an option here.

I meant the defconfig here. By default the errata handling would be turned-off
in the Kconfig.

Any other ideas?


Regards,
Bhupesh

Re: [PATCH 3/3] can: flexcan: Add support for non RX-FIFO mode and ERRATA ERR005829

[Marc Kleine-Budde]

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On 04/09/2015 05:45 PM, bhupesh.sharma@freescale.com wrote:
>> -----Original Message-----
>> From: Marc Kleine-Budde [mailto:mkl@pengutronix.de]
>> On 04/09/2015 05:24 PM, Bhupesh Sharma wrote:
>>> This patch adds support for non RX-FIFO (legacy) mode and ERRATA
>>> ERR005829 handling in flexcan driver.
>>
>> What about
>> 25e924450fcb can: flexcan: implement workaround for errata ERR005829 ?
> 
> Oops, looks like a typo. Will fix in V2.
> 
>>> Both these features are now selectable via Kconfig entries and hence
>>> can be turned-on/off as per a SoC feature set availability.
>>
>> Sorry Kconfig is not an option here.
> 
> I meant the defconfig here. By default the errata handling would be turned-off
> in the Kconfig.
> 
> Any other ideas?

Please look at the mainline commit:

25e924450fcb can: flexcan: implement workaround for errata ERR005829

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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RE: [PATCH 3/3] can: flexcan: Add support for non RX-FIFO mode and ERRATA ERR005829

[bhupesh.sharma]

> -----Original Message-----
> From: Marc Kleine-Budde [mailto:mkl@pengutronix.de]
> On 04/09/2015 05:45 PM, bhupesh.sharma@freescale.com wrote:
> >> -----Original Message-----
> >> From: Marc Kleine-Budde [mailto:mkl@pengutronix.de] On 04/09/2015
> >> 05:24 PM, Bhupesh Sharma wrote:
> >>> This patch adds support for non RX-FIFO (legacy) mode and ERRATA
> >>> ERR005829 handling in flexcan driver.
> >>
> >> What about
> >> 25e924450fcb can: flexcan: implement workaround for errata ERR005829 ?
> >
> > Oops, looks like a typo. Will fix in V2.
> >
> >>> Both these features are now selectable via Kconfig entries and hence
> >>> can be turned-on/off as per a SoC feature set availability.
> >>
> >> Sorry Kconfig is not an option here.
> >
> > I meant the defconfig here. By default the errata handling would be
> > turned-off in the Kconfig.
> >
> > Any other ideas?
> 
> Please look at the mainline commit:
> 
> 25e924450fcb can: flexcan: implement workaround for errata ERR005829
> 

Hmm.. This looks like a fairly simple ERRATA to be handled w/o Kconfig.
But with the legacy mode support ERRATA, we have completely different RX setups for
the legacy and FIFO mode.

Errata handling via Kconfig seems pretty common in the kernel (see [1])

[1] ARM64_ERRATUM_827319: 
https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/arch/arm64/Kconfig?id=refs/tags/next-20150409#n287

Regards,
Bhupesh

Re: [PATCH 3/3] can: flexcan: Add support for non RX-FIFO mode and ERRATA ERR005829

[Marc Kleine-Budde]

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On 04/09/2015 05:53 PM, bhupesh.sharma@freescale.com wrote:
>> Please look at the mainline commit:
>>
>> 25e924450fcb can: flexcan: implement workaround for errata ERR005829
> 
> Hmm.. This looks like a fairly simple ERRATA to be handled w/o Kconfig.
> But with the legacy mode support ERRATA, we have completely different RX setups for
> the legacy and FIFO mode.

Can you give me link to the "ERRATA ERR005829 (A-008965)" description?

The errata ERR005829 is described here
http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf and it's
fixed by mainline commit:

    25e924450fcb can: flexcan: implement workaround for errata ERR005829

Is your "ERRATA ERR005829 (A-008965)" something different?

> Errata handling via Kconfig seems pretty common in the kernel (see [1])

Yes, for the ARM Core itself.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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RE: [PATCH 3/3] can: flexcan: Add support for non RX-FIFO mode and ERRATA ERR005829

[bhupesh.sharma]

> -----Original Message-----
> From: Marc Kleine-Budde [mailto:mkl@pengutronix.de]
> On 04/09/2015 05:53 PM, bhupesh.sharma@freescale.com wrote:
> >> Please look at the mainline commit:
> >>
> >> 25e924450fcb can: flexcan: implement workaround for errata ERR005829
> >
> > Hmm.. This looks like a fairly simple ERRATA to be handled w/o Kconfig.
> > But with the legacy mode support ERRATA, we have completely different
> > RX setups for the legacy and FIFO mode.
> 
> Can you give me link to the "ERRATA ERR005829 (A-008965)" description?
> 
> The errata ERR005829 is described here
> http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf and it's
> fixed by mainline commit:
> 
>     25e924450fcb can: flexcan: implement workaround for errata ERR005829
> 
> Is your "ERRATA ERR005829 (A-008965)" something different?

Yes. I mixed up the errata numbers in the git log by mistake.

Its number A-008965 and is related to LS1021A FlexCAN not being
able to support RX-FIFO mode.

Regards,
Bhupesh

> 
> > Errata handling via Kconfig seems pretty common in the kernel (see
> > [1])
> 
> Yes, for the ARM Core itself.
> 
> Marc
> 
> --
> Pengutronix e.K.                  | Marc Kleine-Budde           |
> Industrial Linux Solutions        | Phone: +49-231-2826-924     |
> Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
> Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |

Re: [PATCH 3/3] can: flexcan: Add support for non RX-FIFO mode and ERRATA ERR005829

[Marc Kleine-Budde]

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On 04/09/2015 06:17 PM, bhupesh.sharma@freescale.com wrote:
>> -----Original Message-----
>> From: Marc Kleine-Budde [mailto:mkl@pengutronix.de]
>> On 04/09/2015 05:53 PM, bhupesh.sharma@freescale.com wrote:
>>>> Please look at the mainline commit:
>>>>
>>>> 25e924450fcb can: flexcan: implement workaround for errata ERR005829
>>>
>>> Hmm.. This looks like a fairly simple ERRATA to be handled w/o Kconfig.
>>> But with the legacy mode support ERRATA, we have completely different
>>> RX setups for the legacy and FIFO mode.
>>
>> Can you give me link to the "ERRATA ERR005829 (A-008965)" description?
>>
>> The errata ERR005829 is described here
>> http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf and it's
>> fixed by mainline commit:
>>
>>     25e924450fcb can: flexcan: implement workaround for errata ERR005829
>>
>> Is your "ERRATA ERR005829 (A-008965)" something different?
> 
> Yes. I mixed up the errata numbers in the git log by mistake.
> 
> Its number A-008965 and is related to LS1021A FlexCAN not being
> able to support RX-FIFO mode.

Do you have a link to the errata? Where's the corresponding kconfig
patch? Why do you have to switch on/off the errata by kconfig? Is there
a LS1021A without the bug?

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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RE: [PATCH 3/3] can: flexcan: Add support for non RX-FIFO mode and ERRATA ERR005829

[bhupesh.sharma]

Hi Marc,

Sorry for the late reply.

> On 04/09/2015 06:17 PM, bhupesh.sharma@freescale.com wrote:
> >> From: Marc Kleine-Budde [mailto:mkl@pengutronix.de] On 04/09/2015
> >> 05:53 PM, bhupesh.sharma@freescale.com wrote:
> >>>> Please look at the mainline commit:
> >>>>
> >>>> 25e924450fcb can: flexcan: implement workaround for errata
> >>>> ERR005829
> >>>
> >>> Hmm.. This looks like a fairly simple ERRATA to be handled w/o
> Kconfig.
> >>> But with the legacy mode support ERRATA, we have completely
> >>> different RX setups for the legacy and FIFO mode.
> >>
> >> Can you give me link to the "ERRATA ERR005829 (A-008965)" description?
> >>
> >> The errata ERR005829 is described here
> >> http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf and
> >> it's fixed by mainline commit:
> >>
> >>     25e924450fcb can: flexcan: implement workaround for errata
> >> ERR005829
> >>
> >> Is your "ERRATA ERR005829 (A-008965)" something different?
> >
> > Yes. I mixed up the errata numbers in the git log by mistake.
> >
> > Its number A-008965 and is related to LS1021A FlexCAN not being able
> > to support RX-FIFO mode.
> 
> Do you have a link to the errata? Where's the corresponding kconfig
> patch? Why do you have to switch on/off the errata by kconfig? Is there a
> LS1021A without the bug?

The errata list is not available for public access on www.freescale.com so far.
The next version of LS1021A SoC, is fixing this bug and since both are supposed
to be used by customers, the kconfig trick is required to turn-off this handling
for one version, while keeping it intact for the other.

Regards,
Bhupesh

Re: [PATCH 3/3] can: flexcan: Add support for non RX-FIFO mode and ERRATA ERR005829

[Marc Kleine-Budde]

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On 04/27/2015 08:38 AM, bhupesh.sharma@freescale.com wrote:
> Hi Marc,
> 
> Sorry for the late reply.
> 
>> On 04/09/2015 06:17 PM, bhupesh.sharma@freescale.com wrote:
>>>> From: Marc Kleine-Budde [mailto:mkl@pengutronix.de] On 04/09/2015
>>>> 05:53 PM, bhupesh.sharma@freescale.com wrote:
>>>>>> Please look at the mainline commit:
>>>>>>
>>>>>> 25e924450fcb can: flexcan: implement workaround for errata
>>>>>> ERR005829
>>>>>
>>>>> Hmm.. This looks like a fairly simple ERRATA to be handled w/o
>> Kconfig.
>>>>> But with the legacy mode support ERRATA, we have completely
>>>>> different RX setups for the legacy and FIFO mode.
>>>>
>>>> Can you give me link to the "ERRATA ERR005829 (A-008965)" description?
>>>>
>>>> The errata ERR005829 is described here
>>>> http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf and
>>>> it's fixed by mainline commit:
>>>>
>>>>     25e924450fcb can: flexcan: implement workaround for errata
>>>> ERR005829
>>>>
>>>> Is your "ERRATA ERR005829 (A-008965)" something different?
>>>
>>> Yes. I mixed up the errata numbers in the git log by mistake.
>>>
>>> Its number A-008965 and is related to LS1021A FlexCAN not being able
>>> to support RX-FIFO mode.
>>
>> Do you have a link to the errata? Where's the corresponding kconfig
>> patch? Why do you have to switch on/off the errata by kconfig? Is there a
>> LS1021A without the bug?
> 
> The errata list is not available for public access on www.freescale.com so far.
> The next version of LS1021A SoC, is fixing this bug and since both are supposed
> to be used by customers, the kconfig trick is required to turn-off this handling
> for one version, while keeping it intact for the other.

Sorry, a compile time switch is not an option here. Please configure it
during runtime via the device tree. This can be done by different
compatibles, one for the broken another one for the fixed SoC.

regards,
Marc
-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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RE: [PATCH 3/3] can: flexcan: Add support for non RX-FIFO mode and ERRATA ERR005829

[bhupesh.sharma]

> From: Marc Kleine-Budde [mailto:mkl@pengutronix.de]
> On 04/27/2015 08:38 AM, bhupesh.sharma@freescale.com wrote:
> > Hi Marc,
> >
> > Sorry for the late reply.
> >
> >> On 04/09/2015 06:17 PM, bhupesh.sharma@freescale.com wrote:
> >>>> From: Marc Kleine-Budde [mailto:mkl@pengutronix.de] On 04/09/2015
> >>>> 05:53 PM, bhupesh.sharma@freescale.com wrote:
> >>>>>> Please look at the mainline commit:
> >>>>>>
> >>>>>> 25e924450fcb can: flexcan: implement workaround for errata
> >>>>>> ERR005829
> >>>>>
> >>>>> Hmm.. This looks like a fairly simple ERRATA to be handled w/o
> >> Kconfig.
> >>>>> But with the legacy mode support ERRATA, we have completely
> >>>>> different RX setups for the legacy and FIFO mode.
> >>>>
> >>>> Can you give me link to the "ERRATA ERR005829 (A-008965)"
> description?
> >>>>
> >>>> The errata ERR005829 is described here
> >>>> http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf and
> >>>> it's fixed by mainline commit:
> >>>>
> >>>>     25e924450fcb can: flexcan: implement workaround for errata
> >>>> ERR005829
> >>>>
> >>>> Is your "ERRATA ERR005829 (A-008965)" something different?
> >>>
> >>> Yes. I mixed up the errata numbers in the git log by mistake.
> >>>
> >>> Its number A-008965 and is related to LS1021A FlexCAN not being able
> >>> to support RX-FIFO mode.
> >>
> >> Do you have a link to the errata? Where's the corresponding kconfig
> >> patch? Why do you have to switch on/off the errata by kconfig? Is
> >> there a LS1021A without the bug?
> >
> > The errata list is not available for public access on www.freescale.com
> so far.
> > The next version of LS1021A SoC, is fixing this bug and since both are
> > supposed to be used by customers, the kconfig trick is required to
> > turn-off this handling for one version, while keeping it intact for the
> other.
> 
> Sorry, a compile time switch is not an option here. Please configure it
> during runtime via the device tree. This can be done by different
> compatibles, one for the broken another one for the fixed SoC.
 
Well, most of the code is written to handle this on run-time (on basis
of the dts). Maybe I can create two versions of fsl_ls1021a_devtype_data rather
than using the kConfig:

For the broken- SoC:
static struct flexcan_devtype_data fsl_ls1021a_devtype_data = {
	.features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES
	| FLEXCAN_USES_RX_MB
	,
};

and for the new-SoC:
static struct flexcan_devtype_data fsl_ls1021a_devtype_data = {
	.features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES
	,
};

Note that the legacy (non-RX FIFO mode) should work on all the FlexCAN variants,
so this a feature which some-one can expose/hide as per their use-case, as long
as the driver supports both the Rx-FIFO and non-RX-FIFO mode legs.

Right?

Regards,
Bhupesh

Re: [PATCH 3/3] can: flexcan: Add support for non RX-FIFO mode and ERRATA ERR005829

[Marc Kleine-Budde]

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On 04/27/2015 08:51 AM, bhupesh.sharma@freescale.com wrote:

>>> The errata list is not available for public access on www.freescale.com
>> so far.
>>> The next version of LS1021A SoC, is fixing this bug and since both are
>>> supposed to be used by customers, the kconfig trick is required to
>>> turn-off this handling for one version, while keeping it intact for the
>> other.
>>
>> Sorry, a compile time switch is not an option here. Please configure it
>> during runtime via the device tree. This can be done by different
>> compatibles, one for the broken another one for the fixed SoC.
>  
> Well, most of the code is written to handle this on run-time (on basis
> of the dts). Maybe I can create two versions of fsl_ls1021a_devtype_data rather
> than using the kConfig:
> 
> For the broken- SoC:
> static struct flexcan_devtype_data fsl_ls1021a_devtype_data = {
> 	.features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES
> 	| FLEXCAN_USES_RX_MB
> 	,
> };
> 
> and for the new-SoC:
> static struct flexcan_devtype_data fsl_ls1021a_devtype_data = {
> 	.features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES
> 	,
> };

Yes - use two different variables for this and assign them to two
compatible entries.

> Note that the legacy (non-RX FIFO mode) should work on all the FlexCAN variants,
> so this a feature which some-one can expose/hide as per their use-case, as long
> as the driver supports both the Rx-FIFO and non-RX-FIFO mode legs.

Sure, but not via a compile time switch.

Marc
-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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RE: [PATCH 3/3] can: flexcan: Add support for non RX-FIFO mode and ERRATA ERR005829

[bhupesh.sharma]

> From: Marc Kleine-Budde [mailto:mkl@pengutronix.de]
> On 04/27/2015 08:51 AM, bhupesh.sharma@freescale.com wrote:
> 
> >>> The errata list is not available for public access on
> >>> www.freescale.com
> >> so far.
> >>> The next version of LS1021A SoC, is fixing this bug and since both
> >>> are supposed to be used by customers, the kconfig trick is required
> >>> to turn-off this handling for one version, while keeping it intact
> >>> for the
> >> other.
> >>
> >> Sorry, a compile time switch is not an option here. Please configure
> >> it during runtime via the device tree. This can be done by different
> >> compatibles, one for the broken another one for the fixed SoC.
> >
> > Well, most of the code is written to handle this on run-time (on basis
> > of the dts). Maybe I can create two versions of
> > fsl_ls1021a_devtype_data rather than using the kConfig:
> >
> > For the broken- SoC:
> > static struct flexcan_devtype_data fsl_ls1021a_devtype_data = {
> > 	.features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES
> > 	| FLEXCAN_USES_RX_MB
> > 	,
> > };
> >
> > and for the new-SoC:
> > static struct flexcan_devtype_data fsl_ls1021a_devtype_data = {
> > 	.features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES
> > 	,
> > };
> 
> Yes - use two different variables for this and assign them to two
> compatible entries.
> 
> > Note that the legacy (non-RX FIFO mode) should work on all the FlexCAN
> > variants, so this a feature which some-one can expose/hide as per
> > their use-case, as long as the driver supports both the Rx-FIFO and
> non-RX-FIFO mode legs.
> 
> Sure, but not via a compile time switch.
> 

Agreed. So I will shortly spin-out a v2 accordingly.

Regards,
Bhupesh