From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 459F0C32771 for ; Wed, 17 Aug 2022 14:37:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240294AbiHQOh1 (ORCPT ); Wed, 17 Aug 2022 10:37:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240230AbiHQOhA (ORCPT ); Wed, 17 Aug 2022 10:37:00 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F7179C2C8 for ; Wed, 17 Aug 2022 07:36:31 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id j8so24868281ejx.9 for ; Wed, 17 Aug 2022 07:36:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=vUjsIUj0sjtjNDnJJ6/7r96WzwA0T1BZA3Wt0Kn9xQk=; b=f1d9zEDhKwLi6aKZxl6lUTN1nF5BWPylGCKU+citrsGjBzPd8sBQ8y1ikUFGBZl5Gc L1/QPCBhfBtqqBHhnVoNaFqkkmSmySU5QFU1XaKk8OO5kpq5AtE4MrDA25qlLcYxU5pQ FFml/YhaAroEbSeCrZ/dQrmLmIRD+HIgY40nk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=vUjsIUj0sjtjNDnJJ6/7r96WzwA0T1BZA3Wt0Kn9xQk=; b=pg/d4bTcQ/FfPpC49+RDG0mIrfjoce0sRkh0k3aSZ1f6Zd8Gnir/a00seXE70uFrST 4W5mGOvYrplAaHCIlSBwD4AKfWlw68cbgg1/bJgjyy08nw8+c4nnl6Zd+L+SadSsDNbN Sh5cg4eSBi+5zsQ/fSrpZwNmI0p+smwwcKc90R/M2ofbC5u4X6Nn27SR7nwkvmypYa+A v/A9GBcGLCDLuNM8I8zZLjSSjyjFeFFP0q2WGgWGDfVckABByTRmOba/F2y3E9rOQu3K QqRD/AwVf5QxwerfIV7Y3ex2T9g/Se//u1VKOUV6Vj9RdQGq/rpVcZd3R1qVBxm4Hz8Q 1vfA== X-Gm-Message-State: ACgBeo1H0OWeGzOSPA0Q61BKFVBaBw1N8TmckylYG1Lt/ZEwrBXkXJXv iHBDTnTVgfrcghRmcc3Z6flqWw== X-Google-Smtp-Source: AA6agR52ooK2bKYnm/Z+Mj/zD2lV/WY0/+4YAisvjjA/tYt5pplPwA4TD3tXZ7SdYX2G4HIN+B0mhA== X-Received: by 2002:a17:907:2721:b0:731:2aeb:7940 with SMTP id d1-20020a170907272100b007312aeb7940mr17579840ejl.448.1660746989538; Wed, 17 Aug 2022 07:36:29 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-31-31-9.retail.telecomitalia.it. [79.31.31.9]) by smtp.gmail.com with ESMTPSA id o9-20020aa7c7c9000000b0043cab10f702sm10711982eds.90.2022.08.17.07.36.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 07:36:29 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Alexandre Torgue , Amarula patchwork , michael@amarulasolutions.com, Marc Kleine-Budde , Dario Binacchi , Dario Binacchi , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Krzysztof Kozlowski , Paolo Abeni , Rob Herring , Wolfgang Grandegger , devicetree@vger.kernel.org, linux-can@vger.kernel.org, netdev@vger.kernel.org Subject: [RFC PATCH 1/4] dt-bindings: net: can: add STM32 bxcan DT bindings Date: Wed, 17 Aug 2022 16:35:26 +0200 Message-Id: <20220817143529.257908-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220817143529.257908-1-dario.binacchi@amarulasolutions.com> References: <20220817143529.257908-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-can@vger.kernel.org Add documentation of device tree bindings for the STM32 basic extended CAN (bxcan) controller. Signed-off-by: Dario Binacchi Signed-off-by: Dario Binacchi --- .../devicetree/bindings/net/can/st,bxcan.yaml | 139 ++++++++++++++++++ 1 file changed, 139 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/can/st,bxcan.yaml diff --git a/Documentation/devicetree/bindings/net/can/st,bxcan.yaml b/Documentation/devicetree/bindings/net/can/st,bxcan.yaml new file mode 100644 index 000000000000..f4cfd26e4785 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/st,bxcan.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/st,bxcan.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics bxCAN controller Device Tree Bindings + +description: STMicroelectronics BxCAN controller for CAN bus + +maintainers: + - Dario Binacchi + +allOf: + - $ref: can-controller.yaml# + +properties: + compatible: + enum: + - st,stm32-bxcan-core + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + description: + Input clock for registers access + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +required: + - compatible + - reg + - resets + - clocks + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +patternProperties: + "^can@[0-9]+$": + type: object + description: + A CAN block node contains two subnodes, representing each one a CAN + instance available on the machine. + + properties: + compatible: + enum: + - st,stm32-bxcan + + master: + description: + Master and slave mode of the bxCAN peripheral is only relevant + if the chip has two CAN peripherals. In that case they share + some of the required logic, and that means you cannot use the + slave CAN without the master CAN. + type: boolean + + reg: + description: | + Offset of CAN instance in CAN block. Valid values are: + - 0x0: CAN1 + - 0x400: CAN2 + maxItems: 1 + + interrupts: + items: + - description: transmit interrupt + - description: FIFO 0 receive interrupt + - description: FIFO 1 receive interrupt + - description: status change error interrupt + + interrupt-names: + items: + - const: tx + - const: rx0 + - const: rx1 + - const: sce + + resets: + maxItems: 1 + + clocks: + description: + Input clock for registers access + maxItems: 1 + + additionalProperties: false + + required: + - compatible + - reg + - interrupts + - resets + +examples: + - | + #include + #include + + can: can@40006400 { + compatible = "st,stm32-bxcan-core"; + reg = <0x40006400 0x800>; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + can1: can@0 { + compatible = "st,stm32-bxcan"; + reg = <0x0>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + master; + status = "disabled"; + }; + + can2: can@400 { + compatible = "st,stm32-bxcan"; + reg = <0x400>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + status = "disabled"; + }; + }; -- 2.32.0