Re: [PATCH v3 0/6] can: flexcan: Add NXP S32N79 SoC support

[Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>]

On 3/24/2026 3:46 PM, Marc Kleine-Budde wrote:
> On 23.03.2026 14:58:21, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> This patch series adds FlexCAN support for the NXP S32N79 SoC.
>>
>> The S32N79 is an automotive-grade processor from NXP with multiple
>> FlexCAN instances. The FlexCAN IP integration on S32N79 differs from
>> other SoCs in the interrupt routing - it uses two separate interrupt
>> lines:
>>    - one interrupt for mailboxes 0-127
>>    - one interrupt for bus error detection and device state changes
> 
> Can you check if the S32N79 suffers from the
> 
> | /* No interrupt for error passive */
> | #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
> 
> problem? Maybe everyone just added the FLEXCAN_QUIRK_BROKEN_PERR_STATE
> for the new SoC without actually testing it.
> 
> regards,
> Marc
> 

Hello Marc,

I've tested on S32N79 hardware. Without the quirk, the controller
reaches Transmit-Error-Counter=128 (error-passive at HW level) but the
driver only sees ERROR-WARNING - the passive interrupt never fires.

With the quirk enabled, ERROR-PASSIVE is correctly reported.
So FLEXCAN_QUIRK_BROKEN_PERR_STATE quirk is needed for S32N79.

Best Regards,
Ciprian