From: Marc Kleine-Budde <mkl@pengutronix.de>
To: info@gerhard-bertelsmann.de
Cc: Michael Luxen <mluxen@gmx.net>, Luka Rahne <luka.rahne@gmail.com>,
"linux-can@vger.kernel.org" <linux-can@vger.kernel.org>
Subject: Re: AW: Receiving messages issue
Date: Tue, 25 Jun 2013 15:36:37 +0200 [thread overview]
Message-ID: <51C99CE5.7070708@pengutronix.de> (raw)
In-Reply-To: <56720.79.205.48.80.1372161611.squirrel@webmail.rdts.de>
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On 06/25/2013 02:00 PM, Gerhard Bertelsmann wrote:
>>> On 06/24/2013 02:26 PM, Luka Rahne wrote:
>>>> I am using MCP2515 with i.MX27
>>>
>>> MCP2515 is the second worst CAN hardware I know. Only MCP2510 is worse.
> IMHO the controller isn't bad - it's the host interface (SPI).
I see the CAN controller as a black box, I don't care if it doesn't
perform under Linux due to the host interface or the fact that it has a
rather shallow FIFO.
> The MCP2515 based capes are using the BB SPI bus. As already stated before,
> the CAN controller is not read-out fast enough. Root cause of this is mainly
> the latency between MCP2515 interrupt and the SPI commands. I have seen
> this on different platforms: there are gaps sometimes in the 100usec range.
> The BBB is fast but there will be still gaps between MCP2515 attention needed
> and SPI transfers and on heavy loaded links there will be reordered packets
> or packet losts.
> One solution could be running the SPI with higher priority. Second one would
> be to tie SPI and MCP2515 driver together, but this is a quite dirty hack.
You probably don't want to do this.
> But the Beaglebone-CPU has a nifty thing: the PRUSS - 2x200 MHz CPUs
> independantly running from the main CPU. Coupling one or more MCP2515s
> to the appropiate pins could be easily served. The PRUSS doesn't have a
> hardware SPI interface, but with old school bitbanging you could get all
> CAN packets even on fully loaded 1MBit link.
You can port the existing CAN driver (note it's GPL'ed) or write a new
one for the PRUSS and design a proper memory mapped interface interface
to the CPU.
> There is shared memory region between main and PRUSS CPU. Both CPU
> domains could generate an interrupt for the other domain. So the data
> could be easily exchanged - without any lost or reordered packets.
> BTW: Which structure would be the best for this kind of data transfer ?
IANAL: If you design the PRUSS firmware to be compatible to an existing
driver e.g. a SJA10000 you don't have to write a new driver under Linux.
However I'm not sure about the legal consequences of this.
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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next prev parent reply other threads:[~2013-06-25 13:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-25 7:43 AW: Receiving messages issue Michael Luxen
2013-06-25 12:00 ` Gerhard Bertelsmann
2013-06-25 12:58 ` wg
2013-06-25 13:36 ` Marc Kleine-Budde [this message]
2013-07-05 10:04 ` Luka Rahne
2013-07-05 10:07 ` Luka Rahne
2013-07-05 10:18 ` Marc Kleine-Budde
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