Re: [PATCH v3 2/2] CAN: CAN driver to support multiple CAN bus on SPI interface

[Oliver Hartkopp <socketcan@hartkopp.net>]

Hi Stefano,

two more remarks:

>> On 02.04.2014 09:18, Stefano Babic wrote:
>>
>>> +
>>> +/* CFG message */
>>> +struct msg_cfg_data {
>>> +	u8	channel;
>>> +	u8	enabled;
>>> +	struct can_bittiming bt;
>>> +} __packed;

When you transfer this structure via SPI.
What are your assumptions about the host specifc byte order?

Does the SPI CAN adapter autodetect the host byte order?

> Only to check what is happening:
> 
> 5: hcan2: <NOARP> mtu 16 qdisc noop state DOWN qlen 10
>     link/can
>     can state STOPPED restart-ms 0
>     bitrate 0 sample-point 0.000
>     tq 0 prop-seg 0 phase-seg1 0 phase-seg2 0 sjw 0
>     clock 100000000

Ah - you also have a CAN clock :-)


> Agree, it is the best way. I will add a SPI_MSG_GET_CFG to retrieve the
> timing from the controller in probe(). In my case, the controller cannot
> have different timing for each channel, but I agree the query must be
> done for each channel, in case a microcontroller supports it.

Yep.

Just to make sure what is needed:

>>> +		priv->can.clock.freq = SLAVE_CLK_FREQ;
>>> +		priv->can.bittiming_const = NULL;
>>> +		priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
>>> +			CAN_CTRLMODE_LISTENONLY	| CAN_CTRLMODE_3_SAMPLES;

These three controller specific settings - which are usually constant values
in other CAN drivers - need to be provided by SPI_MSG_GET_CFG.

Best regards,
Oliver