[PATCH v2] c_can: Add support for eg20t (pch_can)

[PATCH v2] c_can: Add support for eg20t (pch_can)

[Alexander Stein]

Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
---
This is the correct version of this patch I use.
It has no spinlock which is not needed, AFAICT.

 drivers/net/can/c_can/c_can_pci.c | 50 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/drivers/net/can/c_can/c_can_pci.c b/drivers/net/can/c_can/c_can_pci.c
index bce0be5..128788c 100644
--- a/drivers/net/can/c_can/c_can_pci.c
+++ b/drivers/net/can/c_can/c_can_pci.c
@@ -19,9 +19,13 @@
 
 #include "c_can.h"
 
+#define PCI_DEVICE_ID_PCH_CAN	0x8818
+#define PCH_PCI_SOFT_RESET	0x01fc
+
 enum c_can_pci_reg_align {
 	C_CAN_REG_ALIGN_16,
 	C_CAN_REG_ALIGN_32,
+	C_CAN_REG_32,
 };
 
 struct c_can_pci_data {
@@ -31,6 +35,10 @@ struct c_can_pci_data {
 	enum c_can_pci_reg_align reg_align;
 	/* Set the frequency */
 	unsigned int freq;
+	/* PCI bar number */
+	int bar;
+	/* Callback for reset */
+	void (*init)(const struct c_can_priv *priv, bool enable);
 };
 
 /*
@@ -63,6 +71,29 @@ static void c_can_pci_write_reg_aligned_to_32bit(struct c_can_priv *priv,
 	writew(val, priv->base + 2 * priv->regs[index]);
 }
 
+static u16 c_can_pci_read_reg_32bit(struct c_can_priv *priv,
+				    enum reg index)
+{
+	return (u16)ioread32(priv->base + 2 * priv->regs[index]);
+}
+
+static void c_can_pci_write_reg_32bit(struct c_can_priv *priv,
+				      enum reg index, u16 val)
+{
+	iowrite32((u32)val, priv->base + 2 * priv->regs[index]);
+}
+
+static void c_can_pci_reset_pch(const struct c_can_priv *priv, bool enable)
+{
+	if (enable) {
+		u32 __iomem *addr = priv->base + PCH_PCI_SOFT_RESET;
+
+		/* write to sw reset register */
+		iowrite32(1, addr);
+		iowrite32(0, addr);
+	}
+}
+
 static int c_can_pci_probe(struct pci_dev *pdev,
 			   const struct pci_device_id *ent)
 {
@@ -87,7 +118,7 @@ static int c_can_pci_probe(struct pci_dev *pdev,
 	pci_set_master(pdev);
 	pci_enable_msi(pdev);
 
-	addr = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
+	addr = pci_iomap(pdev, c_can_pci_data->bar, pci_resource_len(pdev, 0));
 	if (!addr) {
 		dev_err(&pdev->dev,
 			"device has no PCI memory resources, "
@@ -142,11 +173,17 @@ static int c_can_pci_probe(struct pci_dev *pdev,
 		priv->read_reg = c_can_pci_read_reg_aligned_to_16bit;
 		priv->write_reg = c_can_pci_write_reg_aligned_to_16bit;
 		break;
+	case C_CAN_REG_32:
+		priv->read_reg = c_can_pci_read_reg_32bit;
+		priv->write_reg = c_can_pci_write_reg_32bit;
+		break;
 	default:
 		ret = -EINVAL;
 		goto out_free_c_can;
 	}
 
+	priv->raminit = c_can_pci_data->init;
+
 	ret = register_c_can_dev(dev);
 	if (ret) {
 		dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
@@ -193,6 +230,15 @@ static struct c_can_pci_data c_can_sta2x11= {
 	.type = BOSCH_C_CAN,
 	.reg_align = C_CAN_REG_ALIGN_32,
 	.freq = 52000000, /* 52 Mhz */
+	.bar = 0,
+};
+
+static struct c_can_pci_data c_can_pch = {
+	.type = BOSCH_C_CAN,
+	.reg_align = C_CAN_REG_32,
+	.freq = 50000000, /* 50 MHz */
+	.init = c_can_pci_reset_pch,
+	.bar = 1,
 };
 
 #define C_CAN_ID(_vend, _dev, _driverdata) {		\
@@ -202,6 +248,8 @@ static struct c_can_pci_data c_can_sta2x11= {
 static DEFINE_PCI_DEVICE_TABLE(c_can_pci_tbl) = {
 	C_CAN_ID(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_CAN,
 		 c_can_sta2x11),
+	C_CAN_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_CAN,
+		 c_can_pch),
 	{},
 };
 static struct pci_driver c_can_pci_driver = {
-- 
1.8.3.2

Re: [PATCH v2] c_can: Add support for eg20t (pch_can)

[Thomas Gleixner]

On Mon, 7 Apr 2014, Alexander Stein wrote:
> -	addr = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
> +	addr = pci_iomap(pdev, c_can_pci_data->bar, pci_resource_len(pdev, 0));

Shouldn't that be pci_resource_len(pdev, bar) ????

Thanks,

	tglx

Re: [PATCH v2] c_can: Add support for eg20t (pch_can)

[Wolfgang Grandegger]

On Tue, 8 Apr 2014 16:20:41 +0200 (CEST), Thomas Gleixner
<tglx@linutronix.de> wrote:
> On Mon, 7 Apr 2014, Alexander Stein wrote:
>> -	addr = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
>> +	addr = pci_iomap(pdev, c_can_pci_data->bar, pci_resource_len(pdev,
0));
> 
> Shouldn't that be pci_resource_len(pdev, bar) ????

Yes, or just "0".

Wolfgang.

Re: [PATCH v2] c_can: Add support for eg20t (pch_can)

[Thomas Gleixner]

On Tue, 8 Apr 2014, Wolfgang Grandegger wrote:

> On Tue, 8 Apr 2014 16:20:41 +0200 (CEST), Thomas Gleixner
> <tglx@linutronix.de> wrote:
> > On Mon, 7 Apr 2014, Alexander Stein wrote:
> >> -	addr = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
> >> +	addr = pci_iomap(pdev, c_can_pci_data->bar, pci_resource_len(pdev,
> 0));
> > 
> > Shouldn't that be pci_resource_len(pdev, bar) ????
> 
> Yes, or just "0".

Works as well.

Re: [PATCH v2] c_can: Add support for eg20t (pch_can)

[Marc Kleine-Budde]

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On 04/07/2014 08:52 AM, Alexander Stein wrote:
> Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>

Applied to can-next/master

> ---
> This is the correct version of this patch I use.
> It has no spinlock which is not needed, AFAICT.
> 
>  drivers/net/can/c_can/c_can_pci.c | 50 ++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 49 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/can/c_can/c_can_pci.c b/drivers/net/can/c_can/c_can_pci.c
> index bce0be5..128788c 100644
> --- a/drivers/net/can/c_can/c_can_pci.c
> +++ b/drivers/net/can/c_can/c_can_pci.c

[...]

> @@ -87,7 +118,7 @@ static int c_can_pci_probe(struct pci_dev *pdev,
>  	pci_set_master(pdev);
>  	pci_enable_msi(pdev);
>  
> -	addr = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
> +	addr = pci_iomap(pdev, c_can_pci_data->bar, pci_resource_len(pdev, 0));

	addr = pci_iomap(pdev, c_can_pci_data->bar,
			 pci_resource_len(pdev, c_can_pci_data->bar));

With this fix applied.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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Re: [PATCH v2] c_can: Add support for eg20t (pch_can)

[Marc Kleine-Budde]

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On 04/07/2014 08:52 AM, Alexander Stein wrote:
> Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
[..]

> +static void c_can_pci_reset_pch(const struct c_can_priv *priv, bool enable)
> +{
> +	if (enable) {
> +		u32 __iomem *addr = priv->base + PCH_PCI_SOFT_RESET;
> +
> +		/* write to sw reset register */
> +		iowrite32(1, addr);

Do we need to wait for something here?

> +		iowrite32(0, addr);
> +	}
> +}

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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Re: [PATCH v2] c_can: Add support for eg20t (pch_can)

[Thomas Gleixner]

On Thu, 17 Apr 2014, Marc Kleine-Budde wrote:

> On 04/07/2014 08:52 AM, Alexander Stein wrote:
> > Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
> [..]
> 
> > +static void c_can_pci_reset_pch(const struct c_can_priv *priv, bool enable)
> > +{
> > +	if (enable) {
> > +		u32 __iomem *addr = priv->base + PCH_PCI_SOFT_RESET;
> > +
> > +		/* write to sw reset register */
> > +		iowrite32(1, addr);
> 
> Do we need to wait for something here?

No. It's activating the "reset line" for that IP block. As long as the
bit is set the IP is effectivly in HW reset state. Releasing the reset
brings it back to operation. iowrite32() is serialized by itself, so
no extra work required.

Thanks,

	tglx

Re: [PATCH v2] c_can: Add support for eg20t (pch_can)

[Marc Kleine-Budde]

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On 04/17/2014 11:18 PM, Thomas Gleixner wrote:
> On Thu, 17 Apr 2014, Marc Kleine-Budde wrote:
> 
>> On 04/07/2014 08:52 AM, Alexander Stein wrote:
>>> Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
>> [..]
>>
>>> +static void c_can_pci_reset_pch(const struct c_can_priv *priv, bool enable)
>>> +{
>>> +	if (enable) {
>>> +		u32 __iomem *addr = priv->base + PCH_PCI_SOFT_RESET;
>>> +
>>> +		/* write to sw reset register */
>>> +		iowrite32(1, addr);
>>
>> Do we need to wait for something here?
> 
> No. It's activating the "reset line" for that IP block. As long as the
> bit is set the IP is effectivly in HW reset state. Releasing the reset
> brings it back to operation. iowrite32() is serialized by itself, so
> no extra work required.

Thanks Thomas.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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