Re: [PATCH v2 1/2] Allwinner SoC CAN controller Support

[Marc Kleine-Budde <mkl@pengutronix.de>]

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On 09/03/2015 12:09 PM, Gerhard Bertelsmann wrote:
> Devicetree Bindings documentation
> 
> Signed-off-by: Gerhard Bertelsmann < info@gerhard-bertelsmann.de >
                                      ^                           ^
nitpick: no space here.

Please format your subject like: "can: add Allwinner SoC CAN controller
Devicetree Bindings documentation".

> 
> 
> .../devicetree/bindings/net/can/sunxi_can.txt      |  42 ++
>  1 files changed, 42 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/can/sunxi_can.txt b/Documentation/devicetree/bindings/net/can/sunxi_can.txt
> new file mode 100644
> index 0000000..454e92f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/can/sunxi_can.txt
> @@ -0,0 +1,42 @@
> +Allwinner A10/A20 CAN controller Device Tree Bindings
> +-----------------------------------------------------
> +
> +Required properties:
> +- compatible: "allwinner,sunxican"
> +- reg: physical base address and size of the Allwinner A10/A20 CAN register map.
> +- interrupts: interrupt specifier for the sole interrupt.
> +- clocks: phandle and clock specifier.
> +- pinctrl-0: pin control group to be used for this controller.
> +- pinctrl-names: must be "default".
> +
> +
> +Example
> +-------
> +
> +SoC common .dtsi file:
> +
> +	can0_pins_a: can0@0 {
> +		allwinner,pins = "PH20","PH21";
> +		allwinner,function = "can";
> +		allwinner,drive = <0>;
> +		allwinner,pull = <0>;
> +	};
> +	can0: can@01c2bc00 {
> +		compatible = "allwinner,sunxican";
> +		reg = <0x01c2bc00 0x400>;
> +		interrupts = <0 26 4>;
> +		clocks = <&apb1_gates 4>;
> +		status = "disabled";
> +		#address-cells = <1>;
> +		#size-cells = <0>;

Why address and size cells?

> +	};
> +
> +Board specific .dts file:
> +
> +	can0: can@01c2bc00 {
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&can0_pins_a>;
> +		status = "okay";
> +	};
> +
> 

Marc

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