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* RE: [PATCH v3 1/2] can: flexcan: Remodel FlexCAN register r/w APIs for big endian FlexCAN controllers.
From: Pankaj Bansal @ 2017-11-23  9:55 UTC (permalink / raw)
  To: Marc Kleine-Budde, wg@grandegger.com, linux-can@vger.kernel.org
  Cc: Varun Sethi, Poonam Aggrwal, Bhupesh Sharma, Sakar Arora
In-Reply-To: <7244fe2c-173f-be96-8ec5-1f5d78d8ec53@pengutronix.de>

Hi Marc,

> -----Original Message-----
> From: Marc Kleine-Budde [mailto:mkl@pengutronix.de]
> Sent: Thursday, November 23, 2017 2:48 PM
> To: Pankaj Bansal <pankaj.bansal@nxp.com>; wg@grandegger.com; linux-
> can@vger.kernel.org
> Cc: Varun Sethi <V.Sethi@nxp.com>; Poonam Aggrwal
> <poonam.aggrwal@nxp.com>; Bhupesh Sharma
> <bhupesh.sharma@freescale.com>; Sakar Arora
> <Sakar.Arora@freescale.com>
> Subject: Re: [PATCH v3 1/2] can: flexcan: Remodel FlexCAN register r/w APIs
> for big endian FlexCAN controllers.
> 
> On 11/23/2017 10:09 AM, Pankaj Bansal wrote:
> > The FlexCAN driver assumed that FlexCAN controller is big endian for
> > powerpc architecture and little endian for other architectures.
> >
> > But this may not be the case. FlexCAN controller can be little or big
> > endian on any architecture. For e.g. NXP LS1021A ARM based SOC has big
> > endian FlexCAN controller.
> >
> > Therefore, the driver has been modified to add a provision for both
> > types of controllers using an additional device tree property. On a
> > "fsl,p1010-flexcan" device BE is default, on all other devices LE is.
> >
> > Big Endian controllers should have "big-endian" set in the device tree.
> > check "Documentation/devicetree/bindings/net/can/fsl-flexcan.txt" for
> > usage.
> >
> > This is the standard practice followed in linux. for more info check:
> > Documentation/devicetree/bindings/common-properties.txt
> >
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> > Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
> > Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
> > Reviewed-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
> 
> I'm missing the update of the fsl-flexcan.txt in this series.
> 

As fsl-flexcan.txt is a change in device-tree, I have sent this change in another series of patches which are all in device tree.

> Marc
> 
> --
> Pengutronix e.K.                  | Marc Kleine-Budde           |
> Industrial Linux Solutions        | Phone: +49-231-2826-924     |
> Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
> Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


^ permalink raw reply
* [PATCH v2 4/4] arm: dts: Remove p1010-flexcan compatible from imx series dts
From: Pankaj Bansal @ 2017-11-23  9:55 UTC (permalink / raw)
  To: wg-5Yr1BZd7O62+XT7JhA+gdA, mkl-bIcnvbaLZ9MEGnE8C9+IrQ,
	linux-can-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
	mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA
  Cc: V.Sethi-3arQi8VN3Tc, poonam.aggrwal-3arQi8VN3Tc, Pankaj Bansal
In-Reply-To: <1511430935-29783-1-git-send-email-pankaj.bansal-3arQi8VN3Tc@public.gmane.org>

The flexcan driver has been modified to check for big-endian dts
property for be read/write to flexcan registers/mb.

An exception to this rule is powerpc P1010RDB, which is always
big-endian, even if big-endian is not present in dts. This is
checked using p1010-flexcan compatible in dts.

Therefore, remove p1010-flexcan compatible from imx series dts,
as their flexcan core is little endian.

Signed-off-by: Pankaj Bansal <pankaj.bansal-3arQi8VN3Tc@public.gmane.org>
---
Changes in v2:
  - Add this patch in series.

 arch/arm/boot/dts/imx25.dtsi | 4 ++--
 arch/arm/boot/dts/imx28.dtsi | 4 ++--
 arch/arm/boot/dts/imx35.dtsi | 4 ++--
 arch/arm/boot/dts/imx53.dtsi | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 09ce8b8..fcaff1c 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -122,7 +122,7 @@
 			};
 
 			can1: can@43f88000 {
-				compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
+				compatible = "fsl,imx25-flexcan";
 				reg = <0x43f88000 0x4000>;
 				interrupts = <43>;
 				clocks = <&clks 75>, <&clks 75>;
@@ -131,7 +131,7 @@
 			};
 
 			can2: can@43f8c000 {
-				compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
+				compatible = "fsl,imx25-flexcan";
 				reg = <0x43f8c000 0x4000>;
 				interrupts = <44>;
 				clocks = <&clks 76>, <&clks 76>;
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 2f4ebe0..e52e05c 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -1038,7 +1038,7 @@
 			};
 
 			can0: can@80032000 {
-				compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
+				compatible = "fsl,imx28-flexcan";
 				reg = <0x80032000 0x2000>;
 				interrupts = <8>;
 				clocks = <&clks 58>, <&clks 58>;
@@ -1047,7 +1047,7 @@
 			};
 
 			can1: can@80034000 {
-				compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
+				compatible = "fsl,imx28-flexcan";
 				reg = <0x80034000 0x2000>;
 				interrupts = <9>;
 				clocks = <&clks 59>, <&clks 59>;
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 6d5e6a6..1f0e220 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -303,7 +303,7 @@
 			};
 
 			can1: can@53fe4000 {
-				compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
+				compatible = "fsl,imx35-flexcan";
 				reg = <0x53fe4000 0x1000>;
 				clocks = <&clks 33>, <&clks 33>;
 				clock-names = "ipg", "per";
@@ -312,7 +312,7 @@
 			};
 
 			can2: can@53fe8000 {
-				compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
+				compatible = "fsl,imx35-flexcan";
 				reg = <0x53fe8000 0x1000>;
 				clocks = <&clks 34>, <&clks 34>;
 				clock-names = "ipg", "per";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 8bf0d89..85573cf 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -545,7 +545,7 @@
 			};
 
 			can1: can@53fc8000 {
-				compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+				compatible = "fsl,imx53-flexcan";
 				reg = <0x53fc8000 0x4000>;
 				interrupts = <82>;
 				clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
@@ -555,7 +555,7 @@
 			};
 
 			can2: can@53fcc000 {
-				compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+				compatible = "fsl,imx53-flexcan";
 				reg = <0x53fcc000 0x4000>;
 				interrupts = <83>;
 				clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
-- 
2.7.4

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^ permalink raw reply related
* [PATCH v2 2/4] powerpc: dts: P1010: Add endianness property to flexcan node
From: Pankaj Bansal @ 2017-11-23  9:55 UTC (permalink / raw)
  To: wg-5Yr1BZd7O62+XT7JhA+gdA, mkl-bIcnvbaLZ9MEGnE8C9+IrQ,
	linux-can-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
	mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA
  Cc: V.Sethi-3arQi8VN3Tc, poonam.aggrwal-3arQi8VN3Tc, Pankaj Bansal
In-Reply-To: <1511430935-29783-1-git-send-email-pankaj.bansal-3arQi8VN3Tc@public.gmane.org>

The flexcan driver assumed that flexcan controller is big endian for
powerpc architecture and little endian for other architectures.

But this is not universally true. flexcan controller can be little or
big endian on any architecture.

Therefore the flexcan driver has been modified to check for "big-endian"
device tree property for controllers that are big endian.

consequently add the property to freescale P1010 SOC device tree.

Signed-off-by: Pankaj Bansal <pankaj.bansal-3arQi8VN3Tc@public.gmane.org>
Reviewed-by: Poonam Aggrwal <poonam.aggrwal-3arQi8VN3Tc@public.gmane.org>
---
Changes in v2:
  - No change.
  - Added one more patch in series.

 arch/powerpc/boot/dts/fsl/p1010si-post.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
index af12ead..1b4aafc 100644
--- a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
@@ -137,12 +137,14 @@
 		compatible = "fsl,p1010-flexcan";
 		reg = <0x1c000 0x1000>;
 		interrupts = <48 0x2 0 0>;
+		big-endian;
 	};
 
 	can1: can@1d000 {
 		compatible = "fsl,p1010-flexcan";
 		reg = <0x1d000 0x1000>;
 		interrupts = <61 0x2 0 0>;
+		big-endian;
 	};
 
 	L2: l2-cache-controller@20000 {
-- 
2.7.4

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^ permalink raw reply related
* [PATCH v2 1/4] Documentation : can : flexcan : Add big-endian property to device tree
From: Pankaj Bansal @ 2017-11-23  9:55 UTC (permalink / raw)
  To: wg-5Yr1BZd7O62+XT7JhA+gdA, mkl-bIcnvbaLZ9MEGnE8C9+IrQ,
	linux-can-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
	mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA
  Cc: V.Sethi-3arQi8VN3Tc, poonam.aggrwal-3arQi8VN3Tc, Pankaj Bansal

The FlexCAN controller can be modelled as little or big endian depending
on SOC design. This device tree property identifies the controller
endianness and the driver reads/writes controller registers based on
that.

This is optional property. i.e. if this property is not present in
device tree node then controller is assumed to be little endian. if this
property is present then controller is assumed to be big endian.

Signed-off-by: Pankaj Bansal <pankaj.bansal-3arQi8VN3Tc@public.gmane.org>
Reviewed-by: Poonam Aggrwal <poonam.aggrwal-3arQi8VN3Tc@public.gmane.org>
---
Changes in v2:
  - No change.
  - Added one more patch in series.

 Documentation/devicetree/bindings/net/can/fsl-flexcan.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
index 56d6cc3..bb081ba 100644
--- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
+++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
@@ -18,6 +18,8 @@ Optional properties:
 
 - xceiver-supply: Regulator that powers the CAN transceiver
 
+- big-endian: This means the registers of FlexCAN controller are big endian
+
 Example:
 
 	can@1c000 {
-- 
2.7.4

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^ permalink raw reply related
* [PATCH v2 3/4] arm/dts: Add nodes for flexcan devices present on LS1021A-Rev2 SoC
From: Pankaj Bansal @ 2017-11-23  9:55 UTC (permalink / raw)
  To: wg, mkl, linux-can, robh+dt, mark.rutland, devicetree
  Cc: V.Sethi, poonam.aggrwal, Pankaj Bansal, Bhupesh Sharma,
	Sakar Arora
In-Reply-To: <1511430935-29783-1-git-send-email-pankaj.bansal@nxp.com>

This patch adds the device nodes for flexcan controller(s) present on
LS1021A-Rev2 SoC.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
---
Changes in v2:
  - No change.
  - Added one more patch in series.

 arch/arm/boot/dts/ls1021a-qds.dts | 16 +++++++++++++
 arch/arm/boot/dts/ls1021a-twr.dts | 16 +++++++++++++
 arch/arm/boot/dts/ls1021a.dtsi    | 36 +++++++++++++++++++++++++++++
 3 files changed, 68 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9408753..4f211e3 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -331,3 +331,19 @@
 &uart1 {
 	status = "okay";
 };
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&can2 {
+	status = "disabled";
+};
+
+&can3 {
+	status = "disabled";
+};
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a8b148a..7202d9c 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -243,3 +243,19 @@
 &uart1 {
 	status = "okay";
 };
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&can2 {
+	status = "disabled";
+};
+
+&can3 {
+	status = "disabled";
+};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 9319e1f..7789031 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -730,5 +730,41 @@
 					<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		can0: can@2a70000 {
+			compatible = "fsl,ls1021ar2-flexcan";
+			reg = <0x0 0x2a70000 0x0 0x1000>;
+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
+			clock-names = "ipg", "per";
+			big-endian;
+		};
+
+		can1: can@2a80000 {
+			compatible = "fsl,ls1021ar2-flexcan";
+			reg = <0x0 0x2a80000 0x0 0x1000>;
+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
+			clock-names = "ipg", "per";
+			big-endian;
+		};
+
+		can2: can@2a90000 {
+			compatible = "fsl,ls1021ar2-flexcan";
+			reg = <0x0 0x2a90000 0x0 0x1000>;
+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
+			clock-names = "ipg", "per";
+			big-endian;
+		};
+
+		can3: can@2aa0000 {
+			compatible = "fsl,ls1021ar2-flexcan";
+			reg = <0x0 0x2aa0000 0x0 0x1000>;
+			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
+			clock-names = "ipg", "per";
+			big-endian;
+		};
 	};
 };
-- 
2.7.4


^ permalink raw reply related
* Re: [PATCH 0/7] R-Car D3 (r8a77995) CAN support
From: Simon Horman @ 2017-11-23  9:43 UTC (permalink / raw)
  To: Ulrich Hecht
  Cc: Linux-Renesas, linux-can, devicetree@vger.kernel.org,
	Wolfram Sang, Geert Uytterhoeven, Magnus Damm, Chris Paterson,
	Ramesh Shanmugasundaram
In-Reply-To: <CAO3366xk+Spa=z6bFW9TfqPk_8wUEd5scMK35JbXwpxZ2z7L2w@mail.gmail.com>

On Thu, Nov 23, 2017 at 08:43:18AM +0100, Ulrich Hecht wrote:
> On Wed, Nov 22, 2017 at 7:10 PM, Simon Horman <horms@verge.net.au> wrote:
> > On Fri, Nov 17, 2017 at 11:41:22AM +0100, Ulrich Hecht wrote:
> >> Hi!
> >>
> >> Here's CAN and CAN FD support for the R-Car D3. This is a by-the-datasheet
> >> implementation, with the datasheet missing some bits, namely the pin map.
> >> I filled in the gaps with frog DNA^W^W^Wby deducing the information from
> >> pin numbers already in the PFC driver, so careful scrutiny is advised.
> >>
> >> CU
> >> Uli
> >>
> >>
> >> Ulrich Hecht (7):
> >>   pinctrl: sh-pfc: r8a77995: Add CAN support
> >>   pinctrl: sh-pfc: r8a77995: Add CAN FD support
> >>   arm64: dts: r8a77995: Add CAN external clock support
> >>   arm64: dts: r8a77995: Add CAN support
> >>   arm64: dts: r8a77995: Add CAN FD support
> >>   can: rcar_can: document r8a77995 (R-Car D3) compatibility strings
> >>   can: rcar_canfd: document r8a77995 (R-Car D3) compatibility strings
> >
> > Hi Ulrich,
> >
> > is it safe, from a regression point of view, to apply the dts patches
> > to a tree that does not have the other patches present?
> 
> I believe it is.

Thanks. I have applied them for v4.16.

^ permalink raw reply
* Re: [PATCH v3 1/2] can: flexcan: Remodel FlexCAN register r/w APIs for big endian FlexCAN controllers.
From: Marc Kleine-Budde @ 2017-11-23  9:18 UTC (permalink / raw)
  To: Pankaj Bansal, wg, linux-can
  Cc: V.Sethi, poonam.aggrwal, Bhupesh Sharma, Sakar Arora
In-Reply-To: <1511428158-28710-1-git-send-email-pankaj.bansal@nxp.com>


[-- Attachment #1.1: Type: text/plain, Size: 1528 bytes --]

On 11/23/2017 10:09 AM, Pankaj Bansal wrote:
> The FlexCAN driver assumed that FlexCAN controller is big endian for
> powerpc architecture and little endian for other architectures.
> 
> But this may not be the case. FlexCAN controller can be little or big
> endian on any architecture. For e.g. NXP LS1021A ARM based SOC has big
> endian FlexCAN controller.
> 
> Therefore, the driver has been modified to add a provision for both
> types of controllers using an additional device tree property. On a
> "fsl,p1010-flexcan" device BE is default, on all other devices LE is.
> 
> Big Endian controllers should have "big-endian" set in the device tree.
> check "Documentation/devicetree/bindings/net/can/fsl-flexcan.txt" for
> usage.
> 
> This is the standard practice followed in linux. for more info check:
> Documentation/devicetree/bindings/common-properties.txt
> 
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
> Reviewed-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>

I'm missing the update of the fsl-flexcan.txt in this series.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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^ permalink raw reply
* Re: [PATCH v3 2/2] can: flexcan: adding platform specific details for LS1021A
From: Marc Kleine-Budde @ 2017-11-23  9:16 UTC (permalink / raw)
  To: Pankaj Bansal, wg, linux-can; +Cc: V.Sethi, poonam.aggrwal, Bhupesh Sharma
In-Reply-To: <1511428158-28710-2-git-send-email-pankaj.bansal@nxp.com>


[-- Attachment #1.1: Type: text/plain, Size: 3076 bytes --]

On 11/23/2017 10:09 AM, Pankaj Bansal wrote:
> This patch adds platform specific details for NXP SOC LS1021A to the
> flexcan driver code.
> 
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
> Reviewed-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
> ---
> Changes in v3:
>   - Add LS1021 in FLEXCAN hardware feature flags table
>   - Kept LS1021 compatible in one line, even if it's more than 80
>     chars.
>   - Add PERR_STATE quirk and USE_OFF_TIMESTAMP quirk and
>     ENABLE_EACEN_RRS quirk for LS1021A.
>   - Tested on LS1021A using "cangen can0 -D 11223344DEADBEEF -L 8 -R"
>     and "cangen can0 -D 11223344DEADBEEF -L 8"
> Changes in v2:
>   - No change.
> 
>  drivers/net/can/flexcan.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
> index 4c873fb..21d0dd8 100644
> --- a/drivers/net/can/flexcan.c
> +++ b/drivers/net/can/flexcan.c
> @@ -190,6 +190,7 @@
>   *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
>   *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
>   *   VF610 FlexCAN3  ?               no       yes         ?      yes       yes?
> + * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes

Out of curiosity, where have you got the IP core version from?

>   *
>   * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
>   */
> @@ -304,6 +305,13 @@ static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
>  		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
>  };
>  
> +/* LS1021A-Rev2 has functional RX-FIFO mode  */

That comment is obsolete, isn't it? If it's a noteworthy feature, add it
to the overview table above.

> +static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
> +	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
> +		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
> +		FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
> +};
> +
>  static const struct can_bittiming_const flexcan_bittiming_const = {
>  	.name = DRV_NAME,
>  	.tseg1_min = 4,
> @@ -1248,6 +1256,7 @@ static const struct of_device_id flexcan_of_match[] = {
>  	{ .compatible = "fsl,imx25-flexcan", .data = &fsl_p1010_devtype_data, },
>  	{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
>  	{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
> +	{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
>  	{ /* sentinel */ },
>  };
>  MODULE_DEVICE_TABLE(of, flexcan_of_match);
> 

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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^ permalink raw reply
* [PATCH v3 2/2] can: flexcan: adding platform specific details for LS1021A
From: Pankaj Bansal @ 2017-11-23  9:09 UTC (permalink / raw)
  To: wg, mkl, linux-can; +Cc: V.Sethi, poonam.aggrwal, Pankaj Bansal, Bhupesh Sharma
In-Reply-To: <1511428158-28710-1-git-send-email-pankaj.bansal@nxp.com>

This patch adds platform specific details for NXP SOC LS1021A to the
flexcan driver code.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
---
Changes in v3:
  - Add LS1021 in FLEXCAN hardware feature flags table
  - Kept LS1021 compatible in one line, even if it's more than 80
    chars.
  - Add PERR_STATE quirk and USE_OFF_TIMESTAMP quirk and
    ENABLE_EACEN_RRS quirk for LS1021A.
  - Tested on LS1021A using "cangen can0 -D 11223344DEADBEEF -L 8 -R"
    and "cangen can0 -D 11223344DEADBEEF -L 8"
Changes in v2:
  - No change.

 drivers/net/can/flexcan.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 4c873fb..21d0dd8 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -190,6 +190,7 @@
  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
  *   VF610 FlexCAN3  ?               no       yes         ?      yes       yes?
+ * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes
  *
  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
  */
@@ -304,6 +305,13 @@ static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
 };
 
+/* LS1021A-Rev2 has functional RX-FIFO mode  */
+static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
+	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
+		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
+		FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
+};
+
 static const struct can_bittiming_const flexcan_bittiming_const = {
 	.name = DRV_NAME,
 	.tseg1_min = 4,
@@ -1248,6 +1256,7 @@ static const struct of_device_id flexcan_of_match[] = {
 	{ .compatible = "fsl,imx25-flexcan", .data = &fsl_p1010_devtype_data, },
 	{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
 	{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
+	{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
 	{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, flexcan_of_match);
-- 
2.7.4


^ permalink raw reply related
* [PATCH v3 1/2] can: flexcan: Remodel FlexCAN register r/w APIs for big endian FlexCAN controllers.
From: Pankaj Bansal @ 2017-11-23  9:09 UTC (permalink / raw)
  To: wg, mkl, linux-can
  Cc: V.Sethi, poonam.aggrwal, Pankaj Bansal, Bhupesh Sharma,
	Sakar Arora
In-Reply-To: <1510660589-16125-1-git-send-email-pankaj.bansal@nxp.com>

The FlexCAN driver assumed that FlexCAN controller is big endian for
powerpc architecture and little endian for other architectures.

But this may not be the case. FlexCAN controller can be little or big
endian on any architecture. For e.g. NXP LS1021A ARM based SOC has big
endian FlexCAN controller.

Therefore, the driver has been modified to add a provision for both
types of controllers using an additional device tree property. On a
"fsl,p1010-flexcan" device BE is default, on all other devices LE is.

Big Endian controllers should have "big-endian" set in the device tree.
check "Documentation/devicetree/bindings/net/can/fsl-flexcan.txt" for
usage.

This is the standard practice followed in linux. for more info check:
Documentation/devicetree/bindings/common-properties.txt

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
---
Changes in v3:
  - Added fsl,imx25-flexcan, fsl,imx35-flexcan and fsl,imx53-flexcan
    support to the driver.
Changes in v2:
  - Modified patch deciption to include common-properties.txt reference.
  - Reorder the LE/BE read/write APIs for better readability of code
  - Added an exception to force BE API selection, for powerpc based platform
    P1010. This ensures that new linux kernel works with old P1010
    device-tree, while future powerpc platforms that use big endian
    FlexCAN controller need to specify big-endian in device tree in
    FlexCAN node.
  - Tested on P1010 after backporting to freescale sdk 1.4 linux, without
    any change in device-tree.
  - Tested on NXP LS1021A arm based platform.

 drivers/net/can/flexcan.c | 233 ++++++++++++++++++++----------------
 1 file changed, 131 insertions(+), 102 deletions(-)

diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index a13a489..4c873fb 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -279,6 +279,10 @@ struct flexcan_priv {
 	struct clk *clk_per;
 	const struct flexcan_devtype_data *devtype_data;
 	struct regulator *reg_xceiver;
+
+	/* Read and Write APIs */
+	u32 (*read)(void __iomem *addr);
+	void (*write)(u32 val, void __iomem *addr);
 };
 
 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
@@ -312,39 +316,45 @@ static const struct can_bittiming_const flexcan_bittiming_const = {
 	.brp_inc = 1,
 };
 
-/* Abstract off the read/write for arm versus ppc. This
- * assumes that PPC uses big-endian registers and everything
- * else uses little-endian registers, independent of CPU
- * endianness.
+/* FlexCAN module is essentially modelled as a little-endian IP in most
+ * SoCs, i.e the registers as well as the message buffer areas are
+ * implemented in a little-endian fashion.
+ *
+ * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
+ * module in a big-endian fashion (i.e the registers as well as the
+ * message buffer areas are implemented in a big-endian way).
+ *
+ * In addition, the FlexCAN module can be found on SoCs having ARM or
+ * PPC cores. So, we need to abstract off the register read/write
+ * functions, ensuring that these cater to all the combinations of module
+ * endianness and underlying CPU endianness.
  */
-#if defined(CONFIG_PPC)
-static inline u32 flexcan_read(void __iomem *addr)
+static inline u32 flexcan_read_be(void __iomem *addr)
 {
-	return in_be32(addr);
+	return ioread32be(addr);
 }
 
-static inline void flexcan_write(u32 val, void __iomem *addr)
+static inline void flexcan_write_be(u32 val, void __iomem *addr)
 {
-	out_be32(addr, val);
+	iowrite32be(val, addr);
 }
-#else
-static inline u32 flexcan_read(void __iomem *addr)
+
+static inline u32 flexcan_read_le(void __iomem *addr)
 {
-	return readl(addr);
+	return ioread32(addr);
 }
 
-static inline void flexcan_write(u32 val, void __iomem *addr)
+static inline void flexcan_write_le(u32 val, void __iomem *addr)
 {
-	writel(val, addr);
+	iowrite32(val, addr);
 }
-#endif
 
 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 {
 	struct flexcan_regs __iomem *regs = priv->regs;
 	u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 
-	flexcan_write(reg_ctrl, &regs->ctrl);
+	priv->write(reg_ctrl, &regs->ctrl);
 }
 
 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
@@ -352,7 +362,7 @@ static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 	struct flexcan_regs __iomem *regs = priv->regs;
 	u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 
-	flexcan_write(reg_ctrl, &regs->ctrl);
+	priv->write(reg_ctrl, &regs->ctrl);
 }
 
 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
@@ -377,14 +387,14 @@ static int flexcan_chip_enable(struct flexcan_priv *priv)
 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 	u32 reg;
 
-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
 	reg &= ~FLEXCAN_MCR_MDIS;
-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
 
-	while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 		udelay(10);
 
-	if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
+	if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 		return -ETIMEDOUT;
 
 	return 0;
@@ -396,14 +406,14 @@ static int flexcan_chip_disable(struct flexcan_priv *priv)
 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 	u32 reg;
 
-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
 	reg |= FLEXCAN_MCR_MDIS;
-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
 
-	while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 		udelay(10);
 
-	if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 		return -ETIMEDOUT;
 
 	return 0;
@@ -415,14 +425,14 @@ static int flexcan_chip_freeze(struct flexcan_priv *priv)
 	unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
 	u32 reg;
 
-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
 	reg |= FLEXCAN_MCR_HALT;
-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
 
-	while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 		udelay(100);
 
-	if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 		return -ETIMEDOUT;
 
 	return 0;
@@ -434,14 +444,14 @@ static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 	u32 reg;
 
-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
 	reg &= ~FLEXCAN_MCR_HALT;
-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
 
-	while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 		udelay(10);
 
-	if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
+	if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 		return -ETIMEDOUT;
 
 	return 0;
@@ -452,11 +462,11 @@ static int flexcan_chip_softreset(struct flexcan_priv *priv)
 	struct flexcan_regs __iomem *regs = priv->regs;
 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 
-	flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
-	while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
+	priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
+	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 		udelay(10);
 
-	if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
+	if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 		return -ETIMEDOUT;
 
 	return 0;
@@ -467,7 +477,7 @@ static int __flexcan_get_berr_counter(const struct net_device *dev,
 {
 	const struct flexcan_priv *priv = netdev_priv(dev);
 	struct flexcan_regs __iomem *regs = priv->regs;
-	u32 reg = flexcan_read(&regs->ecr);
+	u32 reg = priv->read(&regs->ecr);
 
 	bec->txerr = (reg >> 0) & 0xff;
 	bec->rxerr = (reg >> 8) & 0xff;
@@ -523,24 +533,24 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
 	if (cf->can_dlc > 0) {
 		data = be32_to_cpup((__be32 *)&cf->data[0]);
-		flexcan_write(data, &priv->tx_mb->data[0]);
+		priv->write(data, &priv->tx_mb->data[0]);
 	}
 	if (cf->can_dlc > 3) {
 		data = be32_to_cpup((__be32 *)&cf->data[4]);
-		flexcan_write(data, &priv->tx_mb->data[1]);
+		priv->write(data, &priv->tx_mb->data[1]);
 	}
 
 	can_put_echo_skb(skb, dev, 0);
 
-	flexcan_write(can_id, &priv->tx_mb->can_id);
-	flexcan_write(ctrl, &priv->tx_mb->can_ctrl);
+	priv->write(can_id, &priv->tx_mb->can_id);
+	priv->write(ctrl, &priv->tx_mb->can_ctrl);
 
 	/* Errata ERR005829 step8:
 	 * Write twice INACTIVE(0x8) code to first MB.
 	 */
-	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 		      &priv->tx_mb_reserved->can_ctrl);
-	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 		      &priv->tx_mb_reserved->can_ctrl);
 
 	return NETDEV_TX_OK;
@@ -659,7 +669,7 @@ static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
 		u32 code;
 
 		do {
-			reg_ctrl = flexcan_read(&mb->can_ctrl);
+			reg_ctrl = priv->read(&mb->can_ctrl);
 		} while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
 
 		/* is this MB empty? */
@@ -674,17 +684,17 @@ static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
 			offload->dev->stats.rx_errors++;
 		}
 	} else {
-		reg_iflag1 = flexcan_read(&regs->iflag1);
+		reg_iflag1 = priv->read(&regs->iflag1);
 		if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
 			return 0;
 
-		reg_ctrl = flexcan_read(&mb->can_ctrl);
+		reg_ctrl = priv->read(&mb->can_ctrl);
 	}
 
 	/* increase timstamp to full 32 bit */
 	*timestamp = reg_ctrl << 16;
 
-	reg_id = flexcan_read(&mb->can_id);
+	reg_id = priv->read(&mb->can_id);
 	if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 		cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 	else
@@ -694,19 +704,19 @@ static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
 		cf->can_id |= CAN_RTR_FLAG;
 	cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 
-	*(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
-	*(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
+	*(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
+	*(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
 
 	/* mark as read */
 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 		/* Clear IRQ */
 		if (n < 32)
-			flexcan_write(BIT(n), &regs->iflag1);
+			priv->write(BIT(n), &regs->iflag1);
 		else
-			flexcan_write(BIT(n - 32), &regs->iflag2);
+			priv->write(BIT(n - 32), &regs->iflag2);
 	} else {
-		flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
-		flexcan_read(&regs->timer);
+		priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
+		priv->read(&regs->timer);
 	}
 
 	return 1;
@@ -718,8 +728,8 @@ static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
 	struct flexcan_regs __iomem *regs = priv->regs;
 	u32 iflag1, iflag2;
 
-	iflag2 = flexcan_read(&regs->iflag2) & priv->reg_imask2_default;
-	iflag1 = flexcan_read(&regs->iflag1) & priv->reg_imask1_default &
+	iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default;
+	iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default &
 		~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
 
 	return (u64)iflag2 << 32 | iflag1;
@@ -735,7 +745,7 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
 	u32 reg_iflag1, reg_esr;
 	enum can_state last_state = priv->can.state;
 
-	reg_iflag1 = flexcan_read(&regs->iflag1);
+	reg_iflag1 = priv->read(&regs->iflag1);
 
 	/* reception interrupt */
 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
@@ -758,7 +768,8 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
 		/* FIFO overflow interrupt */
 		if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
 			handled = IRQ_HANDLED;
-			flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
+			priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
+				    &regs->iflag1);
 			dev->stats.rx_over_errors++;
 			dev->stats.rx_errors++;
 		}
@@ -772,18 +783,18 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
 		can_led_event(dev, CAN_LED_EVENT_TX);
 
 		/* after sending a RTR frame MB is in RX mode */
-		flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
-			      &priv->tx_mb->can_ctrl);
-		flexcan_write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag1);
+		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
+			    &priv->tx_mb->can_ctrl);
+		priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag1);
 		netif_wake_queue(dev);
 	}
 
-	reg_esr = flexcan_read(&regs->esr);
+	reg_esr = priv->read(&regs->esr);
 
 	/* ACK all bus error and state change IRQ sources */
 	if (reg_esr & FLEXCAN_ESR_ALL_INT) {
 		handled = IRQ_HANDLED;
-		flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
+		priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 	}
 
 	/* state change interrupt or broken error state quirk fix is enabled */
@@ -845,7 +856,7 @@ static void flexcan_set_bittiming(struct net_device *dev)
 	struct flexcan_regs __iomem *regs = priv->regs;
 	u32 reg;
 
-	reg = flexcan_read(&regs->ctrl);
+	reg = priv->read(&regs->ctrl);
 	reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
 		 FLEXCAN_CTRL_RJW(0x3) |
 		 FLEXCAN_CTRL_PSEG1(0x7) |
@@ -869,11 +880,11 @@ static void flexcan_set_bittiming(struct net_device *dev)
 		reg |= FLEXCAN_CTRL_SMP;
 
 	netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
-	flexcan_write(reg, &regs->ctrl);
+	priv->write(reg, &regs->ctrl);
 
 	/* print chip status */
 	netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
-		   flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
+		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
 }
 
 /* flexcan_chip_start
@@ -912,7 +923,7 @@ static int flexcan_chip_start(struct net_device *dev)
 	 * choose format C
 	 * set max mailbox number
 	 */
-	reg_mcr = flexcan_read(&regs->mcr);
+	reg_mcr = priv->read(&regs->mcr);
 	reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
 	reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
 		FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
@@ -926,7 +937,7 @@ static int flexcan_chip_start(struct net_device *dev)
 			FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
 	}
 	netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
-	flexcan_write(reg_mcr, &regs->mcr);
+	priv->write(reg_mcr, &regs->mcr);
 
 	/* CTRL
 	 *
@@ -939,7 +950,7 @@ static int flexcan_chip_start(struct net_device *dev)
 	 * enable bus off interrupt
 	 * (== FLEXCAN_CTRL_ERR_STATE)
 	 */
-	reg_ctrl = flexcan_read(&regs->ctrl);
+	reg_ctrl = priv->read(&regs->ctrl);
 	reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
 	reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
 		FLEXCAN_CTRL_ERR_STATE;
@@ -959,45 +970,45 @@ static int flexcan_chip_start(struct net_device *dev)
 	/* leave interrupts disabled for now */
 	reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
 	netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
-	flexcan_write(reg_ctrl, &regs->ctrl);
+	priv->write(reg_ctrl, &regs->ctrl);
 
 	if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
-		reg_ctrl2 = flexcan_read(&regs->ctrl2);
+		reg_ctrl2 = priv->read(&regs->ctrl2);
 		reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
-		flexcan_write(reg_ctrl2, &regs->ctrl2);
+		priv->write(reg_ctrl2, &regs->ctrl2);
 	}
 
 	/* clear and invalidate all mailboxes first */
 	for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
-		flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
-			      &regs->mb[i].can_ctrl);
+		priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
+			    &regs->mb[i].can_ctrl);
 	}
 
 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 		for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++)
-			flexcan_write(FLEXCAN_MB_CODE_RX_EMPTY,
-				      &regs->mb[i].can_ctrl);
+			priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
+				    &regs->mb[i].can_ctrl);
 	}
 
 	/* Errata ERR005829: mark first TX mailbox as INACTIVE */
-	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
-		      &priv->tx_mb_reserved->can_ctrl);
+	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
+		    &priv->tx_mb_reserved->can_ctrl);
 
 	/* mark TX mailbox as INACTIVE */
-	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
-		      &priv->tx_mb->can_ctrl);
+	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
+		    &priv->tx_mb->can_ctrl);
 
 	/* acceptance mask/acceptance code (accept everything) */
-	flexcan_write(0x0, &regs->rxgmask);
-	flexcan_write(0x0, &regs->rx14mask);
-	flexcan_write(0x0, &regs->rx15mask);
+	priv->write(0x0, &regs->rxgmask);
+	priv->write(0x0, &regs->rx14mask);
+	priv->write(0x0, &regs->rx15mask);
 
 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
-		flexcan_write(0x0, &regs->rxfgmask);
+		priv->write(0x0, &regs->rxfgmask);
 
 	/* clear acceptance filters */
 	for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
-		flexcan_write(0, &regs->rximr[i]);
+		priv->write(0, &regs->rximr[i]);
 
 	/* On Vybrid, disable memory error detection interrupts
 	 * and freeze mode.
@@ -1010,16 +1021,16 @@ static int flexcan_chip_start(struct net_device *dev)
 		 * and Correction of Memory Errors" to write to
 		 * MECR register
 		 */
-		reg_ctrl2 = flexcan_read(&regs->ctrl2);
+		reg_ctrl2 = priv->read(&regs->ctrl2);
 		reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
-		flexcan_write(reg_ctrl2, &regs->ctrl2);
+		priv->write(reg_ctrl2, &regs->ctrl2);
 
-		reg_mecr = flexcan_read(&regs->mecr);
+		reg_mecr = priv->read(&regs->mecr);
 		reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
-		flexcan_write(reg_mecr, &regs->mecr);
+		priv->write(reg_mecr, &regs->mecr);
 		reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
 			      FLEXCAN_MECR_FANCEI_MSK);
-		flexcan_write(reg_mecr, &regs->mecr);
+		priv->write(reg_mecr, &regs->mecr);
 	}
 
 	err = flexcan_transceiver_enable(priv);
@@ -1035,14 +1046,14 @@ static int flexcan_chip_start(struct net_device *dev)
 
 	/* enable interrupts atomically */
 	disable_irq(dev->irq);
-	flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
-	flexcan_write(priv->reg_imask1_default, &regs->imask1);
-	flexcan_write(priv->reg_imask2_default, &regs->imask2);
+	priv->write(priv->reg_ctrl_default, &regs->ctrl);
+	priv->write(priv->reg_imask1_default, &regs->imask1);
+	priv->write(priv->reg_imask2_default, &regs->imask2);
 	enable_irq(dev->irq);
 
 	/* print chip status */
 	netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
-		   flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
+		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
 
 	return 0;
 
@@ -1067,10 +1078,10 @@ static void flexcan_chip_stop(struct net_device *dev)
 	flexcan_chip_disable(priv);
 
 	/* Disable all interrupts */
-	flexcan_write(0, &regs->imask2);
-	flexcan_write(0, &regs->imask1);
-	flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
-		      &regs->ctrl);
+	priv->write(0, &regs->imask2);
+	priv->write(0, &regs->imask1);
+	priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+		    &regs->ctrl);
 
 	flexcan_transceiver_disable(priv);
 	priv->can.state = CAN_STATE_STOPPED;
@@ -1185,26 +1196,26 @@ static int register_flexcandev(struct net_device *dev)
 	err = flexcan_chip_disable(priv);
 	if (err)
 		goto out_disable_per;
-	reg = flexcan_read(&regs->ctrl);
+	reg = priv->read(&regs->ctrl);
 	reg |= FLEXCAN_CTRL_CLK_SRC;
-	flexcan_write(reg, &regs->ctrl);
+	priv->write(reg, &regs->ctrl);
 
 	err = flexcan_chip_enable(priv);
 	if (err)
 		goto out_chip_disable;
 
 	/* set freeze, halt and activate FIFO, restrict register access */
-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
 	reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
 		FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
 
 	/* Currently we only support newer versions of this core
 	 * featuring a RX hardware FIFO (although this driver doesn't
 	 * make use of it on some cores). Older cores, found on some
 	 * Coldfire derivates are not tested.
 	 */
-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
 	if (!(reg & FLEXCAN_MCR_FEN)) {
 		netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
 		err = -ENODEV;
@@ -1232,6 +1243,9 @@ static void unregister_flexcandev(struct net_device *dev)
 static const struct of_device_id flexcan_of_match[] = {
 	{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
 	{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
+	{ .compatible = "fsl,imx53-flexcan", .data = &fsl_p1010_devtype_data, },
+	{ .compatible = "fsl,imx35-flexcan", .data = &fsl_p1010_devtype_data, },
+	{ .compatible = "fsl,imx25-flexcan", .data = &fsl_p1010_devtype_data, },
 	{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
 	{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
 	{ /* sentinel */ },
@@ -1313,6 +1327,21 @@ static int flexcan_probe(struct platform_device *pdev)
 	dev->flags |= IFF_ECHO;
 
 	priv = netdev_priv(dev);
+
+	if (of_property_read_bool(pdev->dev.of_node, "big-endian")) {
+		priv->read = flexcan_read_be;
+		priv->write = flexcan_write_be;
+	} else {
+		if (of_device_is_compatible(pdev->dev.of_node,
+					    "fsl,p1010-flexcan")) {
+			priv->read = flexcan_read_be;
+			priv->write = flexcan_write_be;
+		} else {
+			priv->read = flexcan_read_le;
+			priv->write = flexcan_write_le;
+		}
+	}
+
 	priv->can.clock.freq = clock_freq;
 	priv->can.bittiming_const = &flexcan_bittiming_const;
 	priv->can.do_set_mode = flexcan_set_mode;
-- 
2.7.4


^ permalink raw reply related
* Re: [PATCH 0/7] R-Car D3 (r8a77995) CAN support
From: Ulrich Hecht @ 2017-11-23  7:43 UTC (permalink / raw)
  To: Simon Horman
  Cc: Linux-Renesas, linux-can-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Wolfram Sang,
	Geert Uytterhoeven, Magnus Damm, Chris Paterson,
	Ramesh Shanmugasundaram
In-Reply-To: <20171122181045.5pstmikwp43idts5-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>

On Wed, Nov 22, 2017 at 7:10 PM, Simon Horman <horms-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org> wrote:
> On Fri, Nov 17, 2017 at 11:41:22AM +0100, Ulrich Hecht wrote:
>> Hi!
>>
>> Here's CAN and CAN FD support for the R-Car D3. This is a by-the-datasheet
>> implementation, with the datasheet missing some bits, namely the pin map.
>> I filled in the gaps with frog DNA^W^W^Wby deducing the information from
>> pin numbers already in the PFC driver, so careful scrutiny is advised.
>>
>> CU
>> Uli
>>
>>
>> Ulrich Hecht (7):
>>   pinctrl: sh-pfc: r8a77995: Add CAN support
>>   pinctrl: sh-pfc: r8a77995: Add CAN FD support
>>   arm64: dts: r8a77995: Add CAN external clock support
>>   arm64: dts: r8a77995: Add CAN support
>>   arm64: dts: r8a77995: Add CAN FD support
>>   can: rcar_can: document r8a77995 (R-Car D3) compatibility strings
>>   can: rcar_canfd: document r8a77995 (R-Car D3) compatibility strings
>
> Hi Ulrich,
>
> is it safe, from a regression point of view, to apply the dts patches
> to a tree that does not have the other patches present?

I believe it is.

CU
Uli
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^ permalink raw reply
* RE: [PATCH v2 2/2] can: flexcan: adding platform specific details for LS1021A
From: ZHU Yi (ST-FIR/ENG1-Zhu) @ 2017-11-23  7:23 UTC (permalink / raw)
  To: Pankaj Bansal, Wolfgang Grandegger, Marc Kleine-Budde,
	linux-can@vger.kernel.org
  Cc: Varun Sethi, Poonam Aggrwal
In-Reply-To: <AM0PR0402MB39409B1DD5ED9355F12EC85CF1230@AM0PR0402MB3940.eurprd04.prod.outlook.com>

Hello Pankaj,

>From: Pankaj Bansal [mailto:pankaj.bansal@nxp.com]
>Sent: Tuesday, November 21, 2017 6:02 PM
> [...]
>Without PERR_STATE :
>
>root@TinyDistro:~# ip link set can0 up type can bitrate 125000 restart-ms 100 berr-reporting off
>[   22.507345] IPv6: ADDRCONF(NETDEV_CHANGE): can0: link becomes ready
>root@TinyDistro:~# ip link set can1 up type can bitrate 125000 restart-ms 100 berr-reporting off
>[   30.934669] IPv6: ADDRCONF(NETDEV_CHANGE): can1: link becomes ready
>root@TinyDistro:~# candump -td -e any,0:0,#FFFFFFFF &
>[1] 617
>root@TinyDistro:~# cangen can0 -D 11223344DEADBEEF -L 8
>[   48.684839] flexcan_irq 804 reg_esr=0x00062242, reg_ecr=0x00000060, reg_ctrl=0x4a31ac55
> (000.000000)  can0  20000004   [8]  00 08 00 00 00 00 00 00   ERRORFRAME
>        controller-problem{tx-error-warning}
>write: No buffer space available
>        **********  Short L and H signals of CAN ************
>root@TinyDistro:~# [  228.338038] flexcan_irq 804 reg_esr=0x00006036, reg_ecr=0x00000000, reg_ctrl=0x4a31ac55
> (179.653204)  can0  20000040   [8]  00 00 00 00 00 00 00 00   ERRORFRAME
>        bus-off
>[  228.438287] IPv6: ADDRCONF(NETDEV_CHANGE): can0: link becomes ready
> (000.092122)  can0  20000100   [8]  00 00 00 00 00 00 00 00   ERRORFRAME
>        restarted-after-bus-off
>
>With PERR_STATE :
>
>root@TinyDistro:~# ip link set can0 up type can bitrate 125000 restart-ms 100 berr-reporting off
>[   31.997286] IPv6: ADDRCONF(NETDEV_CHANGE): can0: link becomes ready
>root@TinyDistro:~# ip link set can1 up type can bitrate 125000 restart-ms 100 berr-reporting off
>[   40.934824] IPv6: ADDRCONF(NETDEV_CHANGE): can1: link becomes ready
>root@TinyDistro:~# candump -td -e any,0:0,#FFFFFFFF &
>[1] 620
>root@TinyDistro:~# cangen can0 -D 11223344DEADBEEF -L 8
>[   59.314920] flexcan_irq 805 reg_esr=0x00062242, reg_ecr=0x00000060, reg_ctrl=0x4a31ac55
> (000.000000)  [   59.323862] flexcan_irq 805 reg_esr=0x00042252, reg_ecr=0x00000080, reg_ctrl=0x4a31ec55
>can0  20000004   [8]  00 08 00 00 00 00 00 00   ERRORFRAME
>        controller-problem{tx-error-warning}
> (000.009673)  can0  20000004   [8]  00 20 00 00 00 00 00 00   ERRORFRAME
>        controller-problem{tx-error-passive}
>write: No buffer space available
>        **********  Short L and H signals of CAN ************
>root@TinyDistro:~# [   87.995878] flexcan_irq 805 reg_esr=0x00006036, reg_ecr=0x00000000, reg_ctrl=0x4a31ac55
> (028.671291)  can0  20000040   [8]  00 00 00 00 00 00 00 00   ERRORFRAME
>        bus-off
> (000.094305)  [   88.098464] IPv6: ADDRCONF(NETDEV_CHANGE): can0: link becomes ready
>can0  20000100   [8]  00 00 00 00 00 00 00 00   ERRORFRAME
>        restarted-after-bus-off

Seems the state increase can be reported correctly, and the state
decrease should also works fine, thanks for the test results!

Best regards
Yi



^ permalink raw reply
* RE: [PATCH v2 2/2] can: flexcan: adding platform specific details for LS1021A
From: ZHU Yi (ST-FIR/ENG1-Zhu) @ 2017-11-23  1:26 UTC (permalink / raw)
  To: Marc Kleine-Budde, Pankaj Bansal, Wolfgang Grandegger,
	linux-can@vger.kernel.org
  Cc: Varun Sethi, Poonam Aggrwal, Stefan Agner
In-Reply-To: <ced1aea2-144d-9bd5-8ab7-b19492512815@pengutronix.de>

Hello Marc,

>From: Marc Kleine-Budde [mailto:mkl@pengutronix.de]
>Sent: Wednesday, November 22, 2017 8:00 PM
>
>On 11/22/2017 03:56 AM, ZHU Yi (ST-FIR/ENG1-Zhu) wrote:
>>>> I'm afraid so far no known flexcan core supports it.
>>>
>>> Should we update the table and add a "IRQ Err Passive" no for all
>>> cores?
>> By look into the reference manual of MX25[1], MX35[2] and VF610[3],
>> it turns out that none of them support the error passive interrupt.
>> So we should update the "IRQ Err Passive" to no for all cores.
>
>I'll create a patch.
Thanks! :)

>
>> Interestingly, seems the new RM of MX25 (Rev.2) and MX35 (Rev.3)
>> states that both core have the [TR]WRN_INT connected, so I guess the
>> no in that column were added for the legacy core.
>
>What do you mean by connected exactly?
>
>As fas as I know these IP cores have these interrupts lines, but they
>are not properly wired to the IRQ line that leaves the IP core. To quote
>Shawn Guo from the discussion back in 2012:
>
>>> From what I can tell, i.MX35, i.MX51 and i.MX53 use the same version,
>>> so they should all have the bug.  And for i.MX6Q, since it uses a newer
>>> version even than i.MX28, I would believe it's affected by the bug.
>>> But I'm copying Dong who should have better knowledge about this to
>>> confirm.
>
>Further Dong Aisheng says:
>
>>> Our IC owner double checked the MX35 and MX53 IP and found the
>>> RX_WARN & TX_WARN Interrupt source actually are not connected to
>>> ARM. That means flexcan will not trigger interrupt to ARM core even
>>> RX_WARN or TX_WARN Happens. This may be the root cause that why you
>>> cannot see RX_WARN interrupt if not enable bus error interrupt on
>>> mx35. He also checked that mx6q has the rx/tx warning interrupt
>>> connected to arm. So we guess mx6q does not have this issue.
>>> Anyway, we can test to confirm.
>
Ah, that's the reason behind, thanks for dig into the history and
sharing the knowledge with us. :)

>> However, as the driver also needs to work with the legacy core, and
>> they share the same devtype_data as p1010, so I think we should leave
>> it as it is.
>
>>>>  * Below is some version info we got:
>>>>  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
>>>>  *                                Filter? connected?  Passive detection  ception in MB
>>>>  *   MX25  FlexCAN2  03.00.00.00     no        no         ?       no        no
>>>>  *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
>>>>  *   MX35  FlexCAN2  03.00.00.00     no        no         ?       no        no
>>>>  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
>>>>  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
>>>>  *   VF610 FlexCAN3  ?               no       yes         ?      yes       yes?
>>>
>>> And does it make sense to add "FLEXCAN_QUIRK_BROKEN_PERR_STATE" to the
>>> vf610, too?
>
>> I think vf610 will need this quirk to report correct state transitions.
>> The reason last time we do not touch this is because neither Wolfgang
>> nor I had access to vf610, so we can only test with MX28, MX53 and MX6.
>> We thought someone will speak out if they meet problems with this core,
>> and then they can help to fix and test it.
>
>Cc'ed Stefan Agner - maybe he has access to this SoC.
>
>> @Marc, @Wolfgang,
>> What do you think? Or shall we fix first and then wait?
>
>Let's wait if Stefan can test, otherwise just fix.
OK.

Best regards
Yi

^ permalink raw reply
* Re: [PATCH 0/7] R-Car D3 (r8a77995) CAN support
From: Simon Horman @ 2017-11-22 18:10 UTC (permalink / raw)
  To: Ulrich Hecht
  Cc: linux-renesas-soc, linux-can, devicetree, wsa, geert, magnus.damm,
	chris.paterson2, ramesh.shanmugasundaram
In-Reply-To: <1510915289-15059-1-git-send-email-ulrich.hecht+renesas@gmail.com>

On Fri, Nov 17, 2017 at 11:41:22AM +0100, Ulrich Hecht wrote:
> Hi!
> 
> Here's CAN and CAN FD support for the R-Car D3. This is a by-the-datasheet
> implementation, with the datasheet missing some bits, namely the pin map.
> I filled in the gaps with frog DNA^W^W^Wby deducing the information from
> pin numbers already in the PFC driver, so careful scrutiny is advised.
> 
> CU
> Uli
> 
> 
> Ulrich Hecht (7):
>   pinctrl: sh-pfc: r8a77995: Add CAN support
>   pinctrl: sh-pfc: r8a77995: Add CAN FD support
>   arm64: dts: r8a77995: Add CAN external clock support
>   arm64: dts: r8a77995: Add CAN support
>   arm64: dts: r8a77995: Add CAN FD support
>   can: rcar_can: document r8a77995 (R-Car D3) compatibility strings
>   can: rcar_canfd: document r8a77995 (R-Car D3) compatibility strings

Hi Ulrich,

is it safe, from a regression point of view, to apply the dts patches
to a tree that does not have the other patches present?

^ permalink raw reply
* Re: [PATCH v2 2/2] can: flexcan: adding platform specific details for LS1021A
From: Marc Kleine-Budde @ 2017-11-22 13:56 UTC (permalink / raw)
  To: Pankaj Bansal, ZHU Yi (ST-FIR/ENG1-Zhu), Wolfgang Grandegger,
	linux-can@vger.kernel.org
  Cc: Varun Sethi, Poonam Aggrwal
In-Reply-To: <DB3PR0402MB394710921822B0FFE6D827ECF1200@DB3PR0402MB3947.eurprd04.prod.outlook.com>


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On 11/22/2017 07:27 AM, Pankaj Bansal wrote:
> Hi ZHU Yi,
> 
> 
>> From: ZHU Yi (ST-FIR/ENG1-Zhu) [mailto:Yi.Zhu5@cn.bosch.com]
>> Sent: Wednesday, November 22, 2017 8:27 AM
>>> [...]
>> @Pankaj, as you are currently working on patch this driver, is it possible that
>> you can help to create patch for the table and/or the PERR_STATE quirk fix
>> for vf610 in case required? Thanks!
>>
> 
> I am afraid I also do not have access to vf610. I have access to p1010.

Please go ahead and test there.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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^ permalink raw reply
* Re: [PATCH 7/7] can: rcar_canfd: document r8a77995 (R-Car D3) compatibility strings
From: Geert Uytterhoeven @ 2017-11-22 13:20 UTC (permalink / raw)
  To: Ulrich Hecht
  Cc: Linux-Renesas, linux-can, devicetree@vger.kernel.org,
	Wolfram Sang, Simon Horman, Magnus Damm, Chris Paterson,
	Ramesh Shanmugasundaram
In-Reply-To: <1510915289-15059-8-git-send-email-ulrich.hecht+renesas@gmail.com>

Hi Ulrich,

On Fri, Nov 17, 2017 at 11:41 AM, Ulrich Hecht
<ulrich.hecht+renesas@gmail.com> wrote:
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>

Thanks for your patch!

With the below fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> --- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> +++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt

> @@ -24,12 +25,12 @@ The name of the child nodes are "channel0" and "channel1" respectively. Each
>  child node supports the "status" property only, which is used to
>  enable/disable the respective channel.
>
> -Required properties for "renesas,r8a7795-canfd" and "renesas,r8a7796-canfd"
> -compatible:
> -In R8A7795 and R8A7796 SoCs, canfd clock is a div6 clock and can be used by both
> -CAN and CAN FD controller at the same time. It needs to be scaled to maximum
> -frequency if any of these controllers use it. This is done using the below
> -properties:
> +Required properties for "renesas,r8a7795-canfd", "renesas,r8a7796-canfd" and
> +"renesas,r8a77995" compatible:

"renesas,r8a77995-canfd"

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply
* Re: [PATCH 6/7] can: rcar_can: document r8a77995 (R-Car D3) compatibility strings
From: Geert Uytterhoeven @ 2017-11-22 13:18 UTC (permalink / raw)
  To: Ulrich Hecht
  Cc: Linux-Renesas, linux-can, devicetree@vger.kernel.org,
	Wolfram Sang, Simon Horman, Magnus Damm, Chris Paterson,
	Ramesh Shanmugasundaram
In-Reply-To: <1510915289-15059-7-git-send-email-ulrich.hecht+renesas@gmail.com>

On Fri, Nov 17, 2017 at 11:41 AM, Ulrich Hecht
<ulrich.hecht+renesas@gmail.com> wrote:
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply
* Re: [PATCH 5/7] arm64: dts: r8a77995: Add CAN FD support
From: Geert Uytterhoeven @ 2017-11-22 13:18 UTC (permalink / raw)
  To: Ulrich Hecht
  Cc: Linux-Renesas, linux-can, devicetree@vger.kernel.org,
	Wolfram Sang, Simon Horman, Magnus Damm, Chris Paterson,
	Ramesh Shanmugasundaram
In-Reply-To: <1510915289-15059-6-git-send-email-ulrich.hecht+renesas@gmail.com>

On Fri, Nov 17, 2017 at 11:41 AM, Ulrich Hecht
<ulrich.hecht+renesas@gmail.com> wrote:
> Adds CAN FD controller node for r8a77995.
>
> Based on a patch for r8a7796 by Chris Paterson.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply
* Re: [PATCH 4/7] arm64: dts: r8a77995: Add CAN support
From: Geert Uytterhoeven @ 2017-11-22 13:16 UTC (permalink / raw)
  To: Ulrich Hecht
  Cc: Linux-Renesas, linux-can-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Wolfram Sang,
	Simon Horman, Magnus Damm, Chris Paterson,
	Ramesh Shanmugasundaram
In-Reply-To: <1510915289-15059-5-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

On Fri, Nov 17, 2017 at 11:41 AM, Ulrich Hecht
<ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Adds CAN controller nodes for r8a77995.
>
> Based on a patch for r8a7796 by Chris Paterson.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply
* Re: [PATCH 3/7] arm64: dts: r8a77995: Add CAN external clock support
From: Geert Uytterhoeven @ 2017-11-22 13:11 UTC (permalink / raw)
  To: Ulrich Hecht
  Cc: Linux-Renesas, linux-can-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Wolfram Sang,
	Simon Horman, Magnus Damm, Chris Paterson,
	Ramesh Shanmugasundaram
In-Reply-To: <1510915289-15059-4-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

On Fri, Nov 17, 2017 at 11:41 AM, Ulrich Hecht
<ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Adds external CAN clock node for r8a77995. This clock can be used as
> fCAN clock of CAN and CAN FD controller.
>
> Based on a patch for r8a7796 by Chris Paterson.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

^ permalink raw reply
* [PATCH] can: flexcan: Update IRQ Err Passive information
From: Marc Kleine-Budde @ 2017-11-22 12:53 UTC (permalink / raw)
  To: linux-can; +Cc: Marc Kleine-Budde

The flexcan IP cores used on MX25 and MX35 do not generate Error Passive
IRQs. Update the IP core overview table in the driver accordingly.

Suggested-by: ZHU Yi (ST-FIR/ENG1-Zhu) <Yi.Zhu5@cn.bosch.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 drivers/net/can/flexcan.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index a13a4896a8bd..eefddae2e99a 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -184,9 +184,9 @@
  * Below is some version info we got:
  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
  *                                Filter? connected?  Passive detection  ception in MB
- *   MX25  FlexCAN2  03.00.00.00     no        no         ?       no        no
+ *   MX25  FlexCAN2  03.00.00.00     no        no        no       no        no
  *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
- *   MX35  FlexCAN2  03.00.00.00     no        no         ?       no        no
+ *   MX35  FlexCAN2  03.00.00.00     no        no        no       no        no
  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
  *   VF610 FlexCAN3  ?               no       yes         ?      yes       yes?
-- 
2.15.0


^ permalink raw reply related
* Re: [PATCH v2 2/2] can: flexcan: adding platform specific details for LS1021A
From: Marc Kleine-Budde @ 2017-11-22 11:59 UTC (permalink / raw)
  To: ZHU Yi (ST-FIR/ENG1-Zhu), Pankaj Bansal, Wolfgang Grandegger,
	linux-can@vger.kernel.org
  Cc: Varun Sethi, Poonam Aggrwal, Stefan Agner
In-Reply-To: <3e201945af364c5a8a92dd6a931f4448@SGPMBX1017.APAC.bosch.com>


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On 11/22/2017 03:56 AM, ZHU Yi (ST-FIR/ENG1-Zhu) wrote:
>>> I'm afraid so far no known flexcan core supports it.
>>
>> Should we update the table and add a "IRQ Err Passive" no for all
>> cores?
> By look into the reference manual of MX25[1], MX35[2] and VF610[3],
> it turns out that none of them support the error passive interrupt.
> So we should update the "IRQ Err Passive" to no for all cores.

I'll create a patch.

> Interestingly, seems the new RM of MX25 (Rev.2) and MX35 (Rev.3)
> states that both core have the [TR]WRN_INT connected, so I guess the
> no in that column were added for the legacy core.

What do you mean by connected exactly?

As fas as I know these IP cores have these interrupts lines, but they
are not properly wired to the IRQ line that leaves the IP core. To quote
Shawn Guo from the discussion back in 2012:

>> From what I can tell, i.MX35, i.MX51 and i.MX53 use the same version,
>> so they should all have the bug.  And for i.MX6Q, since it uses a newer
>> version even than i.MX28, I would believe it's affected by the bug.
>> But I'm copying Dong who should have better knowledge about this to
>> confirm.

Further Dong Aisheng says:

>> Our IC owner double checked the MX35 and MX53 IP and found the
>> RX_WARN & TX_WARN Interrupt source actually are not connected to
>> ARM. That means flexcan will not trigger interrupt to ARM core even
>> RX_WARN or TX_WARN Happens. This may be the root cause that why you
>> cannot see RX_WARN interrupt if not enable bus error interrupt on
>> mx35. He also checked that mx6q has the rx/tx warning interrupt
>> connected to arm. So we guess mx6q does not have this issue. 
>> Anyway, we can test to confirm.

> However, as the driver also needs to work with the legacy core, and
> they share the same devtype_data as p1010, so I think we should leave
> it as it is.

>>>  * Below is some version info we got:
>>>  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
>>>  *                                Filter? connected?  Passive detection  ception in MB
>>>  *   MX25  FlexCAN2  03.00.00.00     no        no         ?       no        no
>>>  *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
>>>  *   MX35  FlexCAN2  03.00.00.00     no        no         ?       no        no
>>>  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
>>>  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
>>>  *   VF610 FlexCAN3  ?               no       yes         ?      yes       yes?
>>
>> And does it make sense to add "FLEXCAN_QUIRK_BROKEN_PERR_STATE" to the
>> vf610, too?

> I think vf610 will need this quirk to report correct state transitions.
> The reason last time we do not touch this is because neither Wolfgang
> nor I had access to vf610, so we can only test with MX28, MX53 and MX6.
> We thought someone will speak out if they meet problems with this core,
> and then they can help to fix and test it.

Cc'ed Stefan Agner - maybe he has access to this SoC.

> @Marc, @Wolfgang,
> What do you think? Or shall we fix first and then wait?

Let's wait if Stefan can test, otherwise just fix.

> @Pankaj, as you are currently working on patch this driver, is it
> possible that you can help to create patch for the table and/or the
> PERR_STATE quirk fix for vf610 in case required? Thanks!
Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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^ permalink raw reply
* RE: [PATCH v2 2/2] can: flexcan: adding platform specific details for LS1021A
From: Pankaj Bansal @ 2017-11-22  6:27 UTC (permalink / raw)
  To: ZHU Yi (ST-FIR/ENG1-Zhu), Marc Kleine-Budde, Wolfgang Grandegger,
	linux-can@vger.kernel.org
  Cc: Varun Sethi, Poonam Aggrwal
In-Reply-To: <3e201945af364c5a8a92dd6a931f4448@SGPMBX1017.APAC.bosch.com>

Hi ZHU Yi,


> From: ZHU Yi (ST-FIR/ENG1-Zhu) [mailto:Yi.Zhu5@cn.bosch.com]
> Sent: Wednesday, November 22, 2017 8:27 AM
> > [...]
> @Pankaj, as you are currently working on patch this driver, is it possible that
> you can help to create patch for the table and/or the PERR_STATE quirk fix
> for vf610 in case required? Thanks!
> 

I am afraid I also do not have access to vf610. I have access to p1010.

Regards,
Pankaj Bansal


^ permalink raw reply
* RE: [PATCH v2 2/2] can: flexcan: adding platform specific details for LS1021A
From: ZHU Yi (ST-FIR/ENG1-Zhu) @ 2017-11-22  2:56 UTC (permalink / raw)
  To: Marc Kleine-Budde, Pankaj Bansal, Wolfgang Grandegger,
	linux-can@vger.kernel.org
  Cc: Varun Sethi, Poonam Aggrwal, Bhupesh Sharma
In-Reply-To: <be8f51ff-8775-fe03-d299-2dc1f963ebcc@pengutronix.de>

Hello Marc,

>From: Marc Kleine-Budde [mailto:mkl@pengutronix.de]
>Sent: Tuesday, November 21, 2017 8:44 PM
>
> [...]
>> I'm afraid so far no known flexcan core supports it.
>
>Should we update the table and add a "IRQ Err Passive" no for all cores?
By look into the reference manual of MX25[1], MX35[2] and VF610[3],
it turns out that none of them support the error passive interrupt.
So we should update the "IRQ Err Passive" to no for all cores.

Interestingly, seems the new RM of MX25 (Rev.2) and MX35 (Rev.3)
states that both core have the [TR]WRN_INT connected, so I guess the
no in that column were added for the legacy core. However, as the
driver also needs to work with the legacy core, and they share the
same devtype_data as p1010, so I think we should leave it as it is.

>
>>  * Below is some version info we got:
>>  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
>>  *                                Filter? connected?  Passive detection  ception in MB
>>  *   MX25  FlexCAN2  03.00.00.00     no        no         ?       no        no
>>  *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
>>  *   MX35  FlexCAN2  03.00.00.00     no        no         ?       no        no
>>  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
>>  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
>>  *   VF610 FlexCAN3  ?               no       yes         ?      yes       yes?
>
>And does it make sense to add "FLEXCAN_QUIRK_BROKEN_PERR_STATE" to the
>vf610, too?
I think vf610 will need this quirk to report correct state transitions.
The reason last time we do not touch this is because neither Wolfgang
nor I had access to vf610, so we can only test with MX28, MX53 and MX6.
We thought someone will speak out if they meet problems with this core,
and then they can help to fix and test it.

@Marc, @Wolfgang,
What do you think? Or shall we fix first and then wait?

@Pankaj, as you are currently working on patch this driver, is it
possible that you can help to create patch for the table and/or the
PERR_STATE quirk fix for vf610 in case required? Thanks!

Best regards
Yi

[1] https://www.nxp.com/docs/en/reference-manual/IMX25RM.pdf
[2] https://www.nxp.com/docs/en/reference-manual/IMX35RM.pdf
[3] https://www.nxp.com/docs/en/reference-manual/VFXXXRM.pdf

^ permalink raw reply
* Re: [PATCH 0/3] Fixes for kvaser_usb driver
From: Marc Kleine-Budde @ 2017-11-21 13:14 UTC (permalink / raw)
  To: Jimmy Assarsson, linux-can
In-Reply-To: <20171121072228.7570-1-jimmyassarsson@gmail.com>


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On 11/21/2017 08:22 AM, Jimmy Assarsson wrote:
> The first patch fix two missing free calls in error paths. The second patch
> fix a bad comparison between signed and unsigned integer, causing undesired
> behaviour. The third patch will ratelimit error prinouts, if incomplete USB
> messages are received. My kernel log got flooded with these error messages,
> when I encountered the bug described in the previous patch.

Applied to can.

Tnx,
Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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