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Mon, 25 Mar 2024 06:08:48 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42P68mwW015080 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Mar 2024 06:08:48 GMT Received: from [10.216.57.55] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 24 Mar 2024 23:08:42 -0700 Message-ID: <008d574f-9c9e-48c6-b64e-89fb469cbde4@quicinc.com> Date: Mon, 25 Mar 2024 11:38:42 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 RESEND 6/6] arm64: dts: qcom: sm8650: Add video and camera clock controllers Content-Language: en-US To: Dmitry Baryshkov CC: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Vladimir Zapolskiy , , , , , Taniya Das , Satya Priya Kakitapalli , Ajit Pandey , Imran Shaik References: <20240321092529.13362-1-quic_jkona@quicinc.com> <20240321092529.13362-7-quic_jkona@quicinc.com> From: Jagadeesh Kona In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: MvdibvDTsYlwh3efMOse4HNen3L1Cein X-Proofpoint-ORIG-GUID: MvdibvDTsYlwh3efMOse4HNen3L1Cein X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-25_03,2024-03-21_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 phishscore=0 mlxscore=0 clxscore=1015 mlxlogscore=999 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403250031 On 3/21/2024 6:43 PM, Dmitry Baryshkov wrote: > On Thu, 21 Mar 2024 at 11:27, Jagadeesh Kona wrote: >> >> Add device nodes for video and camera clock controllers on Qualcomm >> SM8650 platform. >> >> Signed-off-by: Jagadeesh Kona >> --- >> arch/arm64/boot/dts/qcom/sm8650.dtsi | 28 ++++++++++++++++++++++++++++ >> 1 file changed, 28 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> index 32c0a7b9aded..d862aa6be824 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> @@ -4,6 +4,8 @@ >> */ >> >> #include >> +#include >> +#include >> #include >> #include >> #include >> @@ -3110,6 +3112,32 @@ opp-202000000 { >> }; >> }; >> >> + videocc: clock-controller@aaf0000 { >> + compatible = "qcom,sm8650-videocc"; >> + reg = <0 0x0aaf0000 0 0x10000>; >> + clocks = <&bi_tcxo_div2>, >> + <&gcc GCC_VIDEO_AHB_CLK>; >> + power-domains = <&rpmhpd RPMHPD_MMCX>; >> + required-opps = <&rpmhpd_opp_low_svs>; > > The required-opps should no longer be necessary. > Sure, will check and remove this if not required. Thanks, Jagadeesh >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> + camcc: clock-controller@ade0000 { >> + compatible = "qcom,sm8650-camcc"; >> + reg = <0 0x0ade0000 0 0x20000>; >> + clocks = <&gcc GCC_CAMERA_AHB_CLK>, >> + <&bi_tcxo_div2>, >> + <&bi_tcxo_ao_div2>, >> + <&sleep_clk>; >> + power-domains = <&rpmhpd RPMHPD_MMCX>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> mdss: display-subsystem@ae00000 { >> compatible = "qcom,sm8650-mdss"; >> reg = <0 0x0ae00000 0 0x1000>; >> -- >> 2.43.0 >> >> > >