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PLLs are required by most peripheral to operate. >> Say Y if you want A9 PLL clock controller to work. >> >> +config COMMON_CLK_A9_PERIPHERALS >> + tristate "Amlogic A9 SoC peripherals clock controller support" >> + depends on ARM64 > depends on ARM64 || COMPILE_TEST Ok, I will add COMPILE_TEST in the next version. >> + default ARCH_MESON >> + select COMMON_CLK_MESON_REGMAP >> + select COMMON_CLK_MESON_CLKC_UTILS >> + select COMMON_CLK_MESON_DUALDIV >> + select COMMON_CLK_MESON_VID_PLL_DIV >> + imply COMMON_CLK_SCMI >> + imply COMMON_CLK_A9_PLL >> + help >> + Support for the peripherals clock controller on Amlogic A311Y3 based >> + device, AKA A9. Peripherals are required by most peripheral to operate. >> + Say Y if you want A9 peripherals clock controller to work. >> + >> config COMMON_CLK_C3_PLL >> tristate "Amlogic C3 PLL clock controller" >> depends on ARM64 >> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile >> index 77636033061f..2b5b67b14efc 100644 >> --- a/drivers/clk/meson/Makefile >> +++ b/drivers/clk/meson/Makefile >> @@ -20,6 +20,7 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o >> obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o >> obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o >> obj-$(CONFIG_COMMON_CLK_A9_PLL) += a9-pll.o >> +obj-$(CONFIG_COMMON_CLK_A9_PERIPHERALS) += a9-peripherals.o >> obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o >> obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o >> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o >> diff --git a/drivers/clk/meson/a9-peripherals.c b/drivers/clk/meson/a9-peripherals.c >> new file mode 100644 >> index 000000000000..338a91c473ea >> --- /dev/null >> +++ b/drivers/clk/meson/a9-peripherals.c >> @@ -0,0 +1,2317 @@ >> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) >> +/* >> + * Copyright (C) 2026 Amlogic, Inc. All rights reserved >> + */ >> + >> +#include >> +#include >> +#include >> +#include "clk-regmap.h" >> +#include "clk-dualdiv.h" >> +#include "vid-pll-div.h" >> +#include "meson-clkc-utils.h" > Sort the headers. Ok, I will place them in order. After updated: #include #include #include #include "clk-regmap.h" #include "clk-dualdiv.h" #include "meson-clkc-utils.h" #include "vid-pll-div.h" [......] >> +static const struct clk_parent_data a9_nna_parents[] = { >> + { .fw_name = "xtal", }, >> + { .fw_name = "fdiv2p5", }, >> + { .fw_name = "fdiv4", }, >> + { .fw_name = "fdiv3", }, >> + { .fw_name = "fdiv5", }, >> + { .fw_name = "fdiv2", }, >> + { .fw_name = "gp2", }, >> + { .fw_name = "hifi", } > hifi isn't in the dt bindings. Should this be hifi0 and/or hifi1? It should be hifi0，I will fix it in the next version. Thank you for pointing it out. [......] >> + >> +static struct clk_regmap a9_sc = { >> + .data = &(struct clk_regmap_div_data) { >> + .offset = SC_CLK_CTRL, >> + .shift = 16, >> + .width = 4, >> + }, >> + .hw.init = &(struct clk_init_data) { >> + .name = "sc", >> + .ops = &clk_regmap_divider_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &a9_sc_pre.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, > You can use CLK_HW_INIT_HWS() here. > > Brian Ok, I will use CLK_HW_INIT_HWS instead, and the same below. Best regards, Jian