* [PATCH v11 00/38] ep93xx device tree conversion
@ 2024-07-15 8:38 Nikita Shubin via B4 Relay
2024-07-15 8:38 ` [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx Nikita Shubin via B4 Relay
` (2 more replies)
0 siblings, 3 replies; 12+ messages in thread
From: Nikita Shubin via B4 Relay @ 2024-07-15 8:38 UTC (permalink / raw)
To: Arnd Bergmann, Hartley Sweeten, Alexander Sverdlin, Russell King,
Lukasz Majewski, Linus Walleij, Bartosz Golaszewski,
Andy Shevchenko, Michael Turquette, Stephen Boyd,
Sebastian Reichel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Nikita Shubin, Vinod Koul, Wim Van Sebroeck, Guenter Roeck,
Thierry Reding, Uwe Kleine-König, Mark Brown,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Damien Le Moal, Sergey Shtylyov, Dmitry Torokhov, Liam Girdwood,
Jaroslav Kysela, Takashi Iwai, Ralf Baechle, Wu, Aaron, Lee Jones,
Olof Johansson, Niklas Cassel
Cc: linux-arm-kernel, linux-kernel, linux-gpio, linux-clk, linux-pm,
devicetree, dmaengine, linux-watchdog, linux-pwm, linux-spi,
netdev, linux-mtd, linux-ide, linux-input, linux-sound,
Bartosz Golaszewski, Krzysztof Kozlowski, Andy Shevchenko,
Andy Shevchenko, Andrew Lunn
The goal is to recieve ACKs for all patches in series to merge it via Arnd branch.
It was decided from the very beginning of these series, mostly because
it's a full conversion of platform code to DT and it seemed not
convenient to maintain compatibility with both platform and DT.
Following patches require attention from Stephen Boyd or clk subsystem:
- clk: ep93xx: add DT support for Cirrus EP93xx
It is purely possible to add something like devm_clk_hw_register_fixed_rate_parent_data()
for devm managed version clk_hw_register_fixed_rate_parent_data(), still i would like to
leave for the time after this series if it's all possible.
Couse may be it's better to add something like
devm_clk_hw_register_fixed_rate_index() like it's done for
devm_clk_hw_register_fixed_factor_index().
Changelog for this patch:
- added devm_ep93xx_clk_hw_register_fixed_rate_parent_data() for
devm_ version of clk_hw_register_fixed_rate_parent_data()
- s/devm_clk_hw_register_fixed_rate()/devm_ep93xx_clk_hw_register_fixed_rate_parent_data()/
- replaced all devm_clk_hw_register_fixed_factor() to
devm_clk_hw_register_fixed_factor_parent_hw() or
devm_clk_hw_register_fixed_factor_index()
- s/devm_clk_hw_register_gate()/devm_clk_hw_register_gate_parent_data()
Stephen - it think that's you was aiming for - to get rid of all
functions that are using const char* parent_name directly instead of
clk_hw or clk_parent_data.
Patches should be formated with '--histogram'
---
Changes in v11:
- clk: ep93xx: add DT support for Cirrus EP93xx
- added devm_ep93xx_clk_hw_register_fixed_rate_parent_data() for
devm_ version of clk_hw_register_fixed_rate_parent_data()
- s/devm_clk_hw_register_fixed_rate()/devm_ep93xx_clk_hw_register_fixed_rate_parent_data()/
- replaced all devm_clk_hw_register_fixed_factor() to
devm_clk_hw_register_fixed_factor_parent_hw() or
devm_clk_hw_register_fixed_factor_index()
- s/devm_clk_hw_register_gate()/devm_clk_hw_register_gate_parent_data()
- Link to v10: https://lore.kernel.org/r/20240617-ep93xx-v10-0-662e640ed811@maquefel.me
Changes in v10:
Reordered SoB tags to make sure they appear before Rb and Acked tags.
dmaengine: cirrus: Convert to DT for Cirrus EP93xx
- s/dma/dmaengine/ title
dmaengine: cirrus: remove platform code
- s/dma/dmaengine/ title
soc: Add SoC driver for Cirrus ep93xx:
- added __init for ep93xx_adev_alloc(), ep93xx_controller_register()
- added static, __initconst for pinctrl_names[]
- clk revision for SPI is now resolved here through differently named
clk device
- more verbose Kconfig description
clk: ep93xx: add DT support for Cirrus EP93xx:
- dropped includes
- dropped ep93xx_soc_table[]
- add different named clk and dropped involved includes
- moved pll's and fclk, hclk, pclk init to separate function
- fixed ep93xx_clk_ids[] explicit lines
- Link to v9: https://lore.kernel.org/r/20240326-ep93xx-v9-0-156e2ae5dfc8@maquefel.me
- Link to v2 clk: https://lore.kernel.org/r/20240408-ep93xx-clk-v2-1-adcd68c13753@maquefel.me
Changes in v9:
ARM: dts: add Cirrus EP93XX SoC .dtsi
- added #interrupt-cells to gpio nodes with interrupts-controller
- fixed EOF
ARM: dts: ep93xx: Add EDB9302 DT
- Alexander Sverdlin: fixed bug in Device Tree resulting in CS4271 not working
input: keypad: ep93xx: add DT support for Cirrus EP93xx
- fixed identation and type
- Link to v8: https://lore.kernel.org/r/20240226-ep93xx-v8-0-3136dca7238f@maquefel.me/
Changes in v8:
soc: Add SoC driver for Cirrus ep93xx
- fixed freeing adev instead of rdev
- use __free() and no_free_ptr() for rdev allocation
- s/of_device_get_match_data()/device_get_match_data()/
ata: pata_ep93xx: add device tree support
- more appropriate usage of dev_err_probe()
pinctrl: add a Cirrus ep93xx SoC pin controller
- 8 per row in ide_9312_pins
mtd: rawnand: add support for ts72xx
- fwnode_handle_put() for fwnode in ts72xx_nand_remove()
- Link to v7: https://lore.kernel.org/r/20240118-ep93xx-v7-0-d953846ae771@maquefel.me
Changes in v7:
mtd: rawnand: add support for ts72xx
- fixed KConfig description
ARM: ep93xx: Add terminator to gpiod_lookup_table
- + Reported-by, Fixes
ARM: ep93xx: add regmap aux_dev
- + trailing comma
- - #include <linux/spinlock.h>
clk: ep93xx: add DT support for Cirrus EP93xx
- dropped unused defines
- return from default in ep93xx_mux_get_parent()
- use guard() in ep93xx_mux_set_parent_lock()
- <math.h> header for abs_diff()
- fixed comments
pinctrl: add a Cirrus ep93xx SoC pin controller
- dropped comments for DEVCFG defines
- <linux/array_size.h> for ARRAY_SIZE()
- + default in ep93xx_get_group_name()
- correct cast for id->driver_data
- s/device_set_of_node_from_dev()/device_set_node()/
power: reset: Add a driver for the ep93xx reset
- Add <linux/container_of.h>, <linux/errno.h>, <linux/slab.h>
- Add <linux/module.h>, <linux/mod_devicetable.h>
- Remove <platform_device.h>
spi: ep93xx: add DT support for Cirrus EP93xx
- Replace with ret = dev_err_probe(...);
ata: pata_ep93xx: add device tree support
- fixed wrong rebase with some partes leaked in "ata: pata_ep93xx: remove legacy pinctrl use"
- fix dma_request_chan() error processing
dma: cirrus: Convert to DT for Cirrus EP93xx
- fixed commit message (dropped explicit "only")
- fixed clk_get() processing to defer probe and log spamming
- refactor ep93xx_m2p_dma_filter()
- dropped blank line in ep93xx_m2p_dma_of_xlate()
- refactor ep93xx_m2m_dma_of_xlate()
dma: cirrus: remove platform code
- s/dma/DMA/ in commit message
soc: Add SoC driver for Cirrus ep93xx
- add period
- use cleanup and guard() for spinlocking
- correct cast for device_get_match_data()
- dropped dev_info() with SoC revision - i can't find it anywhere since 2.6 :/,
don't know why i was so sured that ep93xx always printed that
ata: pata_ep93xx: remove legacy pinctrl use
- made error handling in DMA as Uwe suggested
- Link to v6: https://lore.kernel.org/r/20231212-ep93xx-v6-0-c307b8ac9aa8@maquefel.me
Changes in v6:
- clk: ep93xx: add DT support for Cirrus EP93xx
- s/spin_lock_irqsave()/guard()/
- refactor index check in ep93xx_mux_set_parent_lock() to something more readable
- use in_range in ep93xx_mux_set_parent_lock()/ep93xx_ddiv_set_rate()
- use GENMASK() in ep93xx_ddiv_recalc_rate()
- comment reserved bit in ep93xx_ddiv_set_rate()
- move out from loop ClkDiv value assigment
- some style fixes
Andy, i was i asked to set index of XTALI explicitly, i am not setting ddiv_pdata
there becouse only XTALI is jnown in advance, and i think setting them in one place is more convenient.
- pinctrl: add a Cirrus ep93xx SoC pin controller
- drop OF from Kconfig
- droped linux/of.h include
- add space to */ where it is applicable
- add coma in multiline assigment
- "return NULL" as default case in ep93xx_get_group_name()
- fixed casting id->driver_data
- use device_set_of_node_from_dev()
- use dev_err_probe()
- power: reset: Add a driver for the ep93xx reset
- drop linux/of.h include
- soc: Add SoC driver for Cirrus ep93xx
- s/GPL-2.0/GPL-2.0-only/
- drop linux/kernel.h include
- + blank line before linux/soc/cirrus/ep93xx.h
- + blank line after ep93xx_get_soc_rev()
- + coma for pinctrl_names
- valid casting to int for of_device_get_match_data() return value
- mtd: rawnand: add support for ts72xx
- return as part of switch case
- s/iowrite8/iowrite8_rep/
- net: cirrus: add DT support for Cirrus EP93xx
- fix header sorting
- dma: cirrus: Convert to DT for Cirrus EP93xx
- use devm_clk_get
- use is_slave_direction
Changes in v5:
- gpio: ep93xx: split device in multiple
- ordered headers
- use irqd_to_hwirq()
- s/platform_get_irq()/platform_get_irq_optional()/
- [PATCH v4 02/42] ARM: ep93xx: add swlocked prototypes
- replaced with ARM: ep93xx: add regmap aux_dev
- [PATCH v4 03/42] dt-bindings: clock: Add Cirrus EP93xx
- fixed identation
- removed EP93XX_CLK_END
- and dropped it
- clock bindings moved to syscon with renaming to cirrus,ep9301-syscon.h
- clk: ep93xx: add DT support for Cirrus EP93xx
- convert to auxiliary and use parent device tree node
- moved all clocks except XTALI here
- used devm version everywhere and *_parent_hw() instead of passing name where it's possible
- unfortunately devm_clk_hw_register_fixed_rate doesn't have a parent index version
- [PATCH v4 05/42] dt-bindings: pinctrl: Add Cirrus EP93xx
- "unevaluatedProperties: false" for pins
- returned "additionalProperties: false" where it was
- and dropped it
- pinctrl: add a Cirrus ep93xx SoC pin controller
- sorted includes
- convert to auxiliary and use parent device tree node
- power: reset: Add a driver for the ep93xx reset
- convert to auxiliary device
- dt-bindings: soc: Add Cirrus EP93xx
- dropped all ref to reboot, clk, pinctrl subnodes
- added pins, as it's now used for pinctrl
- added #clock-cells, as it's now used for clk
- dt-bindings: pwm: Add Cirrus EP93xx
- $ref to pwm.yaml
- fixed 'pwm-cells'
- s/additionalProperties/unevaluatedProperties/
- soc: Add SoC driver for Cirrus ep93xx
- removed clocks, they are moved to clk auxiliary driver, as we dropped the clk dt node
- removed all swlocked exported functions
- dropped static spinlock
- added instantiating auxiliary reboot, clk, pinctrl
- dt-bindings: spi: Add Cirrus EP93xx
- Document DMA support
- spi: ep93xx: add DT support for Cirrus EP93xx
- dropped CONFIG_OF and SPI/DMA platform data entirely
- s/master/host/
- reworked DMA setup so we can use probe defer
- dt-bindings: dma: Add Cirrus EP93xx
- dropped bindings header (moved ports description to YAML)
- changed '#dma-cells' to 2, we use port, direction in cells so we can drop platform code completely
- dma: cirrus: add DT support for Cirrus EP93xx
- dropped platform probing completely
- dropped struct ep93xx_dma_data replaced with internal struct ep93xx_dma_chan_cfg with port/direction
- added xlate functions for m2m/m2p
- we require filters to set dma_cfg before hw_setup
- dt-bindings: ata: Add Cirrus EP93xx
- Document DMA support
- ata: pata_ep93xx: add device tree support
- drop DMA platform header with data
- use DMA OF so we can defer probing until DMA is up
- ARM: dts: add Cirrus EP93XX SoC .dtsi
- ARM: dts: ep93xx: add ts7250 board
- ARM: dts: ep93xx: Add EDB9302 DT
- replaced "eclk: clock-controller" to syscon reference
- replaced "pinctrl: pinctrl" to syscon reference
- gpios are now "enabled" by default
- reworked i2s node
- change all dma nodes and refs
- new additions to I2S
- Document DMA
- Document Audio Port usage
- drop legacy DMA support
- Link to v4: https://lore.kernel.org/r/20230915-ep93xx-v4-0-a1d779dcec10@maquefel.me
Changes in v4:
- gpio: ep93xx: split device in multiple
- s/generic_handle_irq/generic_handle_domain_irq/
- s/int offset/irq_hw_number_t offset/ though now it looks a bit odd to me
- drop i = 0
- drop 'error'
- use dev_err_probe withour printing devname once again
dt-bindings: clock: Add Cirrus EP93xx
- renamed cirrus,ep93xx-clock.h -> cirrus,ep9301-clk.h
clk: ep93xx: add DT support for Cirrus EP93xx
- drop unused includes
- use .name only for xtali, pll1, pll2 parents
- convert // to /*
- pass clk_parent_data instead of char* clock name
dt-bindings: pinctrl: Add Cirrus EP93xx
- s/additionalProperties/unevaluatedProperties/
dt-bindings: soc: Add Cirrus EP93xx
- move syscon to soc directory
- add vendor prefix
- make reboot same style as pinctrl, clk
- use absolute path for ref
- expand example
soc: Add SoC driver for Cirrus ep93xx
- s/0xf0000000/GENMASK(31, 28)/
- s/ret/ep93xx_chip_revision(map)/
- drop symbol exports
- convert to platform driver
dt-bindings: rtc: Add Cirrus EP93xx
- allOf: with $ref to rtc.yaml
- s/additionalProperties/unevaluatedProperties/
dt-bindings: watchdog: Add Cirrus EP93x
- drop description
- reword
power: reset: Add a driver for the ep93xx reset
- lets use 'GPL-2.0+' instead of '(GPL-2.0)'
- s/of_device/of/
- drop mdelay with warning
- return 0 at the end
net: cirrus: add DT support for Cirrus EP93xx
- fix leaking np
mtd: nand: add support for ts72xx
- +bits.h
- drop comment
- ok to fwnode_get_next_child_node
- use goto to put handle and nand and report error
ARM: dts: add Cirrus EP93XX SoC .dtsi
- add simple-bus for ebi, as we don't require to setup anything
- add arm,pl011 compatible to uart nodes
- drop i2c-gpio, as it's isn't used anywhere
ARM: dts: ep93xx: add ts7250 board
- generic node name for temperature-sensor
- drop i2c
- move nand, rtc, watchdog to ebi node
- Link to v3: https://lore.kernel.org/r/20230605-ep93xx-v3-0-3d63a5f1103e@maquefel.me
---
Alexander Sverdlin (3):
ASoC: ep93xx: Drop legacy DMA support
ARM: dts: ep93xx: Add EDB9302 DT
ASoC: cirrus: edb93xx: Delete driver
Nikita Shubin (35):
gpio: ep93xx: split device in multiple
ARM: ep93xx: add regmap aux_dev
clk: ep93xx: add DT support for Cirrus EP93xx
pinctrl: add a Cirrus ep93xx SoC pin controller
power: reset: Add a driver for the ep93xx reset
dt-bindings: soc: Add Cirrus EP93xx
soc: Add SoC driver for Cirrus ep93xx
dt-bindings: dma: Add Cirrus EP93xx
dmaengine: cirrus: Convert to DT for Cirrus EP93xx
dt-bindings: watchdog: Add Cirrus EP93x
watchdog: ep93xx: add DT support for Cirrus EP93xx
dt-bindings: pwm: Add Cirrus EP93xx
pwm: ep93xx: add DT support for Cirrus EP93xx
dt-bindings: spi: Add Cirrus EP93xx
spi: ep93xx: add DT support for Cirrus EP93xx
dt-bindings: net: Add Cirrus EP93xx
net: cirrus: add DT support for Cirrus EP93xx
dt-bindings: mtd: Add ts7200 nand-controller
mtd: rawnand: add support for ts72xx
dt-bindings: ata: Add Cirrus EP93xx
ata: pata_ep93xx: add device tree support
dt-bindings: input: Add Cirrus EP93xx keypad
input: keypad: ep93xx: add DT support for Cirrus EP93xx
wdt: ts72xx: add DT support for ts72xx
gpio: ep93xx: add DT support for gpio-ep93xx
ASoC: dt-bindings: ep93xx: Document DMA support
ASoC: dt-bindings: ep93xx: Document Audio Port support
ARM: dts: add Cirrus EP93XX SoC .dtsi
ARM: dts: ep93xx: add ts7250 board
ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms
pwm: ep93xx: drop legacy pinctrl
ata: pata_ep93xx: remove legacy pinctrl use
ARM: ep93xx: delete all boardfiles
ARM: ep93xx: soc: drop defines
dmaengine: cirrus: remove platform code
.../bindings/arm/cirrus/cirrus,ep9301.yaml | 38 +
.../bindings/ata/cirrus,ep9312-pata.yaml | 42 +
.../bindings/dma/cirrus,ep9301-dma-m2m.yaml | 84 ++
.../bindings/dma/cirrus,ep9301-dma-m2p.yaml | 144 ++
.../bindings/input/cirrus,ep9307-keypad.yaml | 87 ++
.../devicetree/bindings/mtd/technologic,nand.yaml | 45 +
.../devicetree/bindings/net/cirrus,ep9301-eth.yaml | 59 +
.../devicetree/bindings/pwm/cirrus,ep9301-pwm.yaml | 53 +
.../bindings/soc/cirrus/cirrus,ep9301-syscon.yaml | 94 ++
.../bindings/sound/cirrus,ep9301-i2s.yaml | 16 +
.../devicetree/bindings/spi/cirrus,ep9301-spi.yaml | 70 +
.../bindings/watchdog/cirrus,ep9301-wdt.yaml | 42 +
arch/arm/Makefile | 1 -
arch/arm/boot/dts/cirrus/Makefile | 4 +
arch/arm/boot/dts/cirrus/ep93xx-bk3.dts | 125 ++
arch/arm/boot/dts/cirrus/ep93xx-edb9302.dts | 181 +++
arch/arm/boot/dts/cirrus/ep93xx-ts7250.dts | 145 ++
arch/arm/boot/dts/cirrus/ep93xx.dtsi | 444 ++++++
arch/arm/mach-ep93xx/Kconfig | 20 +-
arch/arm/mach-ep93xx/Makefile | 11 -
arch/arm/mach-ep93xx/clock.c | 733 ----------
arch/arm/mach-ep93xx/core.c | 1018 --------------
arch/arm/mach-ep93xx/dma.c | 114 --
arch/arm/mach-ep93xx/edb93xx.c | 368 -----
arch/arm/mach-ep93xx/ep93xx-regs.h | 38 -
arch/arm/mach-ep93xx/gpio-ep93xx.h | 111 --
arch/arm/mach-ep93xx/hardware.h | 25 -
arch/arm/mach-ep93xx/irqs.h | 76 --
arch/arm/mach-ep93xx/platform.h | 42 -
arch/arm/mach-ep93xx/soc.h | 212 ---
arch/arm/mach-ep93xx/timer-ep93xx.c | 143 --
arch/arm/mach-ep93xx/ts72xx.c | 422 ------
arch/arm/mach-ep93xx/ts72xx.h | 94 --
arch/arm/mach-ep93xx/vision_ep9307.c | 321 -----
drivers/ata/pata_ep93xx.c | 107 +-
drivers/clk/Kconfig | 8 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-ep93xx.c | 846 ++++++++++++
drivers/dma/ep93xx_dma.c | 287 +++-
drivers/gpio/gpio-ep93xx.c | 345 ++---
drivers/input/keyboard/ep93xx_keypad.c | 74 +-
drivers/mtd/nand/raw/Kconfig | 6 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/technologic-nand-controller.c | 222 +++
drivers/net/ethernet/cirrus/ep93xx_eth.c | 63 +-
drivers/pinctrl/Kconfig | 7 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-ep93xx.c | 1434 ++++++++++++++++++++
drivers/power/reset/Kconfig | 10 +
drivers/power/reset/Makefile | 1 +
drivers/power/reset/ep93xx-restart.c | 84 ++
drivers/pwm/pwm-ep93xx.c | 26 +-
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/cirrus/Kconfig | 17 +
drivers/soc/cirrus/Makefile | 2 +
drivers/soc/cirrus/soc-ep93xx.c | 252 ++++
drivers/spi/spi-ep93xx.c | 66 +-
drivers/watchdog/ep93xx_wdt.c | 8 +
drivers/watchdog/ts72xx_wdt.c | 8 +
include/dt-bindings/clock/cirrus,ep9301-syscon.h | 46 +
include/linux/platform_data/dma-ep93xx.h | 94 --
include/linux/platform_data/eth-ep93xx.h | 10 -
include/linux/platform_data/keypad-ep93xx.h | 32 -
include/linux/platform_data/spi-ep93xx.h | 15 -
include/linux/soc/cirrus/ep93xx.h | 47 +-
sound/soc/cirrus/Kconfig | 9 -
sound/soc/cirrus/Makefile | 4 -
sound/soc/cirrus/edb93xx.c | 116 --
sound/soc/cirrus/ep93xx-i2s.c | 19 -
sound/soc/cirrus/ep93xx-pcm.c | 19 +-
71 files changed, 5161 insertions(+), 4550 deletions(-)
---
base-commit: 0c3836482481200ead7b416ca80c68a29cfdaabd
change-id: 20230605-ep93xx-01c76317e2d2
Best regards,
--
Nikita Shubin <nikita.shubin@maquefel.me>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx
2024-07-15 8:38 [PATCH v11 00/38] ep93xx device tree conversion Nikita Shubin via B4 Relay
@ 2024-07-15 8:38 ` Nikita Shubin via B4 Relay
2024-08-02 7:07 ` Nikita Shubin
2024-08-28 20:44 ` Stephen Boyd
2024-07-15 8:38 ` [PATCH v11 06/38] dt-bindings: soc: Add " Nikita Shubin via B4 Relay
2024-07-15 12:12 ` [PATCH v11 00/38] ep93xx device tree conversion Rob Herring (Arm)
2 siblings, 2 replies; 12+ messages in thread
From: Nikita Shubin via B4 Relay @ 2024-07-15 8:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd; +Cc: linux-kernel, linux-clk
From: Nikita Shubin <nikita.shubin@maquefel.me>
Rewrite EP93xx clock driver located in arch/arm/mach-ep93xx/clock.c
trying to do everything the device tree way:
- provide clock acces via of
- drop clk_hw_register_clkdev
- drop init code and use module_auxiliary_driver
Co-developed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
---
drivers/clk/Kconfig | 8 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-ep93xx.c | 846 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 855 insertions(+)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 3e9099504fad..234b0a8b7650 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -218,6 +218,14 @@ config COMMON_CLK_EN7523
This driver provides the fixed clocks and gates present on Airoha
ARM silicon.
+config COMMON_CLK_EP93XX
+ bool "Clock driver for Cirrus Logic ep93xx SoC"
+ depends on ARCH_EP93XX || COMPILE_TEST
+ select MFD_SYSCON
+ select REGMAP
+ help
+ This driver supports the SoC clocks on the Cirrus Logic ep93xx.
+
config COMMON_CLK_FSL_FLEXSPI
tristate "Clock driver for FlexSPI on Layerscape SoCs"
depends on ARCH_LAYERSCAPE || COMPILE_TEST
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4abe16c8ccdf..19d599d706fe 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o
obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
+obj-$(CONFIG_COMMON_CLK_EP93XX) += clk-ep93xx.o
obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o
obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
diff --git a/drivers/clk/clk-ep93xx.c b/drivers/clk/clk-ep93xx.c
new file mode 100644
index 000000000000..bb1cf59a3d47
--- /dev/null
+++ b/drivers/clk/clk-ep93xx.c
@@ -0,0 +1,846 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Clock control for Cirrus EP93xx chips.
+ * Copyright (C) 2021 Nikita Shubin <nikita.shubin@maquefel.me>
+ *
+ * Based on a rewrite of arch/arm/mach-ep93xx/clock.c:
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ */
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
+
+#include <linux/bits.h>
+#include <linux/cleanup.h>
+#include <linux/clk-provider.h>
+#include <linux/math.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/spinlock.h>
+
+#include <linux/soc/cirrus/ep93xx.h>
+#include <dt-bindings/clock/cirrus,ep9301-syscon.h>
+
+#include <asm/div64.h>
+
+#define EP93XX_EXT_CLK_RATE 14745600
+#define EP93XX_EXT_RTC_RATE 32768
+
+#define EP93XX_SYSCON_POWER_STATE 0x00
+#define EP93XX_SYSCON_PWRCNT 0x04
+#define EP93XX_SYSCON_PWRCNT_UARTBAUD BIT(29)
+#define EP93XX_SYSCON_PWRCNT_USH_EN 28
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16
+#define EP93XX_SYSCON_CLKSET1 0x20
+#define EP93XX_SYSCON_CLKSET1_NBYP1 BIT(23)
+#define EP93XX_SYSCON_CLKSET2 0x24
+#define EP93XX_SYSCON_CLKSET2_NBYP2 BIT(19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN BIT(18)
+#define EP93XX_SYSCON_DEVCFG 0x80
+#define EP93XX_SYSCON_DEVCFG_U3EN 24
+#define EP93XX_SYSCON_DEVCFG_U2EN 20
+#define EP93XX_SYSCON_DEVCFG_U1EN 18
+#define EP93XX_SYSCON_VIDCLKDIV 0x84
+#define EP93XX_SYSCON_CLKDIV_ENABLE 15
+#define EP93XX_SYSCON_CLKDIV_ESEL BIT(14)
+#define EP93XX_SYSCON_CLKDIV_PSEL BIT(13)
+#define EP93XX_SYSCON_CLKDIV_MASK GENMASK(14, 13)
+#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
+#define EP93XX_SYSCON_I2SCLKDIV 0x8c
+#define EP93XX_SYSCON_I2SCLKDIV_SENA 31
+#define EP93XX_SYSCON_I2SCLKDIV_ORIDE BIT(29)
+#define EP93XX_SYSCON_I2SCLKDIV_SPOL BIT(19)
+#define EP93XX_SYSCON_KEYTCHCLKDIV 0x90
+#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31
+#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV 0
+#define EP93XX_SYSCON_CHIPID 0x94
+#define EP93XX_SYSCON_CHIPID_ID 0x9213
+
+static const char adc_divisors[] = { 16, 4 };
+static const char sclk_divisors[] = { 2, 4 };
+static const char lrclk_divisors[] = { 32, 64, 128 };
+
+struct ep93xx_clk {
+ struct clk_hw hw;
+ u16 idx;
+ u16 reg;
+ u32 mask;
+ u8 bit_idx;
+ u8 shift;
+ u8 width;
+ u8 num_div;
+ const char *div;
+};
+
+struct ep93xx_clk_priv {
+ spinlock_t lock;
+ struct ep93xx_regmap_adev *aux_dev;
+ struct device *dev;
+ void __iomem *base;
+ struct regmap *map;
+ struct clk_hw *fixed[21];
+ struct ep93xx_clk reg[];
+};
+
+static struct ep93xx_clk *ep93xx_clk_from(struct clk_hw *hw)
+{
+ return container_of(hw, struct ep93xx_clk, hw);
+}
+
+static struct ep93xx_clk_priv *ep93xx_priv_from(struct ep93xx_clk *clk)
+{
+ return container_of(clk, struct ep93xx_clk_priv, reg[clk->idx]);
+}
+
+static void ep93xx_clk_write(struct ep93xx_clk_priv *priv, unsigned int reg, unsigned int val)
+{
+ struct ep93xx_regmap_adev *aux = priv->aux_dev;
+
+ aux->write(aux->map, aux->lock, reg, val);
+}
+
+static int ep93xx_clk_is_enabled(struct clk_hw *hw)
+{
+ struct ep93xx_clk *clk = ep93xx_clk_from(hw);
+ struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
+ u32 val;
+
+ regmap_read(priv->map, clk->reg, &val);
+
+ return !!(val & BIT(clk->bit_idx));
+}
+
+static int ep93xx_clk_enable(struct clk_hw *hw)
+{
+ struct ep93xx_clk *clk = ep93xx_clk_from(hw);
+ struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
+ u32 val;
+
+ guard(spinlock_irqsave)(&priv->lock);
+
+ regmap_read(priv->map, clk->reg, &val);
+ val |= BIT(clk->bit_idx);
+
+ ep93xx_clk_write(priv, clk->reg, val);
+
+ return 0;
+}
+
+static void ep93xx_clk_disable(struct clk_hw *hw)
+{
+ struct ep93xx_clk *clk = ep93xx_clk_from(hw);
+ struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
+ u32 val;
+
+ guard(spinlock_irqsave)(&priv->lock);
+
+ regmap_read(priv->map, clk->reg, &val);
+ val &= ~BIT(clk->bit_idx);
+
+ ep93xx_clk_write(priv, clk->reg, val);
+}
+
+static const struct clk_ops clk_ep93xx_gate_ops = {
+ .enable = ep93xx_clk_enable,
+ .disable = ep93xx_clk_disable,
+ .is_enabled = ep93xx_clk_is_enabled,
+};
+
+static int ep93xx_clk_register_gate(struct ep93xx_clk *clk,
+ const char *name,
+ struct clk_parent_data *parent_data,
+ unsigned long flags,
+ unsigned int reg,
+ u8 bit_idx)
+{
+ struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
+ struct clk_init_data init = { };
+
+ init.name = name;
+ init.ops = &clk_ep93xx_gate_ops;
+ init.flags = flags;
+ init.parent_data = parent_data;
+ init.num_parents = 1;
+
+ clk->reg = reg;
+ clk->bit_idx = bit_idx;
+ clk->hw.init = &init;
+
+ return devm_clk_hw_register(priv->dev, &clk->hw);
+}
+
+static u8 ep93xx_mux_get_parent(struct clk_hw *hw)
+{
+ struct ep93xx_clk *clk = ep93xx_clk_from(hw);
+ struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
+ u32 val;
+
+ regmap_read(priv->map, clk->reg, &val);
+
+ val &= EP93XX_SYSCON_CLKDIV_MASK;
+
+ switch (val) {
+ case EP93XX_SYSCON_CLKDIV_ESEL:
+ return 1; /* PLL1 */
+ case EP93XX_SYSCON_CLKDIV_MASK:
+ return 2; /* PLL2 */
+ default:
+ return 0; /* XTALI */
+ };
+}
+
+static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index)
+{
+ struct ep93xx_clk *clk = ep93xx_clk_from(hw);
+ struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
+ u32 val;
+
+ if (index >= 3)
+ return -EINVAL;
+
+ guard(spinlock_irqsave)(&priv->lock);
+
+ regmap_read(priv->map, clk->reg, &val);
+ val &= ~(EP93XX_SYSCON_CLKDIV_MASK);
+ val |= index > 0 ? EP93XX_SYSCON_CLKDIV_ESEL : 0;
+ val |= index > 1 ? EP93XX_SYSCON_CLKDIV_PSEL : 0;
+
+ ep93xx_clk_write(priv, clk->reg, val);
+
+ return 0;
+}
+
+static bool is_best(unsigned long rate, unsigned long now,
+ unsigned long best)
+{
+ return abs_diff(rate, now) < abs_diff(rate, best);
+}
+
+static int ep93xx_mux_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ unsigned long best_rate = 0, actual_rate, mclk_rate;
+ unsigned long rate = req->rate;
+ struct clk_hw *parent_best = NULL;
+ unsigned long parent_rate_best;
+ unsigned long parent_rate;
+ int div, pdiv;
+ unsigned int i;
+
+ /*
+ * Try the two pll's and the external clock,
+ * because the valid predividers are 2, 2.5 and 3, we multiply
+ * all the clocks by 2 to avoid floating point math.
+ *
+ * This is based on the algorithm in the ep93xx raster guide:
+ * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
+ *
+ */
+ for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
+ struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
+
+ parent_rate = clk_hw_get_rate(parent);
+ mclk_rate = parent_rate * 2;
+
+ /* Try each predivider value */
+ for (pdiv = 4; pdiv <= 6; pdiv++) {
+ div = DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv);
+ if (!in_range(div, 1, 127))
+ continue;
+
+ actual_rate = DIV_ROUND_CLOSEST(mclk_rate, pdiv * div);
+ if (is_best(rate, actual_rate, best_rate)) {
+ best_rate = actual_rate;
+ parent_rate_best = parent_rate;
+ parent_best = parent;
+ }
+ }
+ }
+
+ if (!parent_best)
+ return -EINVAL;
+
+ req->best_parent_rate = parent_rate_best;
+ req->best_parent_hw = parent_best;
+ req->rate = best_rate;
+
+ return 0;
+}
+
+static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct ep93xx_clk *clk = ep93xx_clk_from(hw);
+ struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
+ unsigned int pdiv, div;
+ u32 val;
+
+ regmap_read(priv->map, clk->reg, &val);
+ pdiv = (val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & GENMASK(1, 0);
+ div = val & GENMASK(6, 0);
+ if (!div)
+ return 0;
+
+ return DIV_ROUND_CLOSEST(parent_rate * 2, (pdiv + 3) * div);
+}
+
+static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct ep93xx_clk *clk = ep93xx_clk_from(hw);
+ struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
+ int pdiv, div, npdiv, ndiv;
+ unsigned long actual_rate, mclk_rate, rate_err = ULONG_MAX;
+ u32 val;
+
+ regmap_read(priv->map, clk->reg, &val);
+ mclk_rate = parent_rate * 2;
+
+ for (pdiv = 4; pdiv <= 6; pdiv++) {
+ div = DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv);
+ if (!in_range(div, 1, 127))
+ continue;
+
+ actual_rate = DIV_ROUND_CLOSEST(mclk_rate, pdiv * div);
+ if (abs(actual_rate - rate) < rate_err) {
+ npdiv = pdiv - 3;
+ ndiv = div;
+ rate_err = abs(actual_rate - rate);
+ }
+ }
+
+ if (rate_err == ULONG_MAX)
+ return -EINVAL;
+
+ /*
+ * Clear old dividers.
+ * Bit 7 is reserved bit in all ClkDiv registers.
+ */
+ val &= ~(GENMASK(9, 0) & ~BIT(7));
+
+ /* Set the new pdiv and div bits for the new clock rate */
+ val |= (npdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | ndiv;
+
+ ep93xx_clk_write(priv, clk->reg, val);
+
+ return 0;
+}
+
+static const struct clk_ops clk_ddiv_ops = {
+ .enable = ep93xx_clk_enable,
+ .disable = ep93xx_clk_disable,
+ .is_enabled = ep93xx_clk_is_enabled,
+ .get_parent = ep93xx_mux_get_parent,
+ .set_parent = ep93xx_mux_set_parent_lock,
+ .determine_rate = ep93xx_mux_determine_rate,
+ .recalc_rate = ep93xx_ddiv_recalc_rate,
+ .set_rate = ep93xx_ddiv_set_rate,
+};
+
+static int clk_hw_register_ddiv(struct ep93xx_clk *clk,
+ const char *name,
+ struct clk_parent_data *parent_data,
+ u8 num_parents,
+ unsigned int reg,
+ u8 bit_idx)
+{
+ struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
+ struct clk_init_data init = { };
+
+ init.name = name;
+ init.ops = &clk_ddiv_ops;
+ init.flags = 0;
+ init.parent_data = parent_data;
+ init.num_parents = num_parents;
+
+ clk->reg = reg;
+ clk->bit_idx = bit_idx;
+ clk->hw.init = &init;
+
+ return devm_clk_hw_register(priv->dev, &clk->hw);
+}
+
+static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct ep93xx_clk *clk = ep93xx_clk_from(hw);
+ struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
+ u32 val;
+ u8 index;
+
+ regmap_read(priv->map, clk->reg, &val);
+ index = (val & clk->mask) >> clk->shift;
+ if (index > clk->num_div)
+ return 0;
+
+ return DIV_ROUND_CLOSEST(parent_rate, clk->div[index]);
+}
+
+static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct ep93xx_clk *clk = ep93xx_clk_from(hw);
+ unsigned long best = 0, now;
+ unsigned int i;
+
+ for (i = 0; i < clk->num_div; i++) {
+ if ((rate * clk->div[i]) == *parent_rate)
+ return rate;
+
+ now = DIV_ROUND_CLOSEST(*parent_rate, clk->div[i]);
+ if (!best || is_best(rate, now, best))
+ best = now;
+ }
+
+ return best;
+}
+
+static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct ep93xx_clk *clk = ep93xx_clk_from(hw);
+ struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
+ unsigned int i;
+ u32 val;
+
+ regmap_read(priv->map, clk->reg, &val);
+ val &= ~clk->mask;
+ for (i = 0; i < clk->num_div; i++)
+ if (rate == DIV_ROUND_CLOSEST(parent_rate, clk->div[i]))
+ break;
+
+ if (i == clk->num_div)
+ return -EINVAL;
+
+ val |= i << clk->shift;
+
+ ep93xx_clk_write(priv, clk->reg, val);
+
+ return 0;
+}
+
+static const struct clk_ops ep93xx_div_ops = {
+ .enable = ep93xx_clk_enable,
+ .disable = ep93xx_clk_disable,
+ .is_enabled = ep93xx_clk_is_enabled,
+ .recalc_rate = ep93xx_div_recalc_rate,
+ .round_rate = ep93xx_div_round_rate,
+ .set_rate = ep93xx_div_set_rate,
+};
+
+static int clk_hw_register_div(struct ep93xx_clk *clk,
+ const char *name,
+ struct clk_parent_data *parent_data,
+ unsigned int reg,
+ u8 enable_bit,
+ u8 shift,
+ u8 width,
+ const char *clk_divisors,
+ u8 num_div)
+{
+ struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
+ struct clk_init_data init = { };
+
+ init.name = name;
+ init.ops = &ep93xx_div_ops;
+ init.flags = 0;
+ init.parent_data = parent_data;
+ init.num_parents = 1;
+
+ clk->reg = reg;
+ clk->bit_idx = enable_bit;
+ clk->mask = GENMASK(shift + width - 1, shift);
+ clk->shift = shift;
+ clk->div = clk_divisors;
+ clk->num_div = num_div;
+ clk->hw.init = &init;
+
+ return devm_clk_hw_register(priv->dev, &clk->hw);
+}
+
+struct ep93xx_gate {
+ unsigned int idx;
+ unsigned int bit;
+ const char *name;
+};
+
+static const struct ep93xx_gate ep93xx_uarts[] = {
+ { EP93XX_CLK_UART1, EP93XX_SYSCON_DEVCFG_U1EN, "uart1" },
+ { EP93XX_CLK_UART2, EP93XX_SYSCON_DEVCFG_U2EN, "uart2" },
+ { EP93XX_CLK_UART3, EP93XX_SYSCON_DEVCFG_U3EN, "uart3" },
+};
+
+static int ep93xx_uart_clock_init(struct ep93xx_clk_priv *priv)
+{
+ struct clk_parent_data parent_data = { };
+ unsigned int i, idx, ret, clk_uart_div;
+ struct ep93xx_clk *clk;
+ u32 val;
+
+ regmap_read(priv->map, EP93XX_SYSCON_PWRCNT, &val);
+ if (val & EP93XX_SYSCON_PWRCNT_UARTBAUD)
+ clk_uart_div = 1;
+ else
+ clk_uart_div = 2;
+
+ priv->fixed[EP93XX_CLK_UART] =
+ clk_hw_register_fixed_factor(NULL, "uart", "xtali", 0, 1, clk_uart_div);
+ parent_data.hw = priv->fixed[EP93XX_CLK_UART];
+
+ /* parenting uart gate clocks to uart clock */
+ for (i = 0; i < ARRAY_SIZE(ep93xx_uarts); i++) {
+ idx = ep93xx_uarts[i].idx - EP93XX_CLK_UART1;
+ clk = &priv->reg[idx];
+ clk->idx = idx;
+ ret = ep93xx_clk_register_gate(clk,
+ ep93xx_uarts[i].name,
+ &parent_data, CLK_SET_RATE_PARENT,
+ EP93XX_SYSCON_DEVCFG,
+ ep93xx_uarts[i].bit);
+ if (ret)
+ return dev_err_probe(priv->dev, ret,
+ "failed to register uart[%d] clock\n", i);
+ }
+
+ return 0;
+}
+
+static const struct ep93xx_gate ep93xx_dmas[] = {
+ { EP93XX_CLK_M2M0, EP93XX_SYSCON_PWRCNT_DMA_M2M0, "m2m0" },
+ { EP93XX_CLK_M2M1, EP93XX_SYSCON_PWRCNT_DMA_M2M1, "m2m1" },
+ { EP93XX_CLK_M2P0, EP93XX_SYSCON_PWRCNT_DMA_M2P0, "m2p0" },
+ { EP93XX_CLK_M2P1, EP93XX_SYSCON_PWRCNT_DMA_M2P1, "m2p1" },
+ { EP93XX_CLK_M2P2, EP93XX_SYSCON_PWRCNT_DMA_M2P2, "m2p2" },
+ { EP93XX_CLK_M2P3, EP93XX_SYSCON_PWRCNT_DMA_M2P3, "m2p3" },
+ { EP93XX_CLK_M2P4, EP93XX_SYSCON_PWRCNT_DMA_M2P4, "m2p4" },
+ { EP93XX_CLK_M2P5, EP93XX_SYSCON_PWRCNT_DMA_M2P5, "m2p5" },
+ { EP93XX_CLK_M2P6, EP93XX_SYSCON_PWRCNT_DMA_M2P6, "m2p6" },
+ { EP93XX_CLK_M2P7, EP93XX_SYSCON_PWRCNT_DMA_M2P7, "m2p7" },
+ { EP93XX_CLK_M2P8, EP93XX_SYSCON_PWRCNT_DMA_M2P8, "m2p8" },
+ { EP93XX_CLK_M2P9, EP93XX_SYSCON_PWRCNT_DMA_M2P9, "m2p9" },
+};
+
+static int ep93xx_dma_clock_init(struct ep93xx_clk_priv *priv)
+{
+ struct clk_parent_data parent_data = { };
+ unsigned int i, idx;
+
+ parent_data.hw = priv->fixed[EP93XX_CLK_HCLK];
+ for (i = 0; i < ARRAY_SIZE(ep93xx_dmas); i++) {
+ idx = ep93xx_dmas[i].idx;
+ priv->fixed[idx] = devm_clk_hw_register_gate_parent_data(priv->dev,
+ ep93xx_dmas[i].name,
+ &parent_data, 0,
+ priv->base + EP93XX_SYSCON_PWRCNT,
+ ep93xx_dmas[i].bit,
+ 0,
+ &priv->lock);
+ if (IS_ERR(priv->fixed[idx]))
+ return PTR_ERR(priv->fixed[idx]);
+ }
+
+ return 0;
+}
+
+static struct clk_hw *of_clk_ep93xx_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct ep93xx_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < EP93XX_CLK_UART1)
+ return priv->fixed[idx];
+
+ if (idx <= EP93XX_CLK_I2S_LRCLK)
+ return &priv->reg[idx - EP93XX_CLK_UART1].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+/*
+ * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
+ */
+static unsigned long calc_pll_rate(u64 rate, u32 config_word)
+{
+ rate *= ((config_word >> 11) & GENMASK(4, 0)) + 1; /* X1FBD */
+ rate *= ((config_word >> 5) & GENMASK(5, 0)) + 1; /* X2FBD */
+ do_div(rate, (config_word & GENMASK(4, 0)) + 1); /* X2IPD */
+ rate >>= (config_word >> 16) & GENMASK(1, 0); /* PS */
+
+ return rate;
+}
+
+#define devm_ep93xx_clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, fixed_rate) \
+ __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
+ (parent_data), (flags), (fixed_rate), 0, 0, true)
+
+static int ep93xx_plls_init(struct ep93xx_clk_priv *priv)
+{
+ const char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
+ const char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
+ const char pclk_divisors[] = { 1, 2, 4, 8 };
+ struct clk_parent_data xtali = { .index = 0 };
+ unsigned int clk_f_div, clk_h_div, clk_p_div;
+ unsigned long clk_pll1_rate, clk_pll2_rate;
+ struct device *dev = priv->dev;
+ struct clk_hw *hw, *pll1;
+ u32 value;
+
+ /* Determine the bootloader configured pll1 rate */
+ regmap_read(priv->map, EP93XX_SYSCON_CLKSET1, &value);
+
+ if (value & EP93XX_SYSCON_CLKSET1_NBYP1)
+ clk_pll1_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value);
+ else
+ clk_pll1_rate = EP93XX_EXT_CLK_RATE;
+
+ pll1 = devm_ep93xx_clk_hw_register_fixed_rate_parent_data(dev, "pll1", &xtali,
+ 0, clk_pll1_rate);
+ if (IS_ERR(pll1))
+ return PTR_ERR(pll1);
+
+ priv->fixed[EP93XX_CLK_PLL1] = pll1;
+
+ /* Initialize the pll1 derived clocks */
+ clk_f_div = fclk_divisors[(value >> 25) & GENMASK(2, 0)];
+ clk_h_div = hclk_divisors[(value >> 20) & GENMASK(2, 0)];
+ clk_p_div = pclk_divisors[(value >> 18) & GENMASK(1, 0)];
+
+ hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "fclk", pll1, 0, 1, clk_f_div);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ priv->fixed[EP93XX_CLK_FCLK] = hw;
+
+ hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "hclk", pll1, 0, 1, clk_h_div);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ priv->fixed[EP93XX_CLK_HCLK] = hw;
+
+ hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "pclk", hw, 0, 1, clk_p_div);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ priv->fixed[EP93XX_CLK_PCLK] = hw;
+
+ /* Determine the bootloader configured pll2 rate */
+ regmap_read(priv->map, EP93XX_SYSCON_CLKSET2, &value);
+ if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
+ clk_pll2_rate = EP93XX_EXT_CLK_RATE;
+ else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
+ clk_pll2_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value);
+ else
+ clk_pll2_rate = 0;
+
+ hw = devm_ep93xx_clk_hw_register_fixed_rate_parent_data(dev, "pll2", &xtali,
+ 0, clk_pll2_rate);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ priv->fixed[EP93XX_CLK_PLL2] = hw;
+
+ return 0;
+}
+
+static int ep93xx_clk_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ struct ep93xx_regmap_adev *rdev = to_ep93xx_regmap_adev(adev);
+ struct clk_parent_data xtali = { .index = 0 };
+ struct clk_parent_data ddiv_pdata[3] = { };
+ unsigned int clk_spi_div, clk_usb_div;
+ struct clk_parent_data pdata = {};
+ struct device *dev = &adev->dev;
+ struct ep93xx_clk_priv *priv;
+ struct ep93xx_clk *clk;
+ struct clk_hw *hw;
+ unsigned int idx;
+ int ret;
+ u32 value;
+
+ priv = devm_kzalloc(dev, struct_size(priv, reg, 10), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->lock);
+ priv->dev = dev;
+ priv->aux_dev = rdev;
+ priv->map = rdev->map;
+ priv->base = rdev->base;
+
+ ret = ep93xx_plls_init(priv);
+ if (ret)
+ return ret;
+
+ regmap_read(priv->map, EP93XX_SYSCON_CLKSET2, &value);
+ clk_usb_div = (value >> 28 & GENMASK(3, 0)) + 1;
+ hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "usb_clk",
+ priv->fixed[EP93XX_CLK_PLL2], 0, 1,
+ clk_usb_div);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ priv->fixed[EP93XX_CLK_USB] = hw;
+
+ ret = ep93xx_uart_clock_init(priv);
+ if (ret)
+ return ret;
+
+ ret = ep93xx_dma_clock_init(priv);
+ if (ret)
+ return ret;
+
+ clk_spi_div = id->driver_data;
+ hw = devm_clk_hw_register_fixed_factor_index(dev, "ep93xx-spi.0",
+ 0, /* XTALI external clock */
+ 0, 1, clk_spi_div);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ priv->fixed[EP93XX_CLK_SPI] = hw;
+
+ /* PWM clock */
+ hw = devm_clk_hw_register_fixed_factor_index(dev, "pwm_clk", 0, /* XTALI external clock */
+ 0, 1, 1);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ priv->fixed[EP93XX_CLK_PWM] = hw;
+
+ /* USB clock */
+ pdata.hw = priv->fixed[EP93XX_CLK_USB];
+ hw = devm_clk_hw_register_gate_parent_data(priv->dev, "ohci-platform", &pdata,
+ 0, priv->base + EP93XX_SYSCON_PWRCNT,
+ EP93XX_SYSCON_PWRCNT_USH_EN, 0,
+ &priv->lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ priv->fixed[EP93XX_CLK_USB] = hw;
+
+ ddiv_pdata[0].index = 0; /* XTALI external clock */
+ ddiv_pdata[1].hw = priv->fixed[EP93XX_CLK_PLL1];
+ ddiv_pdata[2].hw = priv->fixed[EP93XX_CLK_PLL2];
+
+ /* touchscreen/ADC clock */
+ idx = EP93XX_CLK_ADC - EP93XX_CLK_UART1;
+ clk = &priv->reg[idx];
+ clk->idx = idx;
+ ret = clk_hw_register_div(clk, "ep93xx-adc", &xtali,
+ EP93XX_SYSCON_KEYTCHCLKDIV,
+ EP93XX_SYSCON_KEYTCHCLKDIV_TSEN,
+ EP93XX_SYSCON_KEYTCHCLKDIV_ADIV,
+ 1,
+ adc_divisors,
+ ARRAY_SIZE(adc_divisors));
+
+
+ /* keypad clock */
+ idx = EP93XX_CLK_KEYPAD - EP93XX_CLK_UART1;
+ clk = &priv->reg[idx];
+ clk->idx = idx;
+ ret = clk_hw_register_div(clk, "ep93xx-keypad", &xtali,
+ EP93XX_SYSCON_KEYTCHCLKDIV,
+ EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
+ EP93XX_SYSCON_KEYTCHCLKDIV_KDIV,
+ 1,
+ adc_divisors,
+ ARRAY_SIZE(adc_divisors));
+
+ /*
+ * On reset PDIV and VDIV is set to zero, while PDIV zero
+ * means clock disable, VDIV shouldn't be zero.
+ * So we set both video and i2s dividers to minimum.
+ * ENA - Enable CLK divider.
+ * PDIV - 00 - Disable clock
+ * VDIV - at least 2
+ */
+
+ /* Check and enable video clk registers */
+ regmap_read(priv->map, EP93XX_SYSCON_VIDCLKDIV, &value);
+ value |= BIT(EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2;
+ ep93xx_clk_write(priv, EP93XX_SYSCON_VIDCLKDIV, value);
+
+ /* Check and enable i2s clk registers */
+ regmap_read(priv->map, EP93XX_SYSCON_I2SCLKDIV, &value);
+ value |= BIT(EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2;
+
+ /*
+ * Override the SAI_MSTR_CLK_CFG from the I2S block and use the
+ * I2SClkDiv Register settings. LRCLK transitions on the falling SCLK
+ * edge.
+ */
+ value |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
+ ep93xx_clk_write(priv, EP93XX_SYSCON_I2SCLKDIV, value);
+
+ /* video clk */
+ idx = EP93XX_CLK_VIDEO - EP93XX_CLK_UART1;
+ clk = &priv->reg[idx];
+ clk->idx = idx;
+ ret = clk_hw_register_ddiv(clk, "ep93xx-fb",
+ ddiv_pdata, ARRAY_SIZE(ddiv_pdata),
+ EP93XX_SYSCON_VIDCLKDIV,
+ EP93XX_SYSCON_CLKDIV_ENABLE);
+
+ /* i2s clk */
+ idx = EP93XX_CLK_I2S_MCLK - EP93XX_CLK_UART1;
+ clk = &priv->reg[idx];
+ clk->idx = idx;
+ ret = clk_hw_register_ddiv(clk, "mclk",
+ ddiv_pdata, ARRAY_SIZE(ddiv_pdata),
+ EP93XX_SYSCON_I2SCLKDIV,
+ EP93XX_SYSCON_CLKDIV_ENABLE);
+
+ /* i2s sclk */
+ idx = EP93XX_CLK_I2S_SCLK - EP93XX_CLK_UART1;
+ clk = &priv->reg[idx];
+ clk->idx = idx;
+ pdata.hw = &priv->reg[EP93XX_CLK_I2S_MCLK - EP93XX_CLK_UART1].hw;
+ ret = clk_hw_register_div(clk, "sclk", &pdata,
+ EP93XX_SYSCON_I2SCLKDIV,
+ EP93XX_SYSCON_I2SCLKDIV_SENA,
+ 16, /* EP93XX_I2SCLKDIV_SDIV_SHIFT */
+ 1, /* EP93XX_I2SCLKDIV_SDIV_WIDTH */
+ sclk_divisors,
+ ARRAY_SIZE(sclk_divisors));
+
+ /* i2s lrclk */
+ idx = EP93XX_CLK_I2S_LRCLK - EP93XX_CLK_UART1;
+ clk = &priv->reg[idx];
+ clk->idx = idx;
+ pdata.hw = &priv->reg[EP93XX_CLK_I2S_SCLK - EP93XX_CLK_UART1].hw;
+ ret = clk_hw_register_div(clk, "lrclk", &pdata,
+ EP93XX_SYSCON_I2SCLKDIV,
+ EP93XX_SYSCON_I2SCLKDIV_SENA,
+ 17, /* EP93XX_I2SCLKDIV_LRDIV32_SHIFT */
+ 2, /* EP93XX_I2SCLKDIV_LRDIV32_WIDTH */
+ lrclk_divisors,
+ ARRAY_SIZE(lrclk_divisors));
+
+ /* IrDa clk uses same pattern but no init code presents in original clock driver */
+ return devm_of_clk_add_hw_provider(priv->dev, of_clk_ep93xx_get, priv);
+}
+
+static const struct auxiliary_device_id ep93xx_clk_ids[] = {
+ { .name = "soc_ep93xx.clk-ep93xx", .driver_data = 2, },
+ { .name = "soc_ep93xx.clk-ep93xx.e2", .driver_data = 1, },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(auxiliary, ep93xx_clk_ids);
+
+static struct auxiliary_driver ep93xx_clk_driver = {
+ .probe = ep93xx_clk_probe,
+ .id_table = ep93xx_clk_ids,
+};
+module_auxiliary_driver(ep93xx_clk_driver);
--
2.43.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v11 06/38] dt-bindings: soc: Add Cirrus EP93xx
2024-07-15 8:38 [PATCH v11 00/38] ep93xx device tree conversion Nikita Shubin via B4 Relay
2024-07-15 8:38 ` [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx Nikita Shubin via B4 Relay
@ 2024-07-15 8:38 ` Nikita Shubin via B4 Relay
2024-07-15 12:12 ` [PATCH v11 00/38] ep93xx device tree conversion Rob Herring (Arm)
2 siblings, 0 replies; 12+ messages in thread
From: Nikita Shubin via B4 Relay @ 2024-07-15 8:38 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Turquette,
Stephen Boyd, Nikita Shubin, Alexander Sverdlin
Cc: Krzysztof Kozlowski, devicetree, linux-kernel, linux-clk
From: Nikita Shubin <nikita.shubin@maquefel.me>
Add device tree bindings for the Cirrus Logic EP93xx SoC.
Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
---
.../bindings/arm/cirrus/cirrus,ep9301.yaml | 38 +++++++++
.../bindings/soc/cirrus/cirrus,ep9301-syscon.yaml | 94 ++++++++++++++++++++++
include/dt-bindings/clock/cirrus,ep9301-syscon.h | 46 +++++++++++
3 files changed, 178 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cirrus/cirrus,ep9301.yaml b/Documentation/devicetree/bindings/arm/cirrus/cirrus,ep9301.yaml
new file mode 100644
index 000000000000..170aad5dd7ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cirrus/cirrus,ep9301.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/cirrus/cirrus,ep9301.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cirrus Logic EP93xx platforms
+
+description:
+ The EP93xx SoC is a ARMv4T-based with 200 MHz ARM9 CPU.
+
+maintainers:
+ - Alexander Sverdlin <alexander.sverdlin@gmail.com>
+ - Nikita Shubin <nikita.shubin@maquefel.me>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: The TS-7250 is a compact, full-featured Single Board
+ Computer (SBC) based upon the Cirrus EP9302 ARM9 CPU
+ items:
+ - const: technologic,ts7250
+ - const: cirrus,ep9301
+
+ - description: The Liebherr BK3 is a derivate from ts7250 board
+ items:
+ - const: liebherr,bk3
+ - const: cirrus,ep9301
+
+ - description: EDB302 is an evaluation board by Cirrus Logic,
+ based on a Cirrus Logic EP9302 CPU
+ items:
+ - const: cirrus,edb9302
+ - const: cirrus,ep9301
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/soc/cirrus/cirrus,ep9301-syscon.yaml b/Documentation/devicetree/bindings/soc/cirrus/cirrus,ep9301-syscon.yaml
new file mode 100644
index 000000000000..7cb1b4114985
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/cirrus/cirrus,ep9301-syscon.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/cirrus/cirrus,ep9301-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cirrus Logic EP93xx Platforms System Controller
+
+maintainers:
+ - Alexander Sverdlin <alexander.sverdlin@gmail.com>
+ - Nikita Shubin <nikita.shubin@maquefel.me>
+
+description: |
+ Central resources are controlled by a set of software-locked registers,
+ which can be used to prevent accidental accesses. Syscon generates
+ the various bus and peripheral clocks and controls the system startup
+ configuration.
+
+ The System Controller (Syscon) provides:
+ - Clock control
+ - Power management
+ - System configuration management
+
+ Syscon registers are common for all EP93xx SoC's, through some actual peripheral
+ may be missing depending on actual SoC model.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - cirrus,ep9302-syscon
+ - cirrus,ep9307-syscon
+ - cirrus,ep9312-syscon
+ - cirrus,ep9315-syscon
+ - const: cirrus,ep9301-syscon
+ - const: syscon
+ - items:
+ - const: cirrus,ep9301-syscon
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ items:
+ - description: reference clock
+
+patternProperties:
+ '^pins-':
+ type: object
+ description: pin node
+ $ref: /schemas/pinctrl/pinmux-node.yaml
+
+ properties:
+ function:
+ enum: [ spi, ac97, i2s, pwm, keypad, pata, lcd, gpio ]
+
+ groups:
+ enum: [ ssp, ac97, i2s_on_ssp, i2s_on_ac97, pwm1, gpio1agrp,
+ gpio2agrp, gpio3agrp, gpio4agrp, gpio6agrp, gpio7agrp,
+ rasteronsdram0grp, rasteronsdram3grp, keypadgrp, idegrp ]
+
+ required:
+ - function
+ - groups
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@80930000 {
+ compatible = "cirrus,ep9301-syscon", "syscon";
+ reg = <0x80930000 0x1000>;
+
+ #clock-cells = <1>;
+ clocks = <&xtali>;
+
+ spi_default_pins: pins-spi {
+ function = "spi";
+ groups = "ssp";
+ };
+ };
diff --git a/include/dt-bindings/clock/cirrus,ep9301-syscon.h b/include/dt-bindings/clock/cirrus,ep9301-syscon.h
new file mode 100644
index 000000000000..6bb8f532e7d0
--- /dev/null
+++ b/include/dt-bindings/clock/cirrus,ep9301-syscon.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+#ifndef DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H
+#define DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H
+
+#define EP93XX_CLK_PLL1 0
+#define EP93XX_CLK_PLL2 1
+
+#define EP93XX_CLK_FCLK 2
+#define EP93XX_CLK_HCLK 3
+#define EP93XX_CLK_PCLK 4
+
+#define EP93XX_CLK_UART 5
+#define EP93XX_CLK_SPI 6
+#define EP93XX_CLK_PWM 7
+#define EP93XX_CLK_USB 8
+
+#define EP93XX_CLK_M2M0 9
+#define EP93XX_CLK_M2M1 10
+
+#define EP93XX_CLK_M2P0 11
+#define EP93XX_CLK_M2P1 12
+#define EP93XX_CLK_M2P2 13
+#define EP93XX_CLK_M2P3 14
+#define EP93XX_CLK_M2P4 15
+#define EP93XX_CLK_M2P5 16
+#define EP93XX_CLK_M2P6 17
+#define EP93XX_CLK_M2P7 18
+#define EP93XX_CLK_M2P8 19
+#define EP93XX_CLK_M2P9 20
+
+#define EP93XX_CLK_UART1 21
+#define EP93XX_CLK_UART2 22
+#define EP93XX_CLK_UART3 23
+
+#define EP93XX_CLK_ADC 24
+#define EP93XX_CLK_ADC_EN 25
+
+#define EP93XX_CLK_KEYPAD 26
+
+#define EP93XX_CLK_VIDEO 27
+
+#define EP93XX_CLK_I2S_MCLK 28
+#define EP93XX_CLK_I2S_SCLK 29
+#define EP93XX_CLK_I2S_LRCLK 30
+
+#endif /* DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H */
--
2.43.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v11 00/38] ep93xx device tree conversion
2024-07-15 8:38 [PATCH v11 00/38] ep93xx device tree conversion Nikita Shubin via B4 Relay
2024-07-15 8:38 ` [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx Nikita Shubin via B4 Relay
2024-07-15 8:38 ` [PATCH v11 06/38] dt-bindings: soc: Add " Nikita Shubin via B4 Relay
@ 2024-07-15 12:12 ` Rob Herring (Arm)
2 siblings, 0 replies; 12+ messages in thread
From: Rob Herring (Arm) @ 2024-07-15 12:12 UTC (permalink / raw)
To: Nikita Shubin
Cc: linux-gpio, David S. Miller, Paolo Abeni, Andy Shevchenko,
linux-mtd, Liam Girdwood, linux-pm, linux-clk, netdev,
Bartosz Golaszewski, Vinod Koul, Dmitry Torokhov, Olof Johansson,
Niklas Cassel, linux-arm-kernel, Jakub Kicinski,
Alexander Sverdlin, Andy Shevchenko, dmaengine,
Bartosz Golaszewski, Russell King, Michael Turquette, Rob Herring,
Guenter Roeck, devicetree, Conor Dooley, Wu, Aaron, Lee Jones,
linux-watchdog, Wim Van Sebroeck, Miquel Raynal, Damien Le Moal,
Linus Walleij, Thierry Reding, Vignesh Raghavendra, linux-pwm,
Uwe Kleine-König, Ralf Baechle, Sebastian Reichel,
Krzysztof Kozlowski, linux-ide, Stephen Boyd, Krzysztof Kozlowski,
linux-spi, Andy Shevchenko, Mark Brown, Hartley Sweeten,
linux-kernel, Takashi Iwai, Andrew Lunn, Richard Weinberger,
Eric Dumazet, linux-sound, Arnd Bergmann, linux-input,
Jaroslav Kysela, Sergey Shtylyov, Lukasz Majewski
On Mon, 15 Jul 2024 11:38:04 +0300, Nikita Shubin wrote:
> The goal is to recieve ACKs for all patches in series to merge it via Arnd branch.
>
> It was decided from the very beginning of these series, mostly because
> it's a full conversion of platform code to DT and it seemed not
> convenient to maintain compatibility with both platform and DT.
>
> Following patches require attention from Stephen Boyd or clk subsystem:
>
> - clk: ep93xx: add DT support for Cirrus EP93xx
>
> It is purely possible to add something like devm_clk_hw_register_fixed_rate_parent_data()
> for devm managed version clk_hw_register_fixed_rate_parent_data(), still i would like to
> leave for the time after this series if it's all possible.
>
> Couse may be it's better to add something like
> devm_clk_hw_register_fixed_rate_index() like it's done for
> devm_clk_hw_register_fixed_factor_index().
>
> Changelog for this patch:
> - added devm_ep93xx_clk_hw_register_fixed_rate_parent_data() for
> devm_ version of clk_hw_register_fixed_rate_parent_data()
> - s/devm_clk_hw_register_fixed_rate()/devm_ep93xx_clk_hw_register_fixed_rate_parent_data()/
> - replaced all devm_clk_hw_register_fixed_factor() to
> devm_clk_hw_register_fixed_factor_parent_hw() or
> devm_clk_hw_register_fixed_factor_index()
> - s/devm_clk_hw_register_gate()/devm_clk_hw_register_gate_parent_data()
>
> Stephen - it think that's you was aiming for - to get rid of all
> functions that are using const char* parent_name directly instead of
> clk_hw or clk_parent_data.
>
> Patches should be formated with '--histogram'
>
> ---
> Changes in v11:
> - clk: ep93xx: add DT support for Cirrus EP93xx
> - added devm_ep93xx_clk_hw_register_fixed_rate_parent_data() for
> devm_ version of clk_hw_register_fixed_rate_parent_data()
> - s/devm_clk_hw_register_fixed_rate()/devm_ep93xx_clk_hw_register_fixed_rate_parent_data()/
> - replaced all devm_clk_hw_register_fixed_factor() to
> devm_clk_hw_register_fixed_factor_parent_hw() or
> devm_clk_hw_register_fixed_factor_index()
> - s/devm_clk_hw_register_gate()/devm_clk_hw_register_gate_parent_data()
>
> - Link to v10: https://lore.kernel.org/r/20240617-ep93xx-v10-0-662e640ed811@maquefel.me
>
> Changes in v10:
>
> Reordered SoB tags to make sure they appear before Rb and Acked tags.
>
> dmaengine: cirrus: Convert to DT for Cirrus EP93xx
> - s/dma/dmaengine/ title
>
> dmaengine: cirrus: remove platform code
> - s/dma/dmaengine/ title
>
> soc: Add SoC driver for Cirrus ep93xx:
> - added __init for ep93xx_adev_alloc(), ep93xx_controller_register()
> - added static, __initconst for pinctrl_names[]
> - clk revision for SPI is now resolved here through differently named
> clk device
> - more verbose Kconfig description
>
> clk: ep93xx: add DT support for Cirrus EP93xx:
> - dropped includes
> - dropped ep93xx_soc_table[]
> - add different named clk and dropped involved includes
> - moved pll's and fclk, hclk, pclk init to separate function
> - fixed ep93xx_clk_ids[] explicit lines
>
> - Link to v9: https://lore.kernel.org/r/20240326-ep93xx-v9-0-156e2ae5dfc8@maquefel.me
> - Link to v2 clk: https://lore.kernel.org/r/20240408-ep93xx-clk-v2-1-adcd68c13753@maquefel.me
>
> Changes in v9:
>
> ARM: dts: add Cirrus EP93XX SoC .dtsi
> - added #interrupt-cells to gpio nodes with interrupts-controller
> - fixed EOF
>
> ARM: dts: ep93xx: Add EDB9302 DT
> - Alexander Sverdlin: fixed bug in Device Tree resulting in CS4271 not working
>
> input: keypad: ep93xx: add DT support for Cirrus EP93xx
> - fixed identation and type
>
> - Link to v8: https://lore.kernel.org/r/20240226-ep93xx-v8-0-3136dca7238f@maquefel.me/
>
> Changes in v8:
>
> soc: Add SoC driver for Cirrus ep93xx
> - fixed freeing adev instead of rdev
> - use __free() and no_free_ptr() for rdev allocation
> - s/of_device_get_match_data()/device_get_match_data()/
>
> ata: pata_ep93xx: add device tree support
> - more appropriate usage of dev_err_probe()
>
> pinctrl: add a Cirrus ep93xx SoC pin controller
> - 8 per row in ide_9312_pins
>
> mtd: rawnand: add support for ts72xx
> - fwnode_handle_put() for fwnode in ts72xx_nand_remove()
>
> - Link to v7: https://lore.kernel.org/r/20240118-ep93xx-v7-0-d953846ae771@maquefel.me
>
> Changes in v7:
>
> mtd: rawnand: add support for ts72xx
> - fixed KConfig description
>
> ARM: ep93xx: Add terminator to gpiod_lookup_table
> - + Reported-by, Fixes
>
> ARM: ep93xx: add regmap aux_dev
> - + trailing comma
> - - #include <linux/spinlock.h>
>
> clk: ep93xx: add DT support for Cirrus EP93xx
> - dropped unused defines
> - return from default in ep93xx_mux_get_parent()
> - use guard() in ep93xx_mux_set_parent_lock()
> - <math.h> header for abs_diff()
> - fixed comments
>
> pinctrl: add a Cirrus ep93xx SoC pin controller
> - dropped comments for DEVCFG defines
> - <linux/array_size.h> for ARRAY_SIZE()
> - + default in ep93xx_get_group_name()
> - correct cast for id->driver_data
> - s/device_set_of_node_from_dev()/device_set_node()/
>
> power: reset: Add a driver for the ep93xx reset
> - Add <linux/container_of.h>, <linux/errno.h>, <linux/slab.h>
> - Add <linux/module.h>, <linux/mod_devicetable.h>
> - Remove <platform_device.h>
>
> spi: ep93xx: add DT support for Cirrus EP93xx
> - Replace with ret = dev_err_probe(...);
>
> ata: pata_ep93xx: add device tree support
> - fixed wrong rebase with some partes leaked in "ata: pata_ep93xx: remove legacy pinctrl use"
> - fix dma_request_chan() error processing
>
> dma: cirrus: Convert to DT for Cirrus EP93xx
> - fixed commit message (dropped explicit "only")
> - fixed clk_get() processing to defer probe and log spamming
> - refactor ep93xx_m2p_dma_filter()
> - dropped blank line in ep93xx_m2p_dma_of_xlate()
> - refactor ep93xx_m2m_dma_of_xlate()
>
> dma: cirrus: remove platform code
> - s/dma/DMA/ in commit message
>
> soc: Add SoC driver for Cirrus ep93xx
> - add period
> - use cleanup and guard() for spinlocking
> - correct cast for device_get_match_data()
> - dropped dev_info() with SoC revision - i can't find it anywhere since 2.6 :/,
> don't know why i was so sured that ep93xx always printed that
>
> ata: pata_ep93xx: remove legacy pinctrl use
> - made error handling in DMA as Uwe suggested
>
> - Link to v6: https://lore.kernel.org/r/20231212-ep93xx-v6-0-c307b8ac9aa8@maquefel.me
>
> Changes in v6:
>
> - clk: ep93xx: add DT support for Cirrus EP93xx
> - s/spin_lock_irqsave()/guard()/
> - refactor index check in ep93xx_mux_set_parent_lock() to something more readable
> - use in_range in ep93xx_mux_set_parent_lock()/ep93xx_ddiv_set_rate()
> - use GENMASK() in ep93xx_ddiv_recalc_rate()
> - comment reserved bit in ep93xx_ddiv_set_rate()
> - move out from loop ClkDiv value assigment
> - some style fixes
>
> Andy, i was i asked to set index of XTALI explicitly, i am not setting ddiv_pdata
> there becouse only XTALI is jnown in advance, and i think setting them in one place is more convenient.
>
> - pinctrl: add a Cirrus ep93xx SoC pin controller
> - drop OF from Kconfig
> - droped linux/of.h include
> - add space to */ where it is applicable
> - add coma in multiline assigment
> - "return NULL" as default case in ep93xx_get_group_name()
> - fixed casting id->driver_data
> - use device_set_of_node_from_dev()
> - use dev_err_probe()
>
> - power: reset: Add a driver for the ep93xx reset
> - drop linux/of.h include
>
> - soc: Add SoC driver for Cirrus ep93xx
> - s/GPL-2.0/GPL-2.0-only/
> - drop linux/kernel.h include
> - + blank line before linux/soc/cirrus/ep93xx.h
> - + blank line after ep93xx_get_soc_rev()
> - + coma for pinctrl_names
> - valid casting to int for of_device_get_match_data() return value
>
> - mtd: rawnand: add support for ts72xx
> - return as part of switch case
> - s/iowrite8/iowrite8_rep/
>
> - net: cirrus: add DT support for Cirrus EP93xx
> - fix header sorting
>
> - dma: cirrus: Convert to DT for Cirrus EP93xx
> - use devm_clk_get
> - use is_slave_direction
>
> Changes in v5:
>
> - gpio: ep93xx: split device in multiple
> - ordered headers
> - use irqd_to_hwirq()
> - s/platform_get_irq()/platform_get_irq_optional()/
>
> - [PATCH v4 02/42] ARM: ep93xx: add swlocked prototypes
> - replaced with ARM: ep93xx: add regmap aux_dev
>
> - [PATCH v4 03/42] dt-bindings: clock: Add Cirrus EP93xx
> - fixed identation
> - removed EP93XX_CLK_END
> - and dropped it
> - clock bindings moved to syscon with renaming to cirrus,ep9301-syscon.h
>
> - clk: ep93xx: add DT support for Cirrus EP93xx
> - convert to auxiliary and use parent device tree node
> - moved all clocks except XTALI here
> - used devm version everywhere and *_parent_hw() instead of passing name where it's possible
> - unfortunately devm_clk_hw_register_fixed_rate doesn't have a parent index version
>
> - [PATCH v4 05/42] dt-bindings: pinctrl: Add Cirrus EP93xx
> - "unevaluatedProperties: false" for pins
> - returned "additionalProperties: false" where it was
> - and dropped it
>
> - pinctrl: add a Cirrus ep93xx SoC pin controller
> - sorted includes
> - convert to auxiliary and use parent device tree node
>
> - power: reset: Add a driver for the ep93xx reset
> - convert to auxiliary device
>
> - dt-bindings: soc: Add Cirrus EP93xx
> - dropped all ref to reboot, clk, pinctrl subnodes
> - added pins, as it's now used for pinctrl
> - added #clock-cells, as it's now used for clk
>
> - dt-bindings: pwm: Add Cirrus EP93xx
> - $ref to pwm.yaml
> - fixed 'pwm-cells'
> - s/additionalProperties/unevaluatedProperties/
>
> - soc: Add SoC driver for Cirrus ep93xx
> - removed clocks, they are moved to clk auxiliary driver, as we dropped the clk dt node
> - removed all swlocked exported functions
> - dropped static spinlock
> - added instantiating auxiliary reboot, clk, pinctrl
>
> - dt-bindings: spi: Add Cirrus EP93xx
> - Document DMA support
>
> - spi: ep93xx: add DT support for Cirrus EP93xx
> - dropped CONFIG_OF and SPI/DMA platform data entirely
> - s/master/host/
> - reworked DMA setup so we can use probe defer
>
> - dt-bindings: dma: Add Cirrus EP93xx
> - dropped bindings header (moved ports description to YAML)
> - changed '#dma-cells' to 2, we use port, direction in cells so we can drop platform code completely
>
> - dma: cirrus: add DT support for Cirrus EP93xx
> - dropped platform probing completely
> - dropped struct ep93xx_dma_data replaced with internal struct ep93xx_dma_chan_cfg with port/direction
> - added xlate functions for m2m/m2p
> - we require filters to set dma_cfg before hw_setup
>
> - dt-bindings: ata: Add Cirrus EP93xx
> - Document DMA support
>
> - ata: pata_ep93xx: add device tree support
> - drop DMA platform header with data
> - use DMA OF so we can defer probing until DMA is up
>
> - ARM: dts: add Cirrus EP93XX SoC .dtsi
> - ARM: dts: ep93xx: add ts7250 board
> - ARM: dts: ep93xx: Add EDB9302 DT
> - replaced "eclk: clock-controller" to syscon reference
> - replaced "pinctrl: pinctrl" to syscon reference
> - gpios are now "enabled" by default
> - reworked i2s node
> - change all dma nodes and refs
>
> - new additions to I2S
> - Document DMA
> - Document Audio Port usage
> - drop legacy DMA support
>
> - Link to v4: https://lore.kernel.org/r/20230915-ep93xx-v4-0-a1d779dcec10@maquefel.me
>
> Changes in v4:
>
> - gpio: ep93xx: split device in multiple
> - s/generic_handle_irq/generic_handle_domain_irq/
> - s/int offset/irq_hw_number_t offset/ though now it looks a bit odd to me
> - drop i = 0
> - drop 'error'
> - use dev_err_probe withour printing devname once again
>
> dt-bindings: clock: Add Cirrus EP93xx
> - renamed cirrus,ep93xx-clock.h -> cirrus,ep9301-clk.h
>
> clk: ep93xx: add DT support for Cirrus EP93xx
> - drop unused includes
> - use .name only for xtali, pll1, pll2 parents
> - convert // to /*
> - pass clk_parent_data instead of char* clock name
>
> dt-bindings: pinctrl: Add Cirrus EP93xx
> - s/additionalProperties/unevaluatedProperties/
>
> dt-bindings: soc: Add Cirrus EP93xx
> - move syscon to soc directory
> - add vendor prefix
> - make reboot same style as pinctrl, clk
> - use absolute path for ref
> - expand example
>
> soc: Add SoC driver for Cirrus ep93xx
> - s/0xf0000000/GENMASK(31, 28)/
> - s/ret/ep93xx_chip_revision(map)/
> - drop symbol exports
> - convert to platform driver
>
> dt-bindings: rtc: Add Cirrus EP93xx
> - allOf: with $ref to rtc.yaml
> - s/additionalProperties/unevaluatedProperties/
>
> dt-bindings: watchdog: Add Cirrus EP93x
> - drop description
> - reword
>
> power: reset: Add a driver for the ep93xx reset
> - lets use 'GPL-2.0+' instead of '(GPL-2.0)'
> - s/of_device/of/
> - drop mdelay with warning
> - return 0 at the end
>
> net: cirrus: add DT support for Cirrus EP93xx
> - fix leaking np
>
> mtd: nand: add support for ts72xx
> - +bits.h
> - drop comment
> - ok to fwnode_get_next_child_node
> - use goto to put handle and nand and report error
>
> ARM: dts: add Cirrus EP93XX SoC .dtsi
> - add simple-bus for ebi, as we don't require to setup anything
> - add arm,pl011 compatible to uart nodes
> - drop i2c-gpio, as it's isn't used anywhere
>
> ARM: dts: ep93xx: add ts7250 board
> - generic node name for temperature-sensor
> - drop i2c
> - move nand, rtc, watchdog to ebi node
>
> - Link to v3: https://lore.kernel.org/r/20230605-ep93xx-v3-0-3d63a5f1103e@maquefel.me
>
> ---
> Alexander Sverdlin (3):
> ASoC: ep93xx: Drop legacy DMA support
> ARM: dts: ep93xx: Add EDB9302 DT
> ASoC: cirrus: edb93xx: Delete driver
>
> Nikita Shubin (35):
> gpio: ep93xx: split device in multiple
> ARM: ep93xx: add regmap aux_dev
> clk: ep93xx: add DT support for Cirrus EP93xx
> pinctrl: add a Cirrus ep93xx SoC pin controller
> power: reset: Add a driver for the ep93xx reset
> dt-bindings: soc: Add Cirrus EP93xx
> soc: Add SoC driver for Cirrus ep93xx
> dt-bindings: dma: Add Cirrus EP93xx
> dmaengine: cirrus: Convert to DT for Cirrus EP93xx
> dt-bindings: watchdog: Add Cirrus EP93x
> watchdog: ep93xx: add DT support for Cirrus EP93xx
> dt-bindings: pwm: Add Cirrus EP93xx
> pwm: ep93xx: add DT support for Cirrus EP93xx
> dt-bindings: spi: Add Cirrus EP93xx
> spi: ep93xx: add DT support for Cirrus EP93xx
> dt-bindings: net: Add Cirrus EP93xx
> net: cirrus: add DT support for Cirrus EP93xx
> dt-bindings: mtd: Add ts7200 nand-controller
> mtd: rawnand: add support for ts72xx
> dt-bindings: ata: Add Cirrus EP93xx
> ata: pata_ep93xx: add device tree support
> dt-bindings: input: Add Cirrus EP93xx keypad
> input: keypad: ep93xx: add DT support for Cirrus EP93xx
> wdt: ts72xx: add DT support for ts72xx
> gpio: ep93xx: add DT support for gpio-ep93xx
> ASoC: dt-bindings: ep93xx: Document DMA support
> ASoC: dt-bindings: ep93xx: Document Audio Port support
> ARM: dts: add Cirrus EP93XX SoC .dtsi
> ARM: dts: ep93xx: add ts7250 board
> ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms
> pwm: ep93xx: drop legacy pinctrl
> ata: pata_ep93xx: remove legacy pinctrl use
> ARM: ep93xx: delete all boardfiles
> ARM: ep93xx: soc: drop defines
> dmaengine: cirrus: remove platform code
>
> .../bindings/arm/cirrus/cirrus,ep9301.yaml | 38 +
> .../bindings/ata/cirrus,ep9312-pata.yaml | 42 +
> .../bindings/dma/cirrus,ep9301-dma-m2m.yaml | 84 ++
> .../bindings/dma/cirrus,ep9301-dma-m2p.yaml | 144 ++
> .../bindings/input/cirrus,ep9307-keypad.yaml | 87 ++
> .../devicetree/bindings/mtd/technologic,nand.yaml | 45 +
> .../devicetree/bindings/net/cirrus,ep9301-eth.yaml | 59 +
> .../devicetree/bindings/pwm/cirrus,ep9301-pwm.yaml | 53 +
> .../bindings/soc/cirrus/cirrus,ep9301-syscon.yaml | 94 ++
> .../bindings/sound/cirrus,ep9301-i2s.yaml | 16 +
> .../devicetree/bindings/spi/cirrus,ep9301-spi.yaml | 70 +
> .../bindings/watchdog/cirrus,ep9301-wdt.yaml | 42 +
> arch/arm/Makefile | 1 -
> arch/arm/boot/dts/cirrus/Makefile | 4 +
> arch/arm/boot/dts/cirrus/ep93xx-bk3.dts | 125 ++
> arch/arm/boot/dts/cirrus/ep93xx-edb9302.dts | 181 +++
> arch/arm/boot/dts/cirrus/ep93xx-ts7250.dts | 145 ++
> arch/arm/boot/dts/cirrus/ep93xx.dtsi | 444 ++++++
> arch/arm/mach-ep93xx/Kconfig | 20 +-
> arch/arm/mach-ep93xx/Makefile | 11 -
> arch/arm/mach-ep93xx/clock.c | 733 ----------
> arch/arm/mach-ep93xx/core.c | 1018 --------------
> arch/arm/mach-ep93xx/dma.c | 114 --
> arch/arm/mach-ep93xx/edb93xx.c | 368 -----
> arch/arm/mach-ep93xx/ep93xx-regs.h | 38 -
> arch/arm/mach-ep93xx/gpio-ep93xx.h | 111 --
> arch/arm/mach-ep93xx/hardware.h | 25 -
> arch/arm/mach-ep93xx/irqs.h | 76 --
> arch/arm/mach-ep93xx/platform.h | 42 -
> arch/arm/mach-ep93xx/soc.h | 212 ---
> arch/arm/mach-ep93xx/timer-ep93xx.c | 143 --
> arch/arm/mach-ep93xx/ts72xx.c | 422 ------
> arch/arm/mach-ep93xx/ts72xx.h | 94 --
> arch/arm/mach-ep93xx/vision_ep9307.c | 321 -----
> drivers/ata/pata_ep93xx.c | 107 +-
> drivers/clk/Kconfig | 8 +
> drivers/clk/Makefile | 1 +
> drivers/clk/clk-ep93xx.c | 846 ++++++++++++
> drivers/dma/ep93xx_dma.c | 287 +++-
> drivers/gpio/gpio-ep93xx.c | 345 ++---
> drivers/input/keyboard/ep93xx_keypad.c | 74 +-
> drivers/mtd/nand/raw/Kconfig | 6 +
> drivers/mtd/nand/raw/Makefile | 1 +
> drivers/mtd/nand/raw/technologic-nand-controller.c | 222 +++
> drivers/net/ethernet/cirrus/ep93xx_eth.c | 63 +-
> drivers/pinctrl/Kconfig | 7 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/pinctrl-ep93xx.c | 1434 ++++++++++++++++++++
> drivers/power/reset/Kconfig | 10 +
> drivers/power/reset/Makefile | 1 +
> drivers/power/reset/ep93xx-restart.c | 84 ++
> drivers/pwm/pwm-ep93xx.c | 26 +-
> drivers/soc/Kconfig | 1 +
> drivers/soc/Makefile | 1 +
> drivers/soc/cirrus/Kconfig | 17 +
> drivers/soc/cirrus/Makefile | 2 +
> drivers/soc/cirrus/soc-ep93xx.c | 252 ++++
> drivers/spi/spi-ep93xx.c | 66 +-
> drivers/watchdog/ep93xx_wdt.c | 8 +
> drivers/watchdog/ts72xx_wdt.c | 8 +
> include/dt-bindings/clock/cirrus,ep9301-syscon.h | 46 +
> include/linux/platform_data/dma-ep93xx.h | 94 --
> include/linux/platform_data/eth-ep93xx.h | 10 -
> include/linux/platform_data/keypad-ep93xx.h | 32 -
> include/linux/platform_data/spi-ep93xx.h | 15 -
> include/linux/soc/cirrus/ep93xx.h | 47 +-
> sound/soc/cirrus/Kconfig | 9 -
> sound/soc/cirrus/Makefile | 4 -
> sound/soc/cirrus/edb93xx.c | 116 --
> sound/soc/cirrus/ep93xx-i2s.c | 19 -
> sound/soc/cirrus/ep93xx-pcm.c | 19 +-
> 71 files changed, 5161 insertions(+), 4550 deletions(-)
> ---
> base-commit: 0c3836482481200ead7b416ca80c68a29cfdaabd
> change-id: 20230605-ep93xx-01c76317e2d2
>
> Best regards,
> --
> Nikita Shubin <nikita.shubin@maquefel.me>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y cirrus/ep93xx-bk3.dtb cirrus/ep93xx-edb9302.dtb cirrus/ep93xx-ts7250.dtb' for 20240715-ep93xx-v11-0-4e924efda795@maquefel.me:
arch/arm/boot/dts/cirrus/ep93xx-edb9302.dtb: /soc/spi@808a0000/codec@0: failed to match any schema with compatible: ['cirrus,cs4271']
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx
2024-07-15 8:38 ` [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx Nikita Shubin via B4 Relay
@ 2024-08-02 7:07 ` Nikita Shubin
2024-08-26 8:33 ` Nikita Shubin
2024-08-28 20:44 ` Stephen Boyd
1 sibling, 1 reply; 12+ messages in thread
From: Nikita Shubin @ 2024-08-02 7:07 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-clk, linux-kernel, mturquette, nikita.shubin,
devnull+nikita.shubin.maquefel.me
Hi Stephen!
Just in case you missed this one in last series update:
Changelog for this patch:
- added devm_ep93xx_clk_hw_register_fixed_rate_parent_data() for
devm_ version of clk_hw_register_fixed_rate_parent_data()
-
s/devm_clk_hw_register_fixed_rate()/devm_ep93xx_clk_hw_register_fixed_r
ate_parent_data()/
- replaced all devm_clk_hw_register_fixed_factor() to
devm_clk_hw_register_fixed_factor_parent_hw() or
devm_clk_hw_register_fixed_factor_index()
- s/devm_clk_hw_register_gate()/devm_clk_hw_register_gate_parent_data()
Stephen - it think that's you was aiming for - to get rid of all
functions that are using const char* parent_name directly instead of
clk_hw or clk_parent_data.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx
2024-08-02 7:07 ` Nikita Shubin
@ 2024-08-26 8:33 ` Nikita Shubin
0 siblings, 0 replies; 12+ messages in thread
From: Nikita Shubin @ 2024-08-26 8:33 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-clk, linux-kernel, mturquette,
devnull+nikita.shubin.maquefel.me, Alexander Sverdlin,
Arnd Bergmann
Hi Stephen,
A gentle reminder on this particular patch, hope you'll have time for
it soon.
On Fri, 2024-08-02 at 10:07 +0300, Nikita Shubin wrote:
> Hi Stephen!
>
> Just in case you missed this one in last series update:
>
> Changelog for this patch:
> - added devm_ep93xx_clk_hw_register_fixed_rate_parent_data() for
> devm_ version of clk_hw_register_fixed_rate_parent_data()
> -
> s/devm_clk_hw_register_fixed_rate()/devm_ep93xx_clk_hw_register_fixed
> _r
> ate_parent_data()/
> - replaced all devm_clk_hw_register_fixed_factor() to
> devm_clk_hw_register_fixed_factor_parent_hw() or
> devm_clk_hw_register_fixed_factor_index()
> -
> s/devm_clk_hw_register_gate()/devm_clk_hw_register_gate_parent_data()
>
> Stephen - it think that's you was aiming for - to get rid of all
> functions that are using const char* parent_name directly instead of
> clk_hw or clk_parent_data.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx
2024-07-15 8:38 ` [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx Nikita Shubin via B4 Relay
2024-08-02 7:07 ` Nikita Shubin
@ 2024-08-28 20:44 ` Stephen Boyd
2024-08-30 9:23 ` Nikita Shubin
1 sibling, 1 reply; 12+ messages in thread
From: Stephen Boyd @ 2024-08-28 20:44 UTC (permalink / raw)
To: Michael Turquette, Nikita Shubin via B4 Relay, nikita.shubin
Cc: linux-kernel, linux-clk
Quoting Nikita Shubin via B4 Relay (2024-07-15 01:38:07)
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 3e9099504fad..234b0a8b7650 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -218,6 +218,14 @@ config COMMON_CLK_EN7523
> This driver provides the fixed clocks and gates present on Airoha
> ARM silicon.
>
> +config COMMON_CLK_EP93XX
> + bool "Clock driver for Cirrus Logic ep93xx SoC"
tristate?
> + depends on ARCH_EP93XX || COMPILE_TEST
> + select MFD_SYSCON
Why is this selecting syscon?
> + select REGMAP
Is this needed either?
> + help
> + This driver supports the SoC clocks on the Cirrus Logic ep93xx.
> +
> config COMMON_CLK_FSL_FLEXSPI
> tristate "Clock driver for FlexSPI on Layerscape SoCs"
> depends on ARCH_LAYERSCAPE || COMPILE_TEST
> diff --git a/drivers/clk/clk-ep93xx.c b/drivers/clk/clk-ep93xx.c
> new file mode 100644
> index 000000000000..bb1cf59a3d47
> --- /dev/null
> +++ b/drivers/clk/clk-ep93xx.c
> @@ -0,0 +1,846 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Clock control for Cirrus EP93xx chips.
> + * Copyright (C) 2021 Nikita Shubin <nikita.shubin@maquefel.me>
> + *
> + * Based on a rewrite of arch/arm/mach-ep93xx/clock.c:
> + * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
> + */
> +#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
> +
> +#include <linux/bits.h>
> +#include <linux/cleanup.h>
> +#include <linux/clk-provider.h>
> +#include <linux/math.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/spinlock.h>
> +
> +#include <linux/soc/cirrus/ep93xx.h>
> +#include <dt-bindings/clock/cirrus,ep9301-syscon.h>
> +
> +#include <asm/div64.h>
[...]
> +
> +static const char adc_divisors[] = { 16, 4 };
These are global symbols in terms of namespace because we're in the
kernel. Please prefix with ep93xx_ to help tags.
> +static const char sclk_divisors[] = { 2, 4 };
> +static const char lrclk_divisors[] = { 32, 64, 128 };
> +
> +struct ep93xx_clk {
> + struct clk_hw hw;
> + u16 idx;
> + u16 reg;
> + u32 mask;
> + u8 bit_idx;
> + u8 shift;
> + u8 width;
> + u8 num_div;
> + const char *div;
> +};
> +
> +struct ep93xx_clk_priv {
> + spinlock_t lock;
> + struct ep93xx_regmap_adev *aux_dev;
> + struct device *dev;
> + void __iomem *base;
> + struct regmap *map;
> + struct clk_hw *fixed[21];
Please make a define for '21'.
> + struct ep93xx_clk reg[];
> +};
[...]
> +
> +static const struct clk_ops ep93xx_div_ops = {
> + .enable = ep93xx_clk_enable,
> + .disable = ep93xx_clk_disable,
> + .is_enabled = ep93xx_clk_is_enabled,
> + .recalc_rate = ep93xx_div_recalc_rate,
> + .round_rate = ep93xx_div_round_rate,
> + .set_rate = ep93xx_div_set_rate,
> +};
> +
> +static int clk_hw_register_div(struct ep93xx_clk *clk,
Please call this something like ep93xx_register_div(). It doesn't take a
clk_hw pointer so the clk_hw prefix doesn't make sense. This same
comment applies to other clk_hw prefixed functions in this file.
> + const char *name,
> + struct clk_parent_data *parent_data,
const?
> + unsigned int reg,
> + u8 enable_bit,
> + u8 shift,
> + u8 width,
> + const char *clk_divisors,
> + u8 num_div)
> +{
> + struct ep93xx_clk_priv *priv = ep93xx_priv_from(clk);
> + struct clk_init_data init = { };
> +
> + init.name = name;
> + init.ops = &ep93xx_div_ops;
> + init.flags = 0;
> + init.parent_data = parent_data;
> + init.num_parents = 1;
> +
> + clk->reg = reg;
> + clk->bit_idx = enable_bit;
> + clk->mask = GENMASK(shift + width - 1, shift);
> + clk->shift = shift;
> + clk->div = clk_divisors;
> + clk->num_div = num_div;
> + clk->hw.init = &init;
> +
> + return devm_clk_hw_register(priv->dev, &clk->hw);
> +}
> +
> +struct ep93xx_gate {
> + unsigned int idx;
> + unsigned int bit;
> + const char *name;
> +};
> +
> +static const struct ep93xx_gate ep93xx_uarts[] = {
> + { EP93XX_CLK_UART1, EP93XX_SYSCON_DEVCFG_U1EN, "uart1" },
> + { EP93XX_CLK_UART2, EP93XX_SYSCON_DEVCFG_U2EN, "uart2" },
> + { EP93XX_CLK_UART3, EP93XX_SYSCON_DEVCFG_U3EN, "uart3" },
> +};
> +
> +static int ep93xx_uart_clock_init(struct ep93xx_clk_priv *priv)
> +{
> + struct clk_parent_data parent_data = { };
> + unsigned int i, idx, ret, clk_uart_div;
> + struct ep93xx_clk *clk;
> + u32 val;
> +
> + regmap_read(priv->map, EP93XX_SYSCON_PWRCNT, &val);
> + if (val & EP93XX_SYSCON_PWRCNT_UARTBAUD)
> + clk_uart_div = 1;
> + else
> + clk_uart_div = 2;
> +
> + priv->fixed[EP93XX_CLK_UART] =
> + clk_hw_register_fixed_factor(NULL, "uart", "xtali", 0, 1, clk_uart_div);
Pass a device instead of NULL. Don't use string names for parent ^
> + parent_data.hw = priv->fixed[EP93XX_CLK_UART];
> +
> + /* parenting uart gate clocks to uart clock */
> + for (i = 0; i < ARRAY_SIZE(ep93xx_uarts); i++) {
> + idx = ep93xx_uarts[i].idx - EP93XX_CLK_UART1;
> + clk = &priv->reg[idx];
> + clk->idx = idx;
> + ret = ep93xx_clk_register_gate(clk,
> + ep93xx_uarts[i].name,
> + &parent_data, CLK_SET_RATE_PARENT,
> + EP93XX_SYSCON_DEVCFG,
> + ep93xx_uarts[i].bit);
> + if (ret)
> + return dev_err_probe(priv->dev, ret,
> + "failed to register uart[%d] clock\n", i);
> + }
> +
> + return 0;
> +}
> +
> +static const struct ep93xx_gate ep93xx_dmas[] = {
> + { EP93XX_CLK_M2M0, EP93XX_SYSCON_PWRCNT_DMA_M2M0, "m2m0" },
> + { EP93XX_CLK_M2M1, EP93XX_SYSCON_PWRCNT_DMA_M2M1, "m2m1" },
> + { EP93XX_CLK_M2P0, EP93XX_SYSCON_PWRCNT_DMA_M2P0, "m2p0" },
> + { EP93XX_CLK_M2P1, EP93XX_SYSCON_PWRCNT_DMA_M2P1, "m2p1" },
> + { EP93XX_CLK_M2P2, EP93XX_SYSCON_PWRCNT_DMA_M2P2, "m2p2" },
> + { EP93XX_CLK_M2P3, EP93XX_SYSCON_PWRCNT_DMA_M2P3, "m2p3" },
> + { EP93XX_CLK_M2P4, EP93XX_SYSCON_PWRCNT_DMA_M2P4, "m2p4" },
> + { EP93XX_CLK_M2P5, EP93XX_SYSCON_PWRCNT_DMA_M2P5, "m2p5" },
> + { EP93XX_CLK_M2P6, EP93XX_SYSCON_PWRCNT_DMA_M2P6, "m2p6" },
> + { EP93XX_CLK_M2P7, EP93XX_SYSCON_PWRCNT_DMA_M2P7, "m2p7" },
> + { EP93XX_CLK_M2P8, EP93XX_SYSCON_PWRCNT_DMA_M2P8, "m2p8" },
> + { EP93XX_CLK_M2P9, EP93XX_SYSCON_PWRCNT_DMA_M2P9, "m2p9" },
> +};
> +
> +static int ep93xx_dma_clock_init(struct ep93xx_clk_priv *priv)
> +{
> + struct clk_parent_data parent_data = { };
> + unsigned int i, idx;
> +
> + parent_data.hw = priv->fixed[EP93XX_CLK_HCLK];
> + for (i = 0; i < ARRAY_SIZE(ep93xx_dmas); i++) {
> + idx = ep93xx_dmas[i].idx;
> + priv->fixed[idx] = devm_clk_hw_register_gate_parent_data(priv->dev,
> + ep93xx_dmas[i].name,
> + &parent_data, 0,
> + priv->base + EP93XX_SYSCON_PWRCNT,
> + ep93xx_dmas[i].bit,
> + 0,
> + &priv->lock);
> + if (IS_ERR(priv->fixed[idx]))
> + return PTR_ERR(priv->fixed[idx]);
> + }
> +
> + return 0;
> +}
> +
> +static struct clk_hw *of_clk_ep93xx_get(struct of_phandle_args *clkspec, void *data)
> +{
> + struct ep93xx_clk_priv *priv = data;
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx < EP93XX_CLK_UART1)
> + return priv->fixed[idx];
> +
> + if (idx <= EP93XX_CLK_I2S_LRCLK)
> + return &priv->reg[idx - EP93XX_CLK_UART1].hw;
> +
> + return ERR_PTR(-EINVAL);
> +}
> +
> +/*
> + * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
> + */
> +static unsigned long calc_pll_rate(u64 rate, u32 config_word)
> +{
> + rate *= ((config_word >> 11) & GENMASK(4, 0)) + 1; /* X1FBD */
> + rate *= ((config_word >> 5) & GENMASK(5, 0)) + 1; /* X2FBD */
> + do_div(rate, (config_word & GENMASK(4, 0)) + 1); /* X2IPD */
> + rate >>= (config_word >> 16) & GENMASK(1, 0); /* PS */
> +
> + return rate;
> +}
> +
> +#define devm_ep93xx_clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, fixed_rate) \
> + __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
> + (parent_data), (flags), (fixed_rate), 0, 0, true)
Is this to workaround a missing devm_clk_hw_register_fixed_rate_parent_data() macro?
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx
2024-08-28 20:44 ` Stephen Boyd
@ 2024-08-30 9:23 ` Nikita Shubin
2024-08-30 22:27 ` Stephen Boyd
0 siblings, 1 reply; 12+ messages in thread
From: Nikita Shubin @ 2024-08-30 9:23 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Nikita Shubin via B4 Relay
Cc: linux-kernel, linux-clk
Hello Stephen!
On Wed, 2024-08-28 at 13:44 -0700, Stephen Boyd wrote:
> Quoting Nikita Shubin via B4 Relay (2024-07-15 01:38:07)
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index 3e9099504fad..234b0a8b7650 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -218,6 +218,14 @@ config COMMON_CLK_EN7523
> > This driver provides the fixed clocks and gates present
> > on Airoha
> > ARM silicon.
> >
> > +config COMMON_CLK_EP93XX
> > + bool "Clock driver for Cirrus Logic ep93xx SoC"
>
> tristate?
>
> > + depends on ARCH_EP93XX || COMPILE_TEST
> > + select MFD_SYSCON
>
> Why is this selecting syscon?
>
> > + select REGMAP
>
> Is this needed either?
Indeed REGMAP is selected by COMMON_CLK, MFD_SYSCON not required, but
it needs AUXILIARY_BUS.
> > +#define devm_ep93xx_clk_hw_register_fixed_rate_parent_data(dev,
> > name, parent_data, flags, fixed_rate) \
> > + __clk_hw_register_fixed_rate((dev), NULL, (name), NULL,
> > NULL, \
> > + (parent_data), (flags),
> > (fixed_rate), 0, 0, true)
>
> Is this to workaround a missing
> devm_clk_hw_register_fixed_rate_parent_data() macro?
Yes, if it's okay - i'll fire next revision, all other comments are
acknowledged.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx
2024-08-30 9:23 ` Nikita Shubin
@ 2024-08-30 22:27 ` Stephen Boyd
2024-09-02 13:31 ` Nikita Shubin
0 siblings, 1 reply; 12+ messages in thread
From: Stephen Boyd @ 2024-08-30 22:27 UTC (permalink / raw)
To: Michael Turquette, Nikita Shubin, Nikita Shubin via B4 Relay
Cc: linux-kernel, linux-clk
Quoting Nikita Shubin (2024-08-30 02:23:12)
> Hello Stephen!
>
> On Wed, 2024-08-28 at 13:44 -0700, Stephen Boyd wrote:
> > Quoting Nikita Shubin via B4 Relay (2024-07-15 01:38:07)
> > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > > index 3e9099504fad..234b0a8b7650 100644
> > > --- a/drivers/clk/Kconfig
> > > +++ b/drivers/clk/Kconfig
> > > @@ -218,6 +218,14 @@ config COMMON_CLK_EN7523
> > > This driver provides the fixed clocks and gates present
> > > on Airoha
> > > ARM silicon.
> > >
> > > +config COMMON_CLK_EP93XX
> > > + bool "Clock driver for Cirrus Logic ep93xx SoC"
> >
> > tristate?
> >
> > > + depends on ARCH_EP93XX || COMPILE_TEST
> > > + select MFD_SYSCON
> >
> > Why is this selecting syscon?
> >
> > > + select REGMAP
> >
> > Is this needed either?
>
> Indeed REGMAP is selected by COMMON_CLK, MFD_SYSCON not required, but
> it needs AUXILIARY_BUS.
I don't see REGMAP selected by COMMON_CLK. Did I miss something?
>
> > > +#define devm_ep93xx_clk_hw_register_fixed_rate_parent_data(dev,
> > > name, parent_data, flags, fixed_rate) \
> > > + __clk_hw_register_fixed_rate((dev), NULL, (name), NULL,
> > > NULL, \
> > > + (parent_data), (flags),
> > > (fixed_rate), 0, 0, true)
> >
> > Is this to workaround a missing
> > devm_clk_hw_register_fixed_rate_parent_data() macro?
>
> Yes, if it's okay - i'll fire next revision, all other comments are
> acknowledged.
>
Can you add the macro so others can use it in another patch?
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx
2024-08-30 22:27 ` Stephen Boyd
@ 2024-09-02 13:31 ` Nikita Shubin
2024-09-05 20:50 ` Stephen Boyd
0 siblings, 1 reply; 12+ messages in thread
From: Nikita Shubin @ 2024-09-02 13:31 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Nikita Shubin via B4 Relay
Cc: linux-kernel, linux-clk
On Fri, 2024-08-30 at 15:27 -0700, Stephen Boyd wrote:
> Quoting Nikita Shubin (2024-08-30 02:23:12)
> > Hello Stephen!
> >
> > On Wed, 2024-08-28 at 13:44 -0700, Stephen Boyd wrote:
> > > Quoting Nikita Shubin via B4 Relay (2024-07-15 01:38:07)
> > > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > > > index 3e9099504fad..234b0a8b7650 100644
> > > > --- a/drivers/clk/Kconfig
> > > > +++ b/drivers/clk/Kconfig
> > > > @@ -218,6 +218,14 @@ config COMMON_CLK_EN7523
> > > > This driver provides the fixed clocks and gates
> > > > present
> > > > on Airoha
> > > > ARM silicon.
> > > >
> > > > +config COMMON_CLK_EP93XX
> > > > + bool "Clock driver for Cirrus Logic ep93xx SoC"
> > >
> > > tristate?
> > >
> > > > + depends on ARCH_EP93XX || COMPILE_TEST
> > > > + select MFD_SYSCON
> > >
> > > Why is this selecting syscon?
> > >
> > > > + select REGMAP
> > >
> > > Is this needed either?
> >
> > Indeed REGMAP is selected by COMMON_CLK, MFD_SYSCON not required,
> > but
> > it needs AUXILIARY_BUS.
>
> I don't see REGMAP selected by COMMON_CLK. Did I miss something?
Indeed REGMAP is selected by COMMON_CLK_MESON_REGMAP not COMMON_CLK on
make tinyconfig + COMPILE_TEST.
Then we require REGMAP because we are using regmap_read() in clk
driver.
>
> >
> > > > +#define
> > > > devm_ep93xx_clk_hw_register_fixed_rate_parent_data(dev,
> > > > name, parent_data, flags, fixed_rate) \
> > > > + __clk_hw_register_fixed_rate((dev), NULL, (name), NULL,
> > > > NULL, \
> > > > + (parent_data), (flags),
> > > > (fixed_rate), 0, 0, true)
> > >
> > > Is this to workaround a missing
> > > devm_clk_hw_register_fixed_rate_parent_data() macro?
> >
> > Yes, if it's okay - i'll fire next revision, all other comments are
> > acknowledged.
> >
>
> Can you add the macro so others can use it in another patch?
Sure.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx
2024-09-02 13:31 ` Nikita Shubin
@ 2024-09-05 20:50 ` Stephen Boyd
2024-09-06 12:08 ` Nikita Shubin
0 siblings, 1 reply; 12+ messages in thread
From: Stephen Boyd @ 2024-09-05 20:50 UTC (permalink / raw)
To: Michael Turquette, Nikita Shubin, Nikita Shubin via B4 Relay
Cc: linux-kernel, linux-clk
Quoting Nikita Shubin (2024-09-02 06:31:59)
> On Fri, 2024-08-30 at 15:27 -0700, Stephen Boyd wrote:
> > Quoting Nikita Shubin (2024-08-30 02:23:12)
> > >
> > > Indeed REGMAP is selected by COMMON_CLK, MFD_SYSCON not required,
> > > but
> > > it needs AUXILIARY_BUS.
> >
> > I don't see REGMAP selected by COMMON_CLK. Did I miss something?
>
> Indeed REGMAP is selected by COMMON_CLK_MESON_REGMAP not COMMON_CLK on
> make tinyconfig + COMPILE_TEST.
The meson driver isn't used here?
>
> Then we require REGMAP because we are using regmap_read() in clk
> driver.
I think you're supposed to select REGMAP_<BUS> config option, not the
toplevel REGMAP option. For example, if you're using mmio, then select
REGMAP_MMIO.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx
2024-09-05 20:50 ` Stephen Boyd
@ 2024-09-06 12:08 ` Nikita Shubin
0 siblings, 0 replies; 12+ messages in thread
From: Nikita Shubin @ 2024-09-06 12:08 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Nikita Shubin via B4 Relay
Cc: linux-kernel, linux-clk
On Thu, 2024-09-05 at 13:50 -0700, Stephen Boyd wrote:
> Quoting Nikita Shubin (2024-09-02 06:31:59)
> > On Fri, 2024-08-30 at 15:27 -0700, Stephen Boyd wrote:
> > > Quoting Nikita Shubin (2024-08-30 02:23:12)
> > > >
> > > > Indeed REGMAP is selected by COMMON_CLK, MFD_SYSCON not
> > > > required,
> > > > but
> > > > it needs AUXILIARY_BUS.
> > >
> > > I don't see REGMAP selected by COMMON_CLK. Did I miss something?
> >
> > Indeed REGMAP is selected by COMMON_CLK_MESON_REGMAP not COMMON_CLK
> > on
> > make tinyconfig + COMPILE_TEST.
>
> The meson driver isn't used here?
This is purely from ARCH=arm make tinyconfig - i use it only with
COMPILE_TEST for testing.
>
> >
> > Then we require REGMAP because we are using regmap_read() in clk
> > driver.
>
> I think you're supposed to select REGMAP_<BUS> config option, not the
> toplevel REGMAP option. For example, if you're using mmio, then
> select
> REGMAP_MMIO.
Yes this makes sense, REGMAP_MMIO it is.
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2024-09-06 12:08 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-07-15 8:38 [PATCH v11 00/38] ep93xx device tree conversion Nikita Shubin via B4 Relay
2024-07-15 8:38 ` [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx Nikita Shubin via B4 Relay
2024-08-02 7:07 ` Nikita Shubin
2024-08-26 8:33 ` Nikita Shubin
2024-08-28 20:44 ` Stephen Boyd
2024-08-30 9:23 ` Nikita Shubin
2024-08-30 22:27 ` Stephen Boyd
2024-09-02 13:31 ` Nikita Shubin
2024-09-05 20:50 ` Stephen Boyd
2024-09-06 12:08 ` Nikita Shubin
2024-07-15 8:38 ` [PATCH v11 06/38] dt-bindings: soc: Add " Nikita Shubin via B4 Relay
2024-07-15 12:12 ` [PATCH v11 00/38] ep93xx device tree conversion Rob Herring (Arm)
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