From: 손신 <shin.son@samsung.com>
To: "'Krzysztof Kozlowski'" <krzk@kernel.org>,
"'Sylwester Nawrocki'" <s.nawrocki@samsung.com>,
"'Chanwoo Choi'" <cw00.choi@samsung.com>,
"'Alim Akhtar'" <alim.akhtar@samsung.com>,
"'Michael Turquette'" <mturquette@baylibre.com>,
"'Stephen Boyd'" <sboyd@kernel.org>,
"'Rob Herring'" <robh@kernel.org>,
"'Conor Dooley'" <conor+dt@kernel.org>,
"'Sunyeal Hong'" <sunyeal.hong@samsung.com>
Cc: <linux-samsung-soc@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 2/3] clk: samsung: exynosautov920: add cpucl1/2 clock support
Date: Mon, 28 Apr 2025 19:47:48 +0900 [thread overview]
Message-ID: <02d901dbb82a$fb7493a0$f25dbae0$@samsung.com> (raw)
In-Reply-To: <a3438b8b-0fd2-454f-a539-39aa7cfcd57b@kernel.org>
Hello, Krzysztof Kozlowski.
> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:krzk@kernel.org]
> Sent: Monday, April 28, 2025 6:15 PM
> To: Shin Son <shin.son@samsung.com>; Sylwester Nawrocki
> <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob Herring
> <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Sunyeal Hong
> <sunyeal.hong@samsung.com>
> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH 2/3] clk: samsung: exynosautov920: add cpucl1/2 clock
> support
>
> On 28/04/2025 10:47, Shin Son wrote:
> > Register compatible and cmu_info data to support clock CPUCL1/2 (CPU
> > Cluster 1 and CPU Cluster 2), these provide clock for
> > CPUCL1/2_SWTICH/CLUSTER.
> >
> > These clocks are required early during boot for the CPUs, so they are
> > declared using CLK_OF_DECLARE instead of being registered through a
> > platform driver.
> >
> > Signed-off-by: Shin Son <shin.son@samsung.com>
> > ---
> > drivers/clk/samsung/clk-exynosautov920.c | 208
> > ++++++++++++++++++++++-
> > 1 file changed, 207 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/samsung/clk-exynosautov920.c
> > b/drivers/clk/samsung/clk-exynosautov920.c
> > index 8021e0912e50..f8168eed4a66 100644
> > --- a/drivers/clk/samsung/clk-exynosautov920.c
> > +++ b/drivers/clk/samsung/clk-exynosautov920.c
> > @@ -18,7 +18,9 @@
> >
> > /* NOTE: Must be equal to the last clock ID increased by one */
> > #define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
> > -#define CLKS_NR_CPUCL0 (CLK_DOUT_CLUSTER0_PERIPHCLK + 1)
> > +#define CLKS_NR_CPUCL0 (CLK_DOUT_CPUCL0_NOCP + 1)
>
>
> You just added that line a week ago and it is already incorrect? Then it
> needs patch on its own explaining what are you fixing.
>
>
> Best regards,
> Krzysztof
Understood. I will separate the fix into its own patch and resend it.
Best regards,
Shin Son
next prev parent reply other threads:[~2025-04-28 10:47 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20250428084728epcas2p486ddfccc41bfba9830bde544b6c292e3@epcas2p4.samsung.com>
2025-04-28 8:47 ` [PATCH 0/3] add CPUCL1/2 clock support for exynosauto v920 SoC Shin Son
2025-04-28 8:47 ` [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions Shin Son
2025-04-28 9:13 ` Krzysztof Kozlowski
2025-04-28 10:41 ` 손신
2025-04-28 8:47 ` [PATCH 2/3] clk: samsung: exynosautov920: add cpucl1/2 clock support Shin Son
2025-04-28 9:14 ` Krzysztof Kozlowski
2025-04-28 10:47 ` 손신 [this message]
2025-04-28 8:47 ` [PATCH 3/3] arm64: dts: exynosautov920: add cpucl1/2 clock DT nodes Shin Son
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