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Fri, 31 Jul 2026 10:08:03 +0000 (GMT) From: "Raghav Sharma" To: "'Krzysztof Kozlowski'" , , , , , , , , , Cc: , , , , , , , , In-Reply-To: <3ccaa869-c0cb-4708-adc6-f01f7b4412ac@kernel.org> Subject: RE: [PATCH 06/13] clk: samsung: exynos8855: add block peris clock support Date: Fri, 31 Jul 2026 15:38:01 +0530 Message-ID: <04b301dd20d4$7b047c30$710d7490$@samsung.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQIRARWKMB8/axP+0I5R2y9G0OYjygG4VZRiAgpYPWACoDz/R7XsV2sQ Content-Language: en-us X-CMS-MailID: 20260731100806epcas5p4e3e2518a0769b38a982e27704eab3711 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260728115305epcas5p4394f65825a0a04aa7d2bd5068507e8ca References: <20260728121111.2077860-1-raghav.s@samsung.com> <20260728121111.2077860-7-raghav.s@samsung.com> <3ccaa869-c0cb-4708-adc6-f01f7b4412ac@kernel.org> > -----Original Message----- > From: Krzysztof Kozlowski > Sent: Tuesday, July 28, 2026 5:31 PM > To: raghav.s ; s.nawrocki=40samsung.com; > cw00.choi=40samsung.com; peter.griffin=40linaro.org; > alim.akhtar=40samsung.com; mturquette=40baylibre.com; sboyd=40kernel.org; > bmasney=40redhat.com; robh=40kernel.org; conor+dt=40kernel.org > Cc: linux-samsung-soc=40vger.kernel.org; linux-clk=40vger.kernel.org; > devicetree=40vger.kernel.org; linux-arm-kernel=40lists.infradead.org; lin= ux- > kernel=40vger.kernel.org; hajun.sung=40samsung.com; > is.gandhi=40samsung.com; ts.amit=40samsung.com; > pokala.reddy=40samsung.com > Subject: Re: =5BPATCH 06/13=5D clk: samsung: exynos8855: add block peris = clock > support >=20 > On 28/07/2026 14:11, raghav.s wrote: > > Register compatible and cmu_info data to support clocks. > > CMU_PERIS, this provides clocks for PERIS > > > > Signed-off-by: raghav.s > > --- > > drivers/clk/samsung/clk-exynos8855.c =7C 117 > > ++++++++++++++++++++++++++- > > 1 file changed, 114 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/clk/samsung/clk-exynos8855.c > > b/drivers/clk/samsung/clk-exynos8855.c > > index 93528f0077a4..40745f04be0c 100644 > > --- a/drivers/clk/samsung/clk-exynos8855.c > > +++ b/drivers/clk/samsung/clk-exynos8855.c > > =40=40 -17,8 +17,9 =40=40 > > =23include =22clk-exynos-arm64.h=22 > > > > /* NOTE: Must be equal to the last clock ID increased by one */ > > -=23define CLKS_NR_TOP (FOUT_MMC_PLL_DIV2 + 1) >=20 > You just added this line, so changing this is odd. Are your patches corre= ctly > split? >=20 >=20 > Best regards, > Krzysztof Hi Krzysztof We will re-check the patches' order Thanks for your reply Regards Raghav