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Wed, 30 Jul 2025 09:50:17 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56U9oGCB023010 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Jul 2025 09:50:16 GMT Received: from [10.218.22.7] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 30 Jul 2025 02:50:10 -0700 Message-ID: <0a6baf09-b1b8-4573-b53d-574838efd9ec@quicinc.com> Date: Wed, 30 Jul 2025 15:20:06 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 00/18] clk: qcom: Add support to attach multiple power domains in cc probe To: Neil Armstrong , Bjorn Andersson , Michael Turquette , "Stephen Boyd" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Vladimir Zapolskiy , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Bryan O'Donoghue , Dmitry Baryshkov , Konrad Dybcio References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> <8e56e1a8-7b26-44df-ad57-e2092cb5c9ab@linaro.org> Content-Language: en-US From: Jagadeesh Kona In-Reply-To: <8e56e1a8-7b26-44df-ad57-e2092cb5c9ab@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=LsaSymdc c=1 sm=1 tr=0 ts=6889ead9 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=jnxDy751yvgSPKbTsG4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzMwMDA2OCBTYWx0ZWRfX7CShTMhBrB6M GGQK00dpo73ItEVCj2y3UrzBn3CX00Gnvn8D7jLwcfKpq8BcHeFOJsHrZDorCIeS/JYheYJj4lG eT43xbGnU4iS6r4xn25zR842d6e7YwXjyknplJ358yhh2VochV0Kg1+hs2VA6ZLYPw2vDJRXP55 PI85ZOfo7+X10+e4YpluRzlp9lciJQWQCsjrjKxoyqw4/nUqIxRHDadw/kSe8teADiQO8gTuCVj b1olYUe7CZMkyxnPczpu+S7WSxOM48GkQzzZrbEtlU4bw14AvnMJJkKeyetnz2+93nTzfX5fXsU P6N3ynnMdEr5syclCyxPikVqheZACs42ZQIZUfBUmovIvwqs3kE2lneXj2BIPveDBZ3rOBV1vnC VR8MRmb4La7/s0GRBl+t64kpeaPVJj01Fj7IT5AZ0s5VwxeZcNUxU8h6tmIm0+qomv/BQ9VN X-Proofpoint-ORIG-GUID: hDajRQOfgDclSVB4mzJABSjYdyXqo_zy X-Proofpoint-GUID: hDajRQOfgDclSVB4mzJABSjYdyXqo_zy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-30_04,2025-07-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 mlxlogscore=999 spamscore=0 phishscore=0 suspectscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507300068 On 7/29/2025 8:19 PM, neil.armstrong@linaro.org wrote: > Hi, > > On 30/05/2025 15:20, Jagadeesh Kona wrote: >> In recent QCOM chipsets, PLLs require more than one power domain to be >> kept ON to configure the PLL. But the current code doesn't enable all >> the required power domains while configuring the PLLs, this leads to >> functional issues due to suboptimal settings of PLLs. >> >> To address this, add support for handling runtime power management, >> configuring plls and enabling critical clocks from qcom_cc_really_probe. >> The clock controller can specify PLLs, critical clocks, and runtime PM >> requirements using the descriptor data. The code in qcom_cc_really_probe() >> ensures all necessary power domains are enabled before configuring PLLs >> or critical clocks. >> >> This series fixes the below warning reported in SM8550 venus testing due >> to video_cc_pll0 not properly getting configured during videocc probe >> >> [   46.535132] Lucid PLL latch failed. Output may be unstable! >> >> The patch adding support to configure the PLLs from common code is >> picked from below series and updated it. >> https://lore.kernel.org/all/20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com/ >> >> This series is dependent on bindings patch in below Vladimir's series, hence >> included the Vladimir's series patches also in this series and updated them. >> https://lore.kernel.org/all/20250303225521.1780611-1-vladimir.zapolskiy@linaro.org/ > > > Could you re-spin patches 13 to 18 to fix the bindings checks ? > I tried applying the patches 13-18 on latest linux-next tip and I see they are applied properly without any conflicts. Bjorn, can you please help to pick the patches 13-18 to fix the bindings checks[1]. Please let me know if anything needed from me. [1]: https://lore.kernel.org/oe-kbuild-all/453bd020-8124-4a7d-8d0f-8180d38f1ebc@quicinc.com/#t Thanks, Jagadeesh > Thanks, > Neil > > >