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Tue, 08 Oct 2024 10:15:34 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 498AFXE4009912 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 8 Oct 2024 10:15:33 GMT Received: from [10.50.47.90] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 8 Oct 2024 03:15:26 -0700 Message-ID: <0aa2599b-a77c-428d-a475-0be63e49d0ca@quicinc.com> Date: Tue, 8 Oct 2024 15:45:23 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V3 2/7] dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding To: Krzysztof Kozlowski , , , , , , , , , , , , , , , , , , , , , CC: References: <20241004102342.2414317-1-quic_srichara@quicinc.com> <20241004102342.2414317-3-quic_srichara@quicinc.com> Content-Language: en-US From: Sricharan Ramabadhran In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: YL0vpv9p-5X-LFf5aMjhRP2uguTED-sN X-Proofpoint-GUID: YL0vpv9p-5X-LFf5aMjhRP2uguTED-sN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 suspectscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410080067 On 10/6/2024 2:09 PM, Krzysztof Kozlowski wrote: > On 04/10/2024 12:23, Sricharan R wrote: > >> maintainers: >> - Bjorn Andersson >> >> description: | >> Qualcomm global clock control module provides the clocks, resets and power >> - domains on IPQ5332. >> + domains on IPQ5332 and IPQ5424. >> >> - See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h >> - >> -allOf: >> - - $ref: qcom,gcc.yaml# >> + See also:: > > s/::/:/ > >> + include/dt-bindings/clock/qcom,gcc-ipq5332.h >> + include/dt-bindings/clock/qcom,gcc-ipq5424.h >> >> properties: >> compatible: >> - const: qcom,ipq5332-gcc >> + enum: >> + - qcom,ipq5332-gcc >> + - qcom,ipq5424-gcc >> >> clocks: >> + minItems: 5 >> items: >> - description: Board XO clock source >> - description: Sleep clock source >> - description: PCIE 2lane PHY pipe clock source >> - description: PCIE 2lane x1 PHY pipe clock source (For second lane) >> + - description: PCIE 2-lane PHY2 pipe clock source >> + - description: PCIE 2-lane PHY3 pipe clock source >> - description: USB PCIE wrapper pipe clock source > > Why do you change fifth clock on ipq5332? > > Please test your patches - change DTS for ipq5332 and provide PCIE > 2-lane PHY2 there. Ho ok, these 2 additional clocks are required only for IPQ5424. I ran the check_dtbs/dt_binding_check for both IPQ5332/IPQ5424. Agree that fifth clock should not be changed in default. So, would it be fine to add these 2 clocks in the end and re-send ? Regards, Sricharan