From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <heiko@sntech.de>
From: Heiko Stuebner <heiko@sntech.de>
To: Xing Zheng <zhengxing@rock-chips.com>
Cc: linux-rockchip@lists.infradead.org, dianders@google.com, zyw@rock-chips.com, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@codeaurora.org>, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: rockchip: add 533.25MHz to rk3399 clock rates table
Date: Fri, 21 Oct 2016 09:47:29 +0200
Message-ID: <10119527.9b3VbjvMOc@phil>
In-Reply-To: <1477022620-8143-1-git-send-email-zhengxing@rock-chips.com>
References: <1477022620-8143-1-git-send-email-zhengxing@rock-chips.com>
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List-ID: <linux-clk.vger.kernel.org>

Am Freitag, 21. Oktober 2016, 12:03:40 CEST schrieb Xing Zheng:
> We need to get the accurate 533.25MHz for the DP display.
> 
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

applied to my clk-branch for 4.10


Thanks
Heiko