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From: "Benoît Monin" <benoit.monin@bootlin.com>
To: "Conor Dooley" <conor+dt@kernel.org>,
	"Gregory CLEMENT" <gregory.clement@bootlin.com>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Rob Herring" <robh@kernel.org>,
	"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
	"Théo Lebrun" <theo.lebrun@bootlin.com>,
	"Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>,
	"Stephen Boyd" <sboyd@kernel.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	Tawfik Bayouk <tawfik.bayouk@mobileye.com>,
	Sari Khoury <sari.khoury@mobileye.com>
Subject: Re: [PATCH 07/19] clk: fixed-factor: add clk_hw_register_fixed_factor_with_accuracy
Date: Thu, 25 Sep 2025 13:47:03 +0200	[thread overview]
Message-ID: <10352124.tdPhlSkOF2@benoit.monin> (raw)
In-Reply-To: <175834529869.4354.196538790945051595@lazor>

On Saturday, 20 September 2025 at 07:14:58 CEST, Stephen Boyd wrote:
> Quoting Benoît Monin (2025-09-03 05:47:14)
> > diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
> > index e62ae8794d445f685156276d5135448f340fca3f..7c76658a725f9b268da2485769979e5ba213d25b 100644
> > --- a/drivers/clk/clk-fixed-factor.c
> > +++ b/drivers/clk/clk-fixed-factor.c
> > @@ -217,6 +217,18 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
> >  }
> >  EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
> >  
> > +struct clk_hw *clk_hw_register_fixed_factor_with_accuracy(struct device *dev,
> > +               const char *name, const char *parent_name, unsigned long flags,
> > +               unsigned int mult, unsigned int div, unsigned long acc)
> > +{
> > +       const struct clk_parent_data pdata = { .index = -1 };
> 
> This is wrong. We're passing parent data and also setting the parent
> name with a string the original way. Do you have a parent?
> 
This is caused by the handling of the init struct in
__clk_hw_register_fixed_factor(). In particular num_parents
is always set to 1:
	...
	if (parent_name)
		init.parent_names = &parent_name;
	else if (parent_hw)
		init.parent_hws = &parent_hw;
	else
		init.parent_data = pdata;
	init.num_parents = 1;

We could adopt the same approach as in __clk_hw_register_divider() to set
num_parents only when one is passed-in, so the invalid pdata could be
dropped:
	...
	init.parent_names = parent_name ? &parent_name : NULL;
	init.parent_hws = parent_hw ? &parent_hw : NULL;
	init.parent_data = parent_data;
	if (parent_name || parent_hw || parent_data)
		init.num_parents = 1;
	else
		init.num_parents = 0;

But doing so would change what happens when a fixed factor is registered
with an invalid parent, for example calling clk_hw_register_fixed_factor()
with a NULL parent_name. Currently we get an orphaned clock (seen in
clk_orphan_summary) since it is created with an invalid parent. With the
change it would register without zero parent but not be considered orphaned
(a "root" clock).

Do you think it is okay to make this change?

> > +
> > +       return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL,
> > +                                             &pdata, flags, mult, div, acc,
> > +                                             CLK_FIXED_FACTOR_FIXED_ACCURACY, false);
> > +}
> > +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_with_accuracy);
> 
> There are a handful of these wrappers now. Can we have one function that
> takes all possibilities and then static inline functions that call one
> exported function?  We can pass some structs to that function to keep
> the argument count "low", so those structs live on the stack for a short
> time.
> 
Yes, we could use the same approach as clk-divider, clk-gate and others.
Export the __clk_hw_register_fixed_factor() symbol in the header and have
macros / inline functions.

> > +
> >  struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
> >                 struct device_node *np, const char *name, const char *fw_name,
> >                 unsigned long flags, unsigned int mult, unsigned int div)
> 


Best regards,
-- 
Benoît Monin, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com




  reply	other threads:[~2025-09-25 11:47 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-03 12:47 [PATCH 00/19] Add clock and reset support for Mobileye eyeQ7H Benoît Monin
2025-09-03 12:47 ` [PATCH 01/19] dt-bindings: soc: mobileye: rename to eyeq-olb.yaml Benoît Monin
2025-09-04  9:20   ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 02/19] dt-bindings: clock: mobileye: rename to eyeq-clk.h Benoît Monin
2025-09-04  9:24   ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 03/19] dt-bindings: soc: mobileye: add eyeQ7H compatibles Benoît Monin
2025-09-04  9:22   ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 04/19] dt-bindings: clock: mobileye: add eyeQ7H clock indexes Benoît Monin
2025-09-04  9:23   ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 05/19] dt-bindings: reset: add Mobileye eyeQ Benoît Monin
2025-09-04  9:25   ` Krzysztof Kozlowski
2025-09-03 12:47 ` [PATCH 06/19] reset: eyeq: add eyeQ7H compatibles Benoît Monin
2025-09-03 12:47 ` [PATCH 07/19] clk: fixed-factor: add clk_hw_register_fixed_factor_with_accuracy Benoît Monin
2025-09-20  5:14   ` Stephen Boyd
2025-09-25 11:47     ` Benoît Monin [this message]
2025-09-03 12:47 ` [PATCH 08/19] clk: divider: check divider validity for CLK_DIVIDER_EVEN_INTEGERS Benoît Monin
2025-09-20  5:15   ` Stephen Boyd
2025-09-25 11:51     ` Benoît Monin
2025-09-03 12:47 ` [PATCH 09/19] clk: divider: check validity of flags when a table is provided Benoît Monin
2025-09-20  5:24   ` Stephen Boyd
2025-09-25 11:55     ` Benoît Monin
2025-09-03 12:47 ` [PATCH 10/19] clk: eyeq: skip post-divisor when computing pll divisor Benoît Monin
2025-09-03 12:47 ` [PATCH 11/19] clk: eyeq: rename the parent field to parent_idx Benoît Monin
2025-09-03 12:47 ` [PATCH 12/19] clk: eyeq: lookup parent clock by name Benoît Monin
2025-09-03 12:47 ` [PATCH 13/19] clk: eyeq: prefix the PLL registers with the PLL type Benoît Monin
2025-09-03 12:47 ` [PATCH 14/19] clk: eyeq: rename the reg64 field of eqc_pll Benoît Monin
2025-09-03 12:47 ` [PATCH 15/19] clk: eyeq: add a type for the PLL Benoît Monin
2025-09-03 12:47 ` [PATCH 16/19] clk: eyeq: add two PLL types Benoît Monin
2025-09-03 12:47 ` [PATCH 17/19] clk: eyeq: add a parent field to the pll Benoît Monin
2025-09-03 12:47 ` [PATCH 18/19] clk: eyeq: add an optional clk_div_table to divider Benoît Monin
2025-09-03 12:47 ` [PATCH 19/19] clk: eyeq: add eyeQ7H compatibles Benoît Monin

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