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Mon, 25 Mar 2024 07:01:15 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42P71EqO001013 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Mar 2024 07:01:14 GMT Received: from [10.216.57.55] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 25 Mar 2024 00:01:07 -0700 Message-ID: <10f46c19-4d02-4af6-a6b0-1549371d7be6@quicinc.com> Date: Mon, 25 Mar 2024 12:30:52 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 RESEND 1/6] dt-bindings: clock: qcom: Add SM8650 video clock controller Content-Language: en-US To: Dmitry Baryshkov CC: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Vladimir Zapolskiy , , , , , Taniya Das , Satya Priya Kakitapalli , Ajit Pandey , Imran Shaik , Krzysztof Kozlowski References: <20240321092529.13362-1-quic_jkona@quicinc.com> <20240321092529.13362-2-quic_jkona@quicinc.com> <725471b1-46a9-43b0-bede-33f01c953d51@quicinc.com> From: Jagadeesh Kona In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: fe2XdN_i5YtJxtzsJjYa7kAgPZ8cv9X8 X-Proofpoint-GUID: fe2XdN_i5YtJxtzsJjYa7kAgPZ8cv9X8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-25_04,2024-03-21_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 mlxscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 adultscore=0 mlxlogscore=999 priorityscore=1501 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403250036 On 3/25/2024 12:08 PM, Dmitry Baryshkov wrote: > On Mon, 25 Mar 2024 at 08:08, Jagadeesh Kona wrote: >> >> >> >> On 3/21/2024 6:42 PM, Dmitry Baryshkov wrote: >>> On Thu, 21 Mar 2024 at 11:26, Jagadeesh Kona wrote: >>>> >>>> Extend device tree bindings of SM8450 videocc to add support >>>> for SM8650 videocc. While it at, fix the incorrect header >>>> include in sm8450 videocc yaml documentation. >>>> >>>> Signed-off-by: Jagadeesh Kona >>>> Reviewed-by: Krzysztof Kozlowski >>>> --- >>>> .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 4 +++- >>>> include/dt-bindings/clock/qcom,sm8450-videocc.h | 8 +++++++- >>>> 2 files changed, 10 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >>>> index bad8f019a8d3..79f55620eb70 100644 >>>> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >>>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >>>> @@ -8,18 +8,20 @@ title: Qualcomm Video Clock & Reset Controller on SM8450 >>>> >>>> maintainers: >>>> - Taniya Das >>>> + - Jagadeesh Kona >>>> >>>> description: | >>>> Qualcomm video clock control module provides the clocks, resets and power >>>> domains on SM8450. >>>> >>>> - See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h >>>> + See also:: include/dt-bindings/clock/qcom,sm8450-videocc.h >>> >>> This almost pleads to go to a separate patch. Fixes generally should >>> be separated from the rest of the changes. >>> >> >> Thanks Dmitry for your review. >> >> Sure, will separate this into a separate patch in next series. >> >>>> >>>> properties: >>>> compatible: >>>> enum: >>>> - qcom,sm8450-videocc >>>> - qcom,sm8550-videocc >>>> + - qcom,sm8650-videocc >>>> >>>> reg: >>>> maxItems: 1 >>>> diff --git a/include/dt-bindings/clock/qcom,sm8450-videocc.h b/include/dt-bindings/clock/qcom,sm8450-videocc.h >>>> index 9d795adfe4eb..ecfebe52e4bb 100644 >>>> --- a/include/dt-bindings/clock/qcom,sm8450-videocc.h >>>> +++ b/include/dt-bindings/clock/qcom,sm8450-videocc.h >>>> @@ -1,6 +1,6 @@ >>>> /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >>>> /* >>>> - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. >>>> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. >>>> */ >>>> >>>> #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H >>>> @@ -19,6 +19,11 @@ >>>> #define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9 >>>> #define VIDEO_CC_PLL0 10 >>>> #define VIDEO_CC_PLL1 11 >>>> +#define VIDEO_CC_MVS0_SHIFT_CLK 12 >>>> +#define VIDEO_CC_MVS0C_SHIFT_CLK 13 >>>> +#define VIDEO_CC_MVS1_SHIFT_CLK 14 >>>> +#define VIDEO_CC_MVS1C_SHIFT_CLK 15 >>>> +#define VIDEO_CC_XO_CLK_SRC 16 >>> >>> Are these values applicable to sm8450? >>> >> >> No, the shift clocks above are part of SM8650 only. To reuse the >> existing SM8550 videocc driver for SM8650 and to register these shift >> clocks for SM8650, I added them here. > > At least it deserves a comment. > Yes, will add the comment in next series. Thanks, Jagadeesh >> >>>> >>>> /* VIDEO_CC power domains */ >>>> #define VIDEO_CC_MVS0C_GDSC 0 >>>> @@ -34,5 +39,6 @@ >>>> #define CVP_VIDEO_CC_MVS1C_BCR 4 >>>> #define VIDEO_CC_MVS0C_CLK_ARES 5 >>>> #define VIDEO_CC_MVS1C_CLK_ARES 6 >>>> +#define VIDEO_CC_XO_CLK_ARES 7 >>>> >>>> #endif >>>> -- >>>> 2.43.0 >>>> >>>> >>> >>> > > >