Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845

[Taniya Das <tdas@codeaurora.org>]

Hello Stephen,

Thanks for your review comments.

On 7/9/2018 5:24 AM, Stephen Boyd wrote:
> Quoting Taniya Das (2018-06-23 07:19:27)
>> diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
>> new file mode 100644
>> index 0000000..af437e0
>> --- /dev/null
>> +++ b/drivers/clk/qcom/dispcc-sdm845.c
>> @@ -0,0 +1,674 @@
>> +// SPDX-License-Identifier: GPL-2.0
> [...]
>> +static struct clk_alpha_pll disp_cc_pll0 = {
>> +       .offset = 0x0,
>> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>> +       .clkr = {
>> +               .hw.init = &(struct clk_init_data){
>> +                       .name = "disp_cc_pll0",
>> +                       .parent_names = (const char *[]){ "bi_tcxo" },
>> +                       .num_parents = 1,
>> +                       .ops = &clk_alpha_pll_fabia_ops,
>> +               },
>> +       },
>> +};
>> +
>> +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
>> +       .cmd_rcgr = 0x20d0,
>> +       .mnd_width = 0,
>> +       .hid_width = 5,
>> +       .parent_map = disp_cc_parent_map_0,
>> +       .clkr.hw.init = &(struct clk_init_data){
>> +               .name = "disp_cc_mdss_byte0_clk_src",
>> +               .parent_names = disp_cc_parent_names_0,
>> +               .num_parents = 4,
>> +               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> 
> Why is there the no cache flag? Last time I asked I don't think I got
> any answer, and there isn't a comment here so please at least add a
> comment to the code so we don't forget.
>

I think you missed my comment from the earlier email. I would add the 
comment and submit again.

 > Why is the nocache flag needed? Applies to all clks in this file.
 >

This flag is required for all RCGs whose PLLs are controlled outside the 
clock controller. The display code would require the recalculated rate 
always.

>> +               .ops = &clk_byte2_ops,
>> +       },
>> +};
>> +
>> +static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
>> +       .cmd_rcgr = 0x20ec,
>> +       .mnd_width = 0,
>> +       .hid_width = 5,
>> +       .parent_map = disp_cc_parent_map_0,
>> +       .clkr.hw.init = &(struct clk_init_data){
>> +               .name = "disp_cc_mdss_byte1_clk_src",
>> +               .parent_names = disp_cc_parent_names_0,
>> +               .num_parents = 4,
>> +               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
>> +               .ops = &clk_byte2_ops,
>> +       },
>> +};
>> +
>> +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
>> +       F(19200000, P_BI_TCXO, 1, 0, 0),
>> +       { }
>> +};
>> +
>> +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
>> +       .cmd_rcgr = 0x2108,
>> +       .mnd_width = 0,
>> +       .hid_width = 5,
>> +       .parent_map = disp_cc_parent_map_0,
>> +       .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
>> +       .clkr.hw.init = &(struct clk_init_data){
>> +               .name = "disp_cc_mdss_esc0_clk_src",
>> +               .parent_names = disp_cc_parent_names_0,
>> +               .num_parents = 4,
>> +               .ops = &clk_rcg2_ops,
>> +       },
>> +};
>> +
>> +static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
>> +       .cmd_rcgr = 0x2120,
>> +       .mnd_width = 0,
>> +       .hid_width = 5,
>> +       .parent_map = disp_cc_parent_map_0,
>> +       .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
>> +       .clkr.hw.init = &(struct clk_init_data){
>> +               .name = "disp_cc_mdss_esc1_clk_src",
>> +               .parent_names = disp_cc_parent_names_0,
>> +               .num_parents = 4,
>> +               .ops = &clk_rcg2_ops,
>> +       },
>> +};
>> +
> [...]
>> +
>> +MODULE_LICENSE("GPL v2");
> 
> MODULE_DESCRIPTION?
> 

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