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([2001:a61:34c9:ea01:14b4:7ed9:5135:9381]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b55f689sm140833345e9.16.2024.10.28.07.01.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2024 07:01:45 -0700 (PDT) Message-ID: <113e98edbff4501556e35698431080364e134233.camel@gmail.com> Subject: Re: [PATCH 1/2] dt-bindings: clock: axi-clkgen: include AXI clk From: Nuno =?ISO-8859-1?Q?S=E1?= To: Conor Dooley Cc: Nuno Sa , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lars-Peter Clausen Date: Mon, 28 Oct 2024 15:01:44 +0100 In-Reply-To: <20241025-numerate-quirk-b622c5acdacc@spud> References: <20241023-axi-clkgen-fix-axiclk-v1-0-980a42ba51c3@analog.com> <20241023-axi-clkgen-fix-axiclk-v1-1-980a42ba51c3@analog.com> <20241023-tucking-pacific-7360480bcb61@spud> <1e0097f6a15f47c173cb207e369909c1cb5943f9.camel@gmail.com> <20241024-wildfowl-pushiness-d5f46c9c538a@spud> <8b853ad3964cd2b7dafc225d4037ddbf11ebb2d3.camel@gmail.com> <20241025-numerate-quirk-b622c5acdacc@spud> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-2.fc40) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2024-10-25 at 17:47 +0100, Conor Dooley wrote: > On Fri, Oct 25, 2024 at 08:56:34AM +0200, Nuno S=C3=A1 wrote: > > On Thu, 2024-10-24 at 17:13 +0100, Conor Dooley wrote: > > > On Thu, Oct 24, 2024 at 02:35:37PM +0200, Nuno S=C3=A1 wrote: > > > > On Wed, 2024-10-23 at 17:30 +0100, Conor Dooley wrote: > > > > > On Wed, Oct 23, 2024 at 04:56:54PM +0200, Nuno Sa wrote: > > > > > > In order to access the registers of the HW, we need to make sur= e that > > > > > > the AXI bus clock is enabled. Hence let's increase the number o= f clocks > > > > > > by one. > > > > > >=20 > > > > > > In order to keep backward compatibility, the new axi clock must= be the > > > > > > last phandle in the array. To make the intent clear, a non mand= atory > > > > > > clock-names property is also being added. > > > > >=20 > > > > > Hmm, I'm not sure. I think clock-names actually may need to be ma= ndatory > > > > > here, as otherwise you'll not what the second clock is. The drive= r would > > > > > have to interpret no clock-names meaning clock 2 was clkin2. > > > > >=20 > > > > >=20 > > > >=20 > > > > So the way things are now is that we just get the parents count wit= h > > > > of_clk_get_parent_count() and then get the names with > > > > of_clk_get_parent_name() > > > > and > > > > this is given into 'struct clk_init_data'. So they are effectively > > > > clk_parents of > > > > the > > > > clock we're registering and as you can see clock-names does not rea= lly > > > > matter. > > > > What > > > > I'm trying to do is to keep this and still allow to get the AXI bus= clock > > > > which > > > > is > > > > something we should get and enable and not rely on others to do it.= The idea > > > > is > > > > then > > > > to add the axi bus clock as the last one in the clocks property and= I will > > > > get it > > > > by > > > > index with of_clk_get(). The rest pretty much remains the same and = we just > > > > need > > > > to > > > > decrement by one the number of parent clocks as the axi clock is no= t really a > > > > parent > > > > of our output clock. > > >=20 > > > I mean, if it works, and you can always disambiguate between whether = or > > > not someone has two clkins or one clkin and the axi clock, then > > > Acked-by: Conor Dooley > >=20 > > The assumption is that the axi clock is the last one in the phandle arr= ay. But > > your > > comment made me think a bit more about this and I do see a possible pro= blem if we > > run > > old DTs against a kernel with this patch. We have two possibilities: > >=20 > > 1) DT only with one parent clock; > > 2) DT with two parent clocks; > >=20 > > 1) is "fine" as it would now fail to probe. 2) is more problematic as w= e would > > assume > > the second parent to be the axi_bus clock so effectively not fixing any= thing and > > silently probing with a broken setup. > >=20 > > So yeah, I think I overthinked the backward compatibility thing. I mean= , in > > theory, > > all old DTs are not correct and should be fixed by including the axi_cl= k. And if > > we > > now enforce clock-names we at least get probe errors right away making = it clear > > (which is far better from silently breaking after probe). > >=20 > > Given the above, it should be fine to just enforce clock-names now, rig= ht? >=20 > I think you need to enforce clock-names in the binding and take > !clock-names and 2 clocks to mean that the second one is a clkin. I > think that's a better solution than failing to probe for all extant > devicestrees. Ok, so IIUC, you mean leaving old DTs as of today and relying on someone el= se to enable the axi clock (if it was not enabled they would have noticed by now)= . And only take care of the bus clock when clock-names is provided? - Nuno S=C3=A1