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Subject: Re: [PATCH 1/4] clk: renesas: rzv2h-cpg: Add support for coupled clock
From: Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>, Biju Das <biju.das.au@gmail.com>
To: Biju Das <biju.das.jz@bp.renesas.com>, Geert Uytterhoeven <geert+renesas@glider.be>, Michael Turquette <mturquette@baylibre.com>
Date: Wed, 05 Mar 2025 15:16:46 -0800
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Quoting Biju Das (2025-03-03 03:04:19)
> The spi and spix2 clk share same bit for clock gating. Add support
> for coupled clock with checking the monitor bit for both the clocks.

Could you add an intermediate parent clk of both spi and spix2 that only
handles the enable bit for clock gating? Then the enable count handling
would be in the core clk code.