From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BCE944C77; Thu, 24 Apr 2025 15:31:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745508684; cv=none; b=a8Gt7NerOQjgz9IRYee7LJpIRrCE/MAia2TmsbJBTM9vwBhMaFmlO55oD5/vWVrRJnGin0DT5M0HO4R4mFWmAEO1rgMktWGo04aAoRFWhCruubi+Z3DMj+21P40PgFoFjVfIXxEzq6VCP9czCngUdnAbU0nmU7GCnNFWw7b4zoc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745508684; c=relaxed/simple; bh=ggnqC+sRhooCK5oEVXjCBnDM2VOyq0O6DNpXNKZNRF8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=TQAChfY7hIQkW3+PY89C5LIm4dq+odpPkdSagb1R7kccJwHQZCohhqT19uyY8SkDff5YdDtCu6pT+34xuGWTWOsaFBgUaTfPMrHQGeo+2C55c8Yqtlw3HV4lteW7+4ZHfwS+dGYsNGXqTiJsc8JcRYX38kN6dNcB8cQmcgYeG6M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=X4CBKwly; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="X4CBKwly" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 278D1C4CEE3; Thu, 24 Apr 2025 15:31:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745508683; bh=ggnqC+sRhooCK5oEVXjCBnDM2VOyq0O6DNpXNKZNRF8=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=X4CBKwly6dh6eQb/Hq2ar0IvUVwlmhzEkl43VEf2jmIptexk12GVwoq+HWxHPsNGH 5cAUNxTb/Q7gfF2oChV35sdQpHx7aLpYs3XmO6989GRDlHe2+A1e7Y2Q0vUVUmMInu Vl4ogRz8gjnCkT+MRPAzIBYQcZP+5uDtU6a38u6cmti+0PfNOLMod5bYQZn2xB3Qyw zlTmTtRbdqXiQTm0u4kGgYICzkoypjWeMfnTnDfyJ1X6UCRgUgE9ZKsev4C/7iLcoD Tn2jUze8MVlhS0Q90qAiMp8Ll3d0d9BkUKtGgT/kqj52gZoK0UcdQxx3M3rkmwfhuf Ux/AC95mz54ug== Message-ID: <1355515c-477e-455c-a910-a69dc1b77f07@kernel.org> Date: Thu, 24 Apr 2025 17:31:18 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 06/10] dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20250424-qcs615-mm-v7-clock-controllers-v8-0-bacad5b3659a@quicinc.com> <20250424-qcs615-mm-v7-clock-controllers-v8-6-bacad5b3659a@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 24/04/2025 11:33, Taniya Das wrote: > Add DT bindings for the Graphics clock on QCS615 platforms. Add the > relevant DT include definitions as well. > > Signed-off-by: Taniya Das > --- > .../bindings/clock/qcom,qcs615-gpucc.yaml | 49 ++++++++++++++++++++++ > include/dt-bindings/clock/qcom,qcs615-gpucc.h | 39 +++++++++++++++++ > 2 files changed, 88 insertions(+) > Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof