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From: Andre Przywara <andre.przywara@arm.com>
To: Maxime Ripard <maxime.ripard@free-electrons.com>,
	Emilio Lopez <emilio@elopez.com.ar>,
	Michael Turquette <mturquette@baylibre.com>,
	Chen-Yu Tsai <wens@csie.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>,
	linux-clk@vger.kernel.org, linux-sunxi@googlegroups.com,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 0/3] clk: sunxi: error checking on clock setup
Date: Tue, 16 Feb 2016 10:46:05 +0000	[thread overview]
Message-ID: <1455619568-1906-1-git-send-email-andre.przywara@arm.com> (raw)

Setting up the clocks properly is quite critical to the system's
operation, but currently our error handling is not very verbose.
This series adds error handling and reporting to the sunxi clocks,
so that any errors are correctly detected and reported. Also previous
actions are rolled back in case something went wrong.
This proves to be helpful in debugging clock tree issues,
especially when adding support for new SoCs.
I tested this on a BananaPi by deliberately misspelling
"clock-output-names". The resulting kernel crash in
sun4i_timer_interrupt is totally misleading, but now there is a line
in the dmesg before saying:
=======
sunxi_divider_clk_setup: could not read clock-output-names for "apb0"
=======

This applies on top of Maxime's sunxi/for-next branch.

Changes v1 .. v2:
- in all three patches:
  - use of_clock_full_name() instead of node->name
  - don't report the uninitialized clk_name
  - handle error in final check in if-clause

Andre Przywara (3):
  clk: sunxi: improve mux_clk error handling and reporting
  clk: sunxi: improve divider_clk error handling and reporting
  clk: sunxi: Improve divs_clk error handling and reporting

 drivers/clk/sunxi/clk-sunxi.c | 75 ++++++++++++++++++++++++++++++++++++-------
 1 file changed, 63 insertions(+), 12 deletions(-)

-- 
2.6.4


             reply	other threads:[~2016-02-16 10:46 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-16 10:46 Andre Przywara [this message]
2016-02-16 10:46 ` [PATCH v2 1/3] clk: sunxi: improve mux_clk error handling and reporting Andre Przywara
2016-02-16 10:46 ` [PATCH v2 2/3] clk: sunxi: improve divider_clk " Andre Przywara
2016-02-16 10:46 ` [PATCH v2 3/3] clk: sunxi: Improve divs_clk " Andre Przywara
2016-02-22  3:45 ` [PATCH v2 0/3] clk: sunxi: error checking on clock setup Maxime Ripard

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