From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Peter De Schrijver To: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , "Stephen Boyd" , Thierry Reding , Jonathan Hunter , , , Subject: [PATCH 03/14] clk: tegra: disable SSC for PLL_D2 Date: Tue, 25 Jul 2017 13:34:04 +0300 Message-ID: <1500978856-5981-4-git-send-email-pdeschrijver@nvidia.com> In-Reply-To: <1500978856-5981-1-git-send-email-pdeschrijver@nvidia.com> References: <1500978856-5981-1-git-send-email-pdeschrijver@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain Return-Path: pdeschrijver@nvidia.com List-ID: PLLD2 is used for HDMI which does not allowe Spread Spectrum clocking. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra210.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 1024e85..facd6ee 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -146,7 +146,7 @@ #define PLLD_SDM_EN_MASK BIT(16) #define PLLD2_SDM_EN_MASK BIT(31) -#define PLLD2_SSC_EN_MASK BIT(30) +#define PLLD2_SSC_EN_MASK 0 #define PLLDP_SS_CFG 0x598 #define PLLDP_SDM_EN_MASK BIT(31) -- 1.9.1