From: Abhishek Sahu <absahu@codeaurora.org>
To: Stephen Boyd <sboyd@codeaurora.org>,
Michael Turquette <mturquette@baylibre.com>
Cc: Andy Gross <andy.gross@linaro.org>,
David Brown <david.brown@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Abhishek Sahu <absahu@codeaurora.org>
Subject: [PATCH 03/11] clk: qcom: ipq8074: fix missing GPLL0 divider width
Date: Tue, 26 Sep 2017 17:53:56 +0530 [thread overview]
Message-ID: <1506428644-2996-4-git-send-email-absahu@codeaurora.org> (raw)
In-Reply-To: <1506428644-2996-1-git-send-email-absahu@codeaurora.org>
GPLL0 uses 4 bits post divider which should be specified
in clock driver structure.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq8074.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 0f735d3..f9b6d51 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -82,6 +82,7 @@ enum {
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x21000,
+ .width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_names = (const char *[]){
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2017-09-26 12:23 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-26 12:23 [PATCH 00/11] Add remaining clocks for QCOM IPQ8074 Abhishek Sahu
2017-09-26 12:23 ` [PATCH 01/11] clk: qcom: add read-only divider operations Abhishek Sahu
2017-09-26 12:23 ` [PATCH 02/11] clk: qcom: add parent map for regmap mux Abhishek Sahu
2017-09-26 12:23 ` Abhishek Sahu [this message]
2017-09-26 12:23 ` [PATCH 04/11] dt-bindings: clock: qcom: add remaining clocks for IPQ8074 Abhishek Sahu
2017-09-26 12:23 ` [PATCH 05/11] clk: qcom: ipq8074: add remaining PLL’s Abhishek Sahu
2017-09-26 12:23 ` [PATCH 06/11] clk: qcom: ipq8074: add PCIE, USB and SDCC clocks Abhishek Sahu
2017-09-26 12:24 ` [PATCH 07/11] clk: qcom: ipq8074: add NSS clocks Abhishek Sahu
2017-09-26 12:24 ` [PATCH 08/11] clk: qcom: ipq8074: add NSS ethernet port clocks Abhishek Sahu
2017-09-26 12:24 ` [PATCH 09/11] clk: qcom: ipq8074: add GP and Crypto clocks Abhishek Sahu
2017-09-26 12:24 ` [PATCH 10/11] dt-bindings: clock: qcom: add misc resets for PCIE and NSS Abhishek Sahu
2017-09-26 12:24 ` [PATCH 11/11] clk: qcom: ipq8074: " Abhishek Sahu
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