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From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: <linux-clk@vger.kernel.org>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Subject: [RFC 05/14] memory: tegra: mc: Introduce helpers
Date: Sat, 15 Sep 2018 00:48:06 +0300	[thread overview]
Message-ID: <1536961695-27809-6-git-send-email-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com>

Introduce a few helper functions to lookup a timing for a given rate and
modify MC register field. These will be useful when adding support for
updating the latency allowance (LA) registers when scaling the EMC clock.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/memory/tegra/mc.c | 30 +++++++++++++++++++++++-------
 1 file changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index a4803ac..af4bf29 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -73,6 +73,17 @@
 };
 MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
 
+static void mc_modifyl(struct tegra_mc *mc, u32 reg, u32 value, u8 shift,
+		       u8 mask)
+{
+	u32 val;
+
+	val = readl(mc->regs + reg);
+	val &= ~(mask << shift);
+	val |= (value & mask) << shift;
+	writel(val, mc->regs + reg);
+}
+
 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
 {
 	unsigned long long tick;
@@ -91,18 +102,14 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
 	/* write latency allowance defaults */
 	for (i = 0; i < mc->soc->num_clients; i++) {
 		const struct tegra_mc_la *la = &mc->soc->clients[i].la;
-		u32 value;
-
-		value = readl(mc->regs + la->reg);
-		value &= ~(la->mask << la->shift);
-		value |= (la->def & la->mask) << la->shift;
-		writel(value, mc->regs + la->reg);
+		mc_modifyl(mc, la->reg, la->def, la->shift, la->mask);
 	}
 
 	return 0;
 }
 
-void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
+static struct tegra_mc_timing *find_mc_timing(struct tegra_mc *mc,
+					      unsigned long rate)
 {
 	unsigned int i;
 	struct tegra_mc_timing *timing = NULL;
@@ -114,6 +121,15 @@ void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
 		}
 	}
 
+	return timing;
+}
+
+void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
+{
+	unsigned int i;
+	struct tegra_mc_timing *timing = NULL;
+
+	timing = find_mc_timing(mc, rate);
 	if (!timing) {
 		dev_err(mc->dev, "no memory timing registered for rate %lu\n",
 			rate);
-- 
1.9.1

  parent reply	other threads:[~2018-09-15  3:13 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-14 21:48 [RFC 00/14] Tegra210 EMC scaling Peter De Schrijver
2018-09-14 21:48 ` [RFC 01/14] memory: tegra: mc: Add Tegra210 MC emem registers Peter De Schrijver
2018-09-14 21:48 ` [RFC 02/14] clk: tegra: rename emc timing functions Peter De Schrijver
2018-09-14 21:48 ` [RFC 03/14] clk: tegra: emc: simplify parent matching Peter De Schrijver
2018-09-14 21:48 ` [RFC 04/14] clk: tegra: emc: prepare for Tegra210 parent table Peter De Schrijver
2018-09-14 21:48 ` Peter De Schrijver [this message]
2018-09-14 21:48 ` [RFC 06/14] memory: tegra: mc: Add support for scaled LA Peter De Schrijver
2018-09-14 21:48 ` [RFC 07/14] memory: tegra: scaled LA register for Tegra210 Peter De Schrijver
2018-09-14 21:48 ` [RFC 08/14] clk: tegra: clock changes for emc scaling Peter De Schrijver
2018-09-14 21:48 ` [RFC 09/14] memory: tegra: Add definitions shared by Tegra210 EMC scaling code Peter De Schrijver
2018-09-14 21:48 ` [RFC 10/14] memory: tegra: Add Tegra210 EMC scaling sequence Peter De Schrijver
2018-09-14 21:48 ` [RFC 11/14] memory: tegra: parse DT and costruct timing tables Peter De Schrijver
2018-09-14 21:48 ` [RFC 12/14] memory: tegra: Tegra210 EMC memory driver Peter De Schrijver
2018-09-14 21:48 ` [RFC 13/14] memory: tegra: enable Tegra210 EMC scaling driver Peter De Schrijver
2018-09-14 21:48 ` [RFC 14/14] dt-bindings: tegra: Add Tegra210 EMC binding Peter De Schrijver

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