Re: [PATCH v1 02/11] clk: mediatek: add new member to mtk_pll_data

Stephen Boyd
2018-11-21T08:03:32Z

Quoting Weiyi Lu (2018-11-19 19:51:20)
> On Tue, 2018-11-13 at 08:18 -0800, Nicolas Boichat wrote:
> > On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> > > @@ -138,9 +140,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> > > static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
> > > u32 freq, u32 fin)
> > > {
> > > - unsigned long fmin = 1000 * MHZ;
> > > + unsigned long fmin = pll->data->fmin ? pll->data->fmin : 1000 * MHZ;
> >
> > I'd put parentheses around (1000 * MHZ), to avoid the need to think
> > about precedence...
> >
>
> OK, thanks for the suggestion. will add in next version

Better style would be to not use a ternary statement for anything like
this and have an if condition instead.