From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BD20C43387 for ; Thu, 17 Jan 2019 08:34:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3D4862063F for ; Thu, 17 Jan 2019 08:34:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730316AbfAQIet (ORCPT ); Thu, 17 Jan 2019 03:34:49 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:39664 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726986AbfAQIet (ORCPT ); Thu, 17 Jan 2019 03:34:49 -0500 X-UUID: 1e120a4f7c444726ad323d805ab44dd3-20190117 X-UUID: 1e120a4f7c444726ad323d805ab44dd3-20190117 Received: from mtkcas32.mediatek.inc [(172.27.4.250)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 174804564; Thu, 17 Jan 2019 16:34:37 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 17 Jan 2019 16:34:36 +0800 Received: from [10.16.6.141] (10.16.6.141) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 17 Jan 2019 16:34:35 +0800 Message-ID: <1547714075.4664.1.camel@mszsdaap41> Subject: Re: [PATCH 4/9] drm/mediatek: fix the rate and divder of hdmi phy for MT2701 From: Chunhui Dai To: Matthias Brugger CC: --to=Michael Turquette , Stephen Boyd , CK Hu , , Philipp Zabel , David Airlie , Sean Wang , Ryder Lee , Colin Ian King , , , , , , , , , Date: Thu, 17 Jan 2019 16:34:35 +0800 In-Reply-To: References: <1546585439-30455-1-git-send-email-chunhui.dai@mediatek.com> <1546585439-30455-5-git-send-email-chunhui.dai@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Wed, 2019-01-09 at 17:54 +0100, Matthias Brugger wrote: > > On 04/01/2019 08:03, chunhui dai wrote: > > fix the rate and divder of hdmi phy for MT2701. > > This is a bug? Then we would need a fixes tag. yes, we would add the tag in V2. > Otherwise you should explain in the commit, that you need to change the > calculation due to previous commits. > > Regards, > Matthias > > > > > Signed-off-by: chunhui dai > > --- > > drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > > index a28a32d..10b6235 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > > +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > > @@ -114,8 +114,8 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > > > > if (rate <= 64000000) > > pos_div = 3; > > - else if (rate <= 12800000) > > - pos_div = 1; > > + else if (rate <= 128000000) > > + pos_div = 2; > > else > > pos_div = 1; > > > >