From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD8BAC43381 for ; Mon, 25 Feb 2019 06:14:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B602D2084D for ; Mon, 25 Feb 2019 06:14:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726666AbfBYGO1 (ORCPT ); Mon, 25 Feb 2019 01:14:27 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:16913 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726436AbfBYGO1 (ORCPT ); Mon, 25 Feb 2019 01:14:27 -0500 X-UUID: cd8873c7bf6a45629b353363b926c5b8-20190225 X-UUID: cd8873c7bf6a45629b353363b926c5b8-20190225 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1096320972; Mon, 25 Feb 2019 14:14:17 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 25 Feb 2019 14:14:15 +0800 Received: from [172.21.84.99] (172.21.84.99) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 25 Feb 2019 14:14:15 +0800 Message-ID: <1551075255.1446.8.camel@mtksdccf07> Subject: Re: [PATCH v1 2/2] clk: mediatek: correct cpu clock name for MT8173 SoC From: Seiya Wang To: Stephen Boyd CC: Mark Rutland , Matthias Brugger , Michael Turquette , "Rob Herring" , , , , , Date: Mon, 25 Feb 2019 14:14:15 +0800 In-Reply-To: <155078662163.77512.15925700437277835877@swboyd.mtv.corp.google.com> References: <20190211071555.31430-1-seiya.wang@mediatek.com> <20190211071555.31430-2-seiya.wang@mediatek.com> <155078662163.77512.15925700437277835877@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Thu, 2019-02-21 at 14:03 -0800, Stephen Boyd wrote: > Quoting Seiya Wang (2019-02-10 23:15:55) > > Change cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72. > > > > Signed-off-by: Seiya Wang > > --- > > Acked-by: Stephen Boyd > > I'm guessing I can't apply this patch because the define is renamed > which would break older DTs. Another option would be to just add another > define and mark the old define as deprecated and unsupported. Then I > could apply the patch to clk tree. Thank you so much for your advice. We will update the patches and resend soon.