From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 852F0C10F0E for ; Tue, 9 Apr 2019 05:39:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5DDEE2083E for ; Tue, 9 Apr 2019 05:39:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727305AbfDIFjh (ORCPT ); Tue, 9 Apr 2019 01:39:37 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:18327 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727233AbfDIFjg (ORCPT ); Tue, 9 Apr 2019 01:39:36 -0400 X-UUID: ce7e1da9f77548d9a12a70dc19e48fdd-20190409 X-UUID: ce7e1da9f77548d9a12a70dc19e48fdd-20190409 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2144505031; Tue, 09 Apr 2019 13:39:29 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 9 Apr 2019 13:39:23 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 9 Apr 2019 13:39:23 +0800 Message-ID: <1554788363.336.5.camel@mtksdaap41> Subject: Re: [PATCH V9 1/5] drm/mediatek: remove flag CLK_SET_RATE_PARENT for mt2701 hdmi phy to not propagate rate change to parent From: CK Hu To: wangyan wang CC: Michael Turquette , Stephen Boyd , Matthias Brugger , "Philipp Zabel" , David Airlie , "Daniel Vetter" , chunhui dai , "Colin Ian King" , Sean Wang , "Ryder Lee" , , , , , , Date: Tue, 9 Apr 2019 13:39:23 +0800 In-Reply-To: <20190409030756.69496-2-wangyan.wang@mediatek.com> References: <20190409030756.69496-1-wangyan.wang@mediatek.com> <20190409030756.69496-2-wangyan.wang@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi, Wangyan: On Tue, 2019-04-09 at 11:07 +0800, wangyan wang wrote: > From: Wangyan Wang > > This is the first step to make MT2701 hdmi stable. > The parent rate of hdmi phy had set by DPI driver. > We should not set or change the parent rate of MT2701 hdmi phy, > as a result we should remove the flags of "CLK_SET_RATE_PARENT" > from the clock of MT2701 hdmi phy. > > Signed-off-by: Wangyan Wang > --- > drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 13 +++++-------- > drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 1 + > drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 1 + > drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 1 + > 4 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c > index 4ef9c57ffd44..13bbaf997819 100644 > --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c > @@ -110,13 +110,11 @@ mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy) > return NULL; > } > > -static void mtk_hdmi_phy_clk_get_ops(struct mtk_hdmi_phy *hdmi_phy, > - const struct clk_ops **ops) > +static void mtk_hdmi_phy_clk_get_data(struct mtk_hdmi_phy *hdmi_phy, > + struct clk_init_data *clk_init) I think you've tried to align, but the result looks not aligned. Make sure your editor have equal size for each character and and the 'tab' length is 8 character. Regards, CK > { > - if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_clk_ops) > - *ops = hdmi_phy->conf->hdmi_phy_clk_ops; > - else > - dev_err(hdmi_phy->dev, "Failed to get clk ops of phy\n"); > + clk_init->flags = hdmi_phy->conf->flags; > + clk_init->ops = hdmi_phy->conf->hdmi_phy_clk_ops; > } > > static int mtk_hdmi_phy_probe(struct platform_device *pdev) > @@ -129,7 +127,6 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev) > struct clk_init_data clk_init = { > .num_parents = 1, > .parent_names = (const char * const *)&ref_clk_name, > - .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, > }; > > struct phy *phy; > @@ -167,7 +164,7 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev) > hdmi_phy->dev = dev; > hdmi_phy->conf = > (struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev); > - mtk_hdmi_phy_clk_get_ops(hdmi_phy, &clk_init.ops); > + mtk_hdmi_phy_clk_get_data(hdmi_phy, &clk_init); > hdmi_phy->pll_hw.init = &clk_init; > hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw); > if (IS_ERR(hdmi_phy->pll)) { > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h > index f39b1fc66612..0045824c1be9 100644 > --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h > @@ -21,6 +21,7 @@ struct mtk_hdmi_phy; > > struct mtk_hdmi_phy_conf { > bool tz_disabled; > + unsigned long flags; > const struct clk_ops *hdmi_phy_clk_ops; > void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy); > void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy); > diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > index fcc42dc6ea7f..67a814649e19 100644 > --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > @@ -202,6 +202,7 @@ static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) > > struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = { > .tz_disabled = true, > + .flags = CLK_SET_RATE_GATE, > .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops, > .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds, > .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds, > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > index ed5916b27658..f44066875dcd 100644 > --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > @@ -309,6 +309,7 @@ static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) > } > > struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = { > + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, > .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops, > .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds, > .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,