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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 9qVoZZG9qfb0pC7AlSFNfPd5nLEQoDd6UHTuroCOC60N7AMzdXtZfdJuJHP9ldveoYg4BhmzUYSqxS8w4W+kR8m2BB25wdWtVxqrtSJTSYt7Uy/qs+MC5U6u6K3C9EqjRWoF9EG3xTFKeiTPf6DH75hmtBjKBG3DISjd7r2xJMo2IoNautdX1CBiFabPS3FfMmIm3VFiWk1efaeEjmTwL30WKSGL6KLxXCFOishdJ/fyMsBW9AQZMHb9i4rZ0UONeAVKK+djsukLK6NWoRYh2HwymOahh8iIHywphMd2OR7D7eQnWzrEPfgeFseiyI4Zo1eF410bH2FkT4k5f/HXgvwy5zm7vnF3LAPoWkzn+BV9KdnVRgjEAo5H70jfy86gjTC8Uv5GO8e927psUIpESBkPSD+3ZwXpkjcVa3LfMJ4= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7358983f-3931-4223-1bb2-08d74c9f3395 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Oct 2019 09:58:14.8763 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: E0zcoTYdvTYkivrYuDz9eDlTFfI48PZLPNRX6WXcQLGkuRJuwblg7YMu8x2bfXlMlgXJcVGEe+NzNKiFwH80oQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4177 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Peng Fan According Architecture definition guide, SYS_PLL1 is fixed at 800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed to register the clocks and drop code that could change the rate. Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8mm.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 04876ec66127..ae7321ab7837 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -34,8 +34,6 @@ static const char *dram_pll_bypass_sels[] =3D {"dram_pll"= , "dram_pll_ref_sel", }; static const char *gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_ref_sel"= , }; static const char *vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_ref_sel"= , }; static const char *arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_ref_sel"= , }; -static const char *sys_pll1_bypass_sels[] =3D {"sys_pll1", "sys_pll1_ref_s= el", }; -static const char *sys_pll2_bypass_sels[] =3D {"sys_pll2", "sys_pll2_ref_s= el", }; static const char *sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll3_ref_s= el", }; =20 /* CCM ROOT */ @@ -325,8 +323,6 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) clks[IMX8MM_GPU_PLL_REF_SEL] =3D imx_clk_mux("gpu_pll_ref_sel", base + 0x= 64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); clks[IMX8MM_VPU_PLL_REF_SEL] =3D imx_clk_mux("vpu_pll_ref_sel", base + 0x= 74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); clks[IMX8MM_ARM_PLL_REF_SEL] =3D imx_clk_mux("arm_pll_ref_sel", base + 0x= 84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - clks[IMX8MM_SYS_PLL1_REF_SEL] =3D imx_clk_mux("sys_pll1_ref_sel", base + = 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - clks[IMX8MM_SYS_PLL2_REF_SEL] =3D imx_clk_mux("sys_pll2_ref_sel", base + = 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); clks[IMX8MM_SYS_PLL3_REF_SEL] =3D imx_clk_mux("sys_pll3_ref_sel", base + = 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); =20 clks[IMX8MM_AUDIO_PLL1] =3D imx_clk_pll14xx("audio_pll1", "audio_pll1_ref= _sel", base, &imx_1443x_pll); @@ -336,8 +332,8 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) clks[IMX8MM_GPU_PLL] =3D imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", ba= se + 0x64, &imx_1416x_pll); clks[IMX8MM_VPU_PLL] =3D imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", ba= se + 0x74, &imx_1416x_pll); clks[IMX8MM_ARM_PLL] =3D imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", ba= se + 0x84, &imx_1416x_pll); - clks[IMX8MM_SYS_PLL1] =3D imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",= base + 0x94, &imx_1416x_pll); - clks[IMX8MM_SYS_PLL2] =3D imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",= base + 0x104, &imx_1416x_pll); + clks[IMX8MM_SYS_PLL1] =3D imx_clk_fixed("sys_pll1", 800000000); + clks[IMX8MM_SYS_PLL2] =3D imx_clk_fixed("sys_pll2", 1000000000); clks[IMX8MM_SYS_PLL3] =3D imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",= base + 0x114, &imx_1416x_pll); =20 /* PLL bypass out */ @@ -348,8 +344,6 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) clks[IMX8MM_GPU_PLL_BYPASS] =3D imx_clk_mux_flags("gpu_pll_bypass", base = + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SE= T_RATE_PARENT); clks[IMX8MM_VPU_PLL_BYPASS] =3D imx_clk_mux_flags("vpu_pll_bypass", base = + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SE= T_RATE_PARENT); clks[IMX8MM_ARM_PLL_BYPASS] =3D imx_clk_mux_flags("arm_pll_bypass", base = + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SE= T_RATE_PARENT); - clks[IMX8MM_SYS_PLL1_BYPASS] =3D imx_clk_mux_flags("sys_pll1_bypass", bas= e + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CL= K_SET_RATE_PARENT); - clks[IMX8MM_SYS_PLL2_BYPASS] =3D imx_clk_mux_flags("sys_pll2_bypass", bas= e + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), C= LK_SET_RATE_PARENT); clks[IMX8MM_SYS_PLL3_BYPASS] =3D imx_clk_mux_flags("sys_pll3_bypass", bas= e + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), C= LK_SET_RATE_PARENT); =20 /* PLL out gate */ @@ -360,8 +354,8 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) clks[IMX8MM_GPU_PLL_OUT] =3D imx_clk_gate("gpu_pll_out", "gpu_pll_bypass"= , base + 0x64, 11); clks[IMX8MM_VPU_PLL_OUT] =3D imx_clk_gate("vpu_pll_out", "vpu_pll_bypass"= , base + 0x74, 11); clks[IMX8MM_ARM_PLL_OUT] =3D imx_clk_gate("arm_pll_out", "arm_pll_bypass"= , base + 0x84, 11); - clks[IMX8MM_SYS_PLL1_OUT] =3D imx_clk_gate("sys_pll1_out", "sys_pll1_bypa= ss", base + 0x94, 11); - clks[IMX8MM_SYS_PLL2_OUT] =3D imx_clk_gate("sys_pll2_out", "sys_pll2_bypa= ss", base + 0x104, 11); + clks[IMX8MM_SYS_PLL1_OUT] =3D imx_clk_gate("sys_pll1_out", "sys_pll1", ba= se + 0x94, 11); + clks[IMX8MM_SYS_PLL2_OUT] =3D imx_clk_gate("sys_pll2_out", "sys_pll2", ba= se + 0x104, 11); clks[IMX8MM_SYS_PLL3_OUT] =3D imx_clk_gate("sys_pll3_out", "sys_pll3_bypa= ss", base + 0x114, 11); =20 /* SYS PLL fixed output */ --=20 2.16.4